Datasheet

Section 13 Timer Z
Rev.5.00 Nov. 02, 2005 Page 248 of 500
REJ09B0027-0500
7. Contention between GR Write and Input Capture: If an input capture signal is generated in the
T
2
state of a GR write cycle, the input capture operation has priority and the write to GR is not
performed. Figure 13.58 shows the timing in this case.
T 1 T 2
TCNT N
GR write cycle
GR address
Input capture
signal
WGR
(internal write signal)
Address bus
GR write data
GR
M
φ
Figure 13.58 Contention between GR Write and Input Capture