Datasheet

Section 17 EEPROM
Rev.5.00 Nov. 02, 2005 Page 280 of 418
REJ09B0028-0500
17.4 Operation
17.4.1 EEPROM Interface
The HD64N3694G has a multi-chip structure with two internal chips of the HD64F3694G (F-
ZTAT™ version) and 512-byte EEPROM. The HD6483694G has a multi-chip structure with two
internal chips of the HD6433694G (mask-ROM version) and 512-byte EEPROM.
The EEPROM interface is the I
2
C bus interface. This I
2
C bus is open to the outside, so the
communication with the external devices connected to the I
2
C bus can be made.
17.4.2 Bus Format and Timing
The I
2
C bus format and the I
2
C bus timing follow section 15.4.1, I
2
C Bus Format. The bus formats
specific for the EEPROM are the following two.
1. The EEPROM address is configured of two bytes, the write data is transferred in the order of
upper address and lower address from each MSB side.
2. The write data is transmitted from the MSB side.
The bus format and bus timing of the EEPROM are shown in figure 17.2.
R/W ACK
SCL
SDA
Start
condition
Slave address
Upper memory
address
lower memory
address
Data Data
Stop
conditon
[Legend]
R/W: R/W code (0 is for a write and 1 is for a read),
ACK: acknowledge
ACK ACKACK ACK
112345678
A15 A8 A7 A0 D7 D0 D7 D0
9189 189 189 8
9
Figure 17.2 EEPROM Bus Format and Bus Timing
17.4.3 Start Condition
A high-to-low transition of the SDA input with the SCL input high is needed to generate the start
condition for starting read, write operation.