To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8/3694 Group are single-chip microcomputers made up of the high-speed H8/300H CPU employing Renesas Technology original architecture as their cores, and the peripheral functions required to configure a system. The H8/300H CPU has an instruction set that is compatible with the H8/300 CPU. Target Users: This manual was written for users who will be using the H8/3694 Group in the design of application systems.
5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8. If address breaks are set as being used by the E7 or E8, the address break control registers must not be accessed. 6. When the E7 or E8 is used, NMI is an input/output pin (open-drain in output mode), P85 and P87 are input pins, and P86 is an output pin. Related Manuals: The latest versions of all related manuals are available from our web site.
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Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 1.4 Features.................................................................................................................................. 1 Internal Block Diagram.......................................................................................................... 4 Pin Arrangement ..................................................................................
3.3 3.4 3.5 3.2.5 Wakeup Interrupt Flag Register (IWPR) ................................................................ 55 Reset Exception Handling.................................................................................................... 56 Interrupt Exception Handling .............................................................................................. 57 3.4.1 External Interrupts .................................................................................................. 57 3.
6.2 6.3 6.4 6.5 Mode Transitions and States of LSI..................................................................................... 80 6.2.1 Sleep Mode ............................................................................................................. 83 6.2.2 Standby Mode ......................................................................................................... 83 6.2.3 Subsleep Mode.............................................................................................
9.2 9.3 9.4 9.5 9.6 9.1.4 Port Pull-Up Control Register 1 (PUCR1)............................................................ 112 9.1.5 Pin Functions ........................................................................................................ 112 Port 2.................................................................................................................................. 114 9.2.1 Port Control Register 2 (PCR2) ......................................................................
11.3.2 Time Constant Registers A and B (TCORA, TCORB) ........................................ 139 11.3.3 Timer Control Register V0 (TCRV0) ................................................................... 140 11.3.4 Timer Control/Status Register V (TCSRV) .......................................................... 142 11.3.5 Timer Control Register V1 (TCRV1) ................................................................... 143 11.4 Operation ..............................................................
13.2.1 Timer Control/Status Register WD (TCSRWD) .................................................. 184 13.2.2 Timer Counter WD (TCWD)................................................................................ 185 13.2.3 Timer Mode Register WD (TMWD) .................................................................... 186 13.3 Operation ...........................................................................................................................
Section 15 I2C Bus Interface 2 (IIC2) ................................................................231 15.1 Features.............................................................................................................................. 231 15.2 Input/Output Pins ............................................................................................................... 233 15.3 Register Descriptions ................................................................................................
16.5 A/D Conversion Accuracy Definitions .............................................................................. 274 16.6 Usage Notes ....................................................................................................................... 276 16.6.1 Permissible Signal Source Impedance .................................................................. 276 16.6.2 Influences on Absolute Accuracy .........................................................................
20.2 Register Bits....................................................................................................................... 307 20.3 Registers States in Each Operating Mode .......................................................................... 311 Section 21 Electrical Characteristics .................................................................315 21.1 Absolute Maximum Ratings .............................................................................................. 315 21.
Appendix D Package Dimensions ..................................................................... 405 Appendix E EEPROM Stacked-Structure Cross-Sectional View ..................... 410 Main Revisions and Additions in this Edition..................................................... 411 Index .................................................................................................................. 415 Rev.5.00 Nov.
Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Overview Internal Block Diagram of H8/3694 Group of F-ZTATTM and Mask-ROM Versions.. 4 Internal Block Diagram of H8/3694N (EEPROM Stacked Version) ............................ 5 Pin Arrangement of H8/3694 Group of F-ZTATTM and Mask-ROM Versions (FP-64E, FP-64A).......................................................................................................... 6 Figure 1.
Section 5 Clock Pulse Generators Figure 5.1 Block Diagram of Clock Pulse Generators.................................................................. 69 Figure 5.2 Block Diagram of System Clock Generator ................................................................ 70 Figure 5.3 Typical Connection to Crystal Resonator.................................................................... 70 Figure 5.4 Equivalent Circuit of Crystal Resonator....................................................................
Figure 11.9 Pulse Output Example ............................................................................................. 148 Figure 11.10 Example of Pulse Output Synchronized to TRGV Input....................................... 149 Figure 11.11 Contention between TCNTV Write and Clear ...................................................... 150 Figure 11.12 Contention between TCORA Write and Compare Match ..................................... 151 Figure 11.
Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Serial Communication Interface 3 (SCI3) Block Diagram of SCI3........................................................................................... 190 Data Format in Asynchronous Communication ...................................................... 205 Relationship between Output Clock and Transfer Data Phase (Asynchronous Mode) (Example with 8-Bit Data, Parity, Two Stop Bits) ............. 205 Figure 14.4 Sample SCI3 Initialization Flowchart ............
Figure 15.11 Figure 15.12 Figure 15.13 Figure 15.14 Figure 15.15 Figure 15.16 Figure 15.17 Figure 15.18 Figure 15.19 Figure 15.20 Figure 15.21 Slave Receive Mode Operation Timing (1)........................................................... 254 Slave Receive Mode Operation Timing (2)........................................................... 254 Clocked Synchronous Serial Transfer Format....................................................... 255 Transmit Mode Operation Timing..............................
Figure 21.3 Figure 21.4 Figure 21.5 Figure 21.6 Figure 21.7 Figure 21.8 Input Timing............................................................................................................ 352 I2C Bus Interface Input/Output Timing ................................................................... 352 SCK3 Input Clock Timing ...................................................................................... 353 SCI Input/Output Timing in Clocked Synchronous Mode .....................................
Tables Section 1 Overview Table 1.1 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Operation Notation ................................................................................................. 24 Table 2.2 Data Transfer Instructions....................................................................................... 25 Table 2.3 Arithmetic Operations Instructions (1) ...............................
Table 7.5 Table 7.6 Table 7.7 Additional-Program Data Computation Table ...................................................... 100 Programming Time ............................................................................................... 100 Flash Memory Operating States............................................................................ 105 Section 10 Timer A Table 10.1 Pin Configuration..................................................................................................
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Table 18.1 LVDCR Settings and Select Functions................................................................. 292 Section 21 Electrical Characteristics Table 21.1 Absolute Maximum Ratings ................................................................................. 315 Table 21.2 DC Characteristics (1)........................................................................................... 318 Table 21.2 DC Characteristics (2)..
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Section 1 Overview Section 1 Overview 1.
Section 1 Overview • On-chip memory Model Standard Version Product Classification On-Chip Power-On Reset and LowVoltage Detecting Circuit Version ROM RAM Flash memory version TM (F-ZTAT version) H8/3694F HD64F3694 HD64F3694G 32 kbytes 2,048 bytes Mask ROM version H8/3694 HD6433694 HD6433694G 32 kbytes 1,024 bytes H8/3693 HD6433693 HD6433693G 24 kbytes 1,024 bytes H8/3692 HD6433692 HD6433692G 16 kbytes 512 bytes H8/3691 HD6433691 HD6433691G 12 kbytes 512 bytes H8/3690 HD6433690 HD
Section 1 Overview • Compact package Package Code Body Size Pin Pitch LQFP-64 FP-64E 10.0 × 10.0 mm 0.5 mm QFP-64 FP-64A LQFP-48 FP-48F LQFP-48 FP-48B QFN-48 TNP-48 14.0 × 14.0 mm 10.0 × 10.0 mm 7.0 × 7.0 mm 7.0 × 7.0 mm 0.8 mm 0.65 mm 0.5 mm 0.5 mm Only LQFP-64 (FP-64E) for H8/3694N package Rev.5.00 Nov.
Section 1 Overview Port 8 Port 7 P74/TMRIV P75/TMCIV P76/TMOV Port 5 P20/SCK3 P21/RXD P22/TXD P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5/ADTRG P56/SDA P57/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 CPU H8/300H Port 1 Data bus (lower) Port 2 P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV System clock generator Port B Subclock generator OSC1 OSC2 X1 X2 NMI TEST RES VCL Internal Bloc
Port 8 Port 7 P74/TMRIV P75/TMCIV P76/TMOV Port 5 SCL P50/WKP0 P51/WKP1 P52/WKP2 P53/WKP3 P54/WKP4 P55/WKP5/ADTRG P56/SDA P57/SCL PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6/AN6 PB7/AN7 Port 1 2 SDA I C bus P20/SCK3 P21/RXD P22/TXD P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 CPU H8/300H Data bus (lower) Port 2 P10/TMOW P11 P12 P14/IRQ0 P15/IRQ1 P16/IRQ2 P17/IRQ3/TRGV System clock generator Port B Subclock generator OSC1 OSC2 X1 X2 NMI TEST RES VCL VSS VCC Se
Section 1 Overview NC NC NMI P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 P20/SCK3 P21/RXD P22/TXD NC Pin Arrangement NC 1.
NMI P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 P20/SCK3 P21/RXD P22/TXD Section 1 Overview 36 35 34 33 32 31 30 29 28 27 26 25 40 21 P57/SCL PB4/AN4 41 20 P56/SDA PB5/AN5 42 19 P12 PB6/AN6 43 H8/3694 Group 18 P11 PB7/AN7 44 Top View 17 P10/TMOW PB3/AN3 45 16 P55/WKP5/ADTRG PB2/AN2 46 15 P54/WKP4 PB1/AN1 47 14 P53/WKP3 PB0/AN0 48 13 P52/WKP2 4 5 6 7 8 9 10 11 12 P51/WKP1 3 P50/WKP0 2 Vcc 1 OSC1 P74/TMRIV P17/IRQ3/TRGV OSC2 2
NC NC NMI P80/FTCI P81/FTIOA P82/FTIOB P83/FTIOC P84/FTIOD P85 P86 P87 P20/SCK3 P21/RXD P22/TXD NC NC Section 1 Overview 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 52 29 P75/TMCIV P16/IRQ2 53 28 P74/TMRIV P17/IRQ3/TRGV 54 27 SCL PB4/AN4 55 26 SDA PB5/AN5 56 H8/3694N 25 P12 PB6/AN6 57 Top View 24 P11 PB7/AN7 58 23 P10/TMOW PB3/AN3 59 22 P55/WKP5/ADTRG PB2/AN2 60 21 P54/WKP4 PB1/AN1 61 20 P53/WKP3 PB0/AN0 62 19 P52/WKP2 NC 63 18 NC NC 64
Section 1 Overview 1.4 Pin Functions Table 1.1 Pin Functions Pin No. FP-48F FP-48B TNP-48 I/O Functions Type Symbol FP-64E FP-64A Power source pins VCC 12 10 Input Power supply pin. Connect this pin to the system power supply. VSS 9 7 Input Ground pin. Connect this pin to the system power supply (0V). AVCC 3 1 Input Analog power supply pin for the A/D converter. When the A/D converter is not used, connect this pin to the system power supply.
Section 1 Overview Pin No. FP-48F FP-48B TNP-48 I/O Functions Type Symbol FP-64E FP-64A Timer A TMOW 23 17 Output This is an output pin for divided clocks. Timer V TMOV 30 24 Output This is an output pin for waveforms generated by the output compare function. TMCIV 29 23 Input External event input pin. TMRIV 28 22 Input Counter reset input pin. TRGV 54 40 Input Counter start trigger input pin. FTCI 36 26 Input External event input pin.
Section 1 Overview Pin No. FP-64E FP-64A FP-48F FP-48B TNP-48 I/O Functions Type Symbol I/O ports P76 to P74 28 to 30 22 to 24 I/O 3-bit I/O port P87 to P80 36 to 43 26 to 33 I/O 8-bit I/O port. Notes: 1. These pins are only available for the I2C bus interface in the H8/3694N. Since the I2C bus is disabled after canceling a reset, the ICE bit in ICCR1 must be set to 1 by using the program. 2. The P57 and P56 pins are not available in the H8/3694N. Rev.5.00 Nov.
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Section 2 CPU Section 2 CPU This LSI has an H8/300H CPU with an internal 32-bit architecture that is upward-compatible with the H8/300CPU, and supports only normal mode, which has a 64-kbyte address space. • Upward-compatible with H8/300 CPUs Can execute H8/300 CPUs object programs Additional eight 16-bit extended registers 32-bit transfer and arithmetic and logic instructions are added Signed multiply and divide instructions are added.
Section 2 CPU 2.1 Address Space and Memory Map The address space of this LSI is 64 kbytes, which includes the program area and the data area. Figures 2.1 show the memory map.
Section 2 CPU HD6433692, HD6433692G (Mask ROM version) H'0000 H'0033 H'0034 Interrupt vector HD6433693, HD6433693G (Mask ROM version) H'0000 H'0033 H'0034 HD6433694, HD6433694G (Mask ROM version) H'0000 H'0033 H'0034 Interrupt vector Interrupt vector On-chip ROM (16 kbytes) On-chip ROM (24 kbytes) H'3FFF On-chip ROM (32 kbytes) H'5FFF Not used H'7FFF Not used Not used H'F730 H'F730 Internal I/O register H'F74F H'F730 Internal I/O register Internal I/O register H'F74F H'F74F Not used Not us
Section 2 CPU HD64N3694G HD6483694G (On-chip EEPROM module) H'0000 H'01FF User area (512 bytes) Not used H'FF09 Slave address register Not used Figure 2.1 Memory Map (3) Rev.5.00 Nov.
Section 2 CPU 2.2 Register Configuration The H8/300H CPU has the internal registers shown in figure 2.2. There are two types of registers; general registers and control registers. The control registers are a 24-bit program counter (PC), and an 8-bit condition code register (CCR).
Section 2 CPU 2.2.1 General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally identical and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.3 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.4 shows the relationship between stack pointer and the stack area. Free area SP (ER7) Stack area Figure 2.4 Relationship between Stack Pointer and Stack Area 2.2.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute.
Section 2 CPU Bit Bit Name Initial Value R/W Description 7 I 1 R/W Interrupt Mask Bit Masks interrupts other than NMI when set to 1. NMI is accepted regardless of the I bit setting. The I bit is set to 1 at the start of an exception-handling sequence. 6 UI Undefined R/W User Bit Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.
Section 2 CPU 2.3 Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.3.1 General Register Data Formats Figure 2.5 shows the data formats in general registers.
Section 2 CPU Data Type General Register Word data Rn Data Format 15 Word data MSB En 15 MSB Longword data 0 LSB 0 LSB ERn 31 16 15 MSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2.5 General Register Data Formats (2) Rev.5.00 Nov.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.6 shows the data formats in memory. The H8/300H CPU can access word data and longword data in memory, however word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, an address error does not occur, however the least significant bit of the address is regarded as 0, so access begins the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.4 Instruction Set 2.4.1 Table of Instructions Classified by Function The H8/300H CPU has 62 instructions. Tables 2.2 to 2.9 summarize the instructions in each functional category. The notation used in tables 2.2 to 2.9 is defined below. Table 2.
Section 2 CPU Table 2.2 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) → Rd, Cannot be used in this LSI. MOVTPE B Rs → (EAs) Cannot be used in this LSI. POP W/L @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register (immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU Table 2.3 Arithmetic Operations Instructions (2) Instruction Size* Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU Table 2.4 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register.
Section 2 CPU Table 2.6 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C XORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU Table 2.7 Branch Instructions Instruction Size Function Bcc* — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Table 2.8 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling. RTE — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR Moves the source operand contents to the CCR. The CCR size is one byte, but in transfer from memory, data is read by word access. STC B/W CCR → (EAd) Transfers the CCR contents to a destination location.
Section 2 CPU Table 2.9 Block Data Transfer Instructions Instruction Size Function EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+, R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+, R4–1 → R4 Until R4 = 0 else next; Transfers a data block. Starting from the address set in ER5, transfers data for the number of bytes set in R4L or R4 to the address location set in ER6. Execution of the next instruction begins as soon as the transfer is completed. 2.4.
Section 2 CPU (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op rn rm MOV.B @(d:16, Rn), Rm EA(disp) (4) Operation field, effective address extension, and condition field op cc EA(disp) BRA d:8 Figure 2.7 Instruction Formats 2.5 Addressing Modes and Effective Address Calculation The following describes the H8/300H CPU.
Section 2 CPU Table 2.10 Addressing Modes No.
Section 2 CPU • Register indirect with pre-decrement—@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the lower 24 bits of the result is the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. For the word or longword access, the register value should be even.
Section 2 CPU so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value should be an even number. Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The memory operand is accessed by longword access.
Section 2 CPU 2.5.2 Effective Address Calculation Table 2.12 indicates how effective addresses are calculated in each addressing mode. In this LSI the upper 8 bits of the effective address are ignored in order to generate a 16-bit effective address. Table 2.12 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct(Rn) rm Operand is general register contents.
Section 2 CPU Table 2.12 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 8 7 23 op abs 0 H'FFFF @aa:16 23 op abs 16 15 0 Sign extension @aa:24 op 0 23 abs 6 Immediate #xx:8/#xx:16/#xx:32 op 7 Operand is immediate data.
Section 2 CPU 2.6 Basic Bus Cycle CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.1 Access to On-Chip Memory (RAM, ROM) Access to on-chip memory takes place in two states.
Section 2 CPU 2.6.2 On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits or 16 bits depending on the register. For description on the data bus width and number of accessing states of each register, refer to section 20.1, Register Addresses (Address Order). Registers with 16-bit data bus width can be accessed by word size only. Registers with 8-bit data bus width can be accessed by byte or word size.
Section 2 CPU 2.7 CPU States There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state. The program execution state includes active mode and subactive mode. For the program halt state there are a sleep mode, standby mode, and sub-sleep mode. These states are shown in figure 2.11. Figure 2.12 shows the state transitions. For details on program execution state and program halt state, refer to section 6, Power-Down Modes.
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source Program halt state Interrupt source Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.12 State Transitions 2.8 Usage Notes 2.8.1 Notes on Data Access to Empty Areas The address space of this LSI includes empty areas in addition to the ROM, RAM, and on-chip I/O registers areas available to the user.
Section 2 CPU Bit manipulation for two registers assigned to the same address Example 1: Bit manipulation for the timer load register and timer counter (Applicable for timer B and timer C, not for the group of this LSI.) Figure 2.13 shows an example of a timer in which two timer registers are assigned to the same address.
Section 2 CPU • Prior to executing BSET instruction P57 P56 P55 P54 P53 P52 P51 P50 Input/output Input Input Output Output Output Output Output Output Pin state Low level High level Low level Low level Low level Low level Low level Low level PCR5 0 0 1 1 1 1 1 1 PDR5 1 0 0 0 0 0 0 0 • BSET instruction executed instruction BSET #0, @PDR5 The BSET instruction is executed for port 5.
Section 2 CPU • Prior to executing BSET instruction MOV.B MOV.B MOV.B #80, R0L, R0L, R0L @RAM0 @PDR5 The PDR5 value (H'80) is written to a work area in memory (RAM0) as well as to PDR5.
Section 2 CPU an input pin by the BCLR instruction is shown below. It is assumed that a high-level signal will be input to this input pin.
Section 2 CPU • Prior to executing BCLR instruction MOV.B MOV.B MOV.B #3F, R0L, R0L, R0L @RAM0 @PCR5 The PCR5 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR5.
Section 3 Exception Handling Section 3 Exception Handling Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts. • Reset A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared by the RES pin. The chip is also reset when the watchdog timer overflows, and exception handling starts. Exception handling is the same as exception handling by the RES pin.
Section 3 Exception Handling Vector Number Vector Address Priority Direct transition by executing the SLEEP instruction 13 H'001A to H'001B High IRQ0 Low-voltage detection interrupt* 14 H'001C to H'001D IRQ1 15 H'001E to H'001F IRQ2 16 H'0020 to H'0021 IRQ3 17 H'0022 to H'0023 WKP 18 H'0024 to H'0025 Timer A Overflow 19 H’0026 to H’0027 Reserved for system use 20 H’0028 to H’0029 Timer W Timer W input capture A /compare match A Timer W input capture B /compare match B Timer
Section 3 Exception Handling 3.2 Register Descriptions Interrupts are controlled by the following registers. • • • • • Interrupt edge select register 1 (IEGR1) Interrupt edge select register 2 (IEGR2) Interrupt enable register 1 (IENR1) Interrupt flag register 1 (IRR1) Wakeup interrupt flag register (IWPR) 3.2.1 Interrupt Edge Select Register 1 (IEGR1) IEGR1 selects the direction of an edge that generates interrupt requests of pins NMI and IRQ3 to IRQ0.
Section 3 Exception Handling 3.2.2 Interrupt Edge Select Register 2 (IEGR2) IEGR2 selects the direction of an edge that generates interrupt requests of the pins ADTRG and WKP5 to WKP0. Bit Bit Name Initial Value R/W Description 7, 6 All 1 Reserved 5 WPEG5 0 R/W WKP5 Edge Select These bits are always read as 1.
Section 3 Exception Handling 3.2.3 Interrupt Enable Register 1 (IENR1) IENR1 enables direct transition interrupts, timer A overflow interrupts, and external pin interrupts. Bit Bit Name Initial Value R/W Description 7 IENDT 0 R/W Direct Transfer Interrupt Enable When this bit is set to 1, direct transition interrupt requests are enabled. 6 IENTA 0 R/W Timer A Interrupt Enable When this bit is set to 1, timer A overflow interrupt requests are enabled.
Section 3 Exception Handling 3.2.4 Interrupt Flag Register 1 (IRR1) IRR1 is a status flag register for direct transition interrupts, timer A overflow interrupts, and IRQ3 to IRQ0 interrupt requests. Bit Bit Name Initial Value R/W Description 7 IRRDT 0 R/W Direct Transfer Interrupt Request Flag [Setting condition] When a direct transfer is made by executing a SLEEP instruction while DTON in SYSCR2 is set to 1.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 0 IRRl0 0 R/W IRQ0 Interrupt Request Flag [Setting condition] When IRQ0 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IRRI0 is cleared by writing 0 3.2.5 Wakeup Interrupt Flag Register (IWPR) IWPR is a status flag register for WKP5 to WKP0 interrupt requests.
Section 3 Exception Handling Bit Bit Name Initial Value R/W Description 2 IWPF2 0 R/W WKP2 Interrupt Request Flag [Setting condition] When WKP2 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF2 is cleared by writing 0. 1 IWPF1 0 R/W WKP1 Interrupt Request Flag [Setting condition] When WKP1 pin is designated for interrupt input and the designated signal edge is detected. [Clearing condition] When IWPF1 is cleared by writing 0.
Section 3 Exception Handling 3.4 Interrupt Exception Handling 3.4.1 External Interrupts As the external interrupts, there are NMI, IRQ3 to IRQ0, and WKP5 to WKP0 interrupts. NMI Interrupt NMI interrupt is requested by input signal edge to pin NMI. This interrupt is detected by either rising edge sensing or falling edge sensing, depending on the setting of bit NMIEG in IEGR1. NMI is the highest-priority interrupt, and can always be accepted without depending on the I bit value in CCR.
Section 3 Exception Handling Reset cleared Initial program instruction prefetch Vector fetch Internal processing RES φ Internal address bus (1) (2) Internal read signal Internal write signal Internal data bus (16 bits) (2) (3) (1) Reset exception handling vector address (H'0000) (2) Program start address (3) Initial program instruction Figure 3.1 Reset Sequence 3.4.
Section 3 Exception Handling 2. When multiple interrupt requests are generated, the interrupt controller requests to the CPU for the interrupt handling with the highest priority at that time according to table 3.1. Other interrupt requests are held pending. 3. The CPU accepts the NMI and address break without depending on the I bit value. Other interrupt requests are accepted, if the I bit is cleared to 0 in CCR; if the I bit is set to 1, the interrupt request is held pending. 4.
Section 3 Exception Handling SP – 4 SP (R7) CCR SP – 3 SP + 1 CCR*3 SP – 2 SP + 2 PCH SP – 1 SP + 3 PCL SP (R7) SP + 4 Even address Stack area Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling [Legend] PCH : Upper 8 bits of program counter (PC) PCL : Lower 8 bits of program counter (PC) CCR: Condition code register SP: Stack pointer Notes: 1.
(2) (1) (4) Instruction prefetch (3) Internal processing (5) (1) Stack access (6) (7) (9) Vector fetch (8) (1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) (2)(4) Instruction code (not executed) (3) Instruction prefetch address (Instruction is not executed.
Section 3 Exception Handling 3.5 Usage Notes 3.5.1 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset.
Section 4 Address Break Section 4 Address Break The address break simplifies on-board program debugging. It requests an address break interrupt when the set break condition is satisfied. The interrupt request is not affected by the I bit of CCR. Break conditions that can be set include instruction execution at a specific address and a combination of access and data at a specific address.
Section 4 Address Break 4.1.1 Address Break Control Register (ABRKCR) ABRKCR sets address break conditions. Bit Bit Name Initial Value R/W Description 7 RTINTE 1 R/W RTE Interrupt Enable When this bit is 0, the interrupt immediately after executing RTE is masked and then one instruction must be executed. When this bit is 1, the interrupt is not masked. 6 CSEL1 0 R/W Condition Select 1 and 0 5 CSEL0 0 R/W These bits set address break conditions.
Section 4 Address Break When an address break is set in the data read cycle or data write cycle, the data bus used will depend on the combination of the byte/word access and address. Table 4.1 shows the access and data bus used. When an I/O register space with an 8-bit data bus width is accessed in word size, a byte access is generated twice. For details on data widths of each register, see section 20.1, Register Addresses (Address Order). Table 4.
Section 4 Address Break 4.1.3 Break Address Registers (BARH, BARL) BARH and BARL are 16-bit read/write registers that set the address for generating an address break interrupt. When setting the address break condition to the instruction execution cycle, set the first byte address of the instruction. The initial value of this register is H'FFFF. 4.1.4 Break Data Registers (BDRH, BDRL) BDRH and BDRL are 16-bit read/write registers that set the data for generating an address break interrupt.
Section 4 Address Break Figures 4.2 show the operation examples of the address break interrupt setting. When the address break is specified in instruction execution cycle Register setting • ABRKCR = H'80 • BAR = H'025A Program 0258 * 025A 025C 0260 0262 : NOP NOP MOV.W @H'025A,R0 NOP NOP : Underline indicates the address to be stacked.
Section 4 Address Break Rev.5.00 Nov.
Section 5 Clock Pulse Generators Section 5 Clock Pulse Generators Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator, a duty correction circuit, and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider. Figure 5.1 shows a block diagram of the clock pulse generators.
Section 5 Clock Pulse Generators 5.1 System Clock Generator Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic resonator, or by providing external clock input. Figure 5.2 shows a block diagram of the system clock generator. OSC 2 LPM OSC 1 LPM: Low-power mode (standby mode, subactive mode, subsleep mode) Figure 5.2 Block Diagram of System Clock Generator 5.1.1 Connecting Crystal Resonator Figure 5.
Section 5 Clock Pulse Generators Table 5.1 Crystal Resonator Parameters Frequency (MHz) 2 4 8 10 16 20 RS (max) 500 Ω 120 Ω 80 Ω 60 Ω 50 Ω 40 Ω C0 (max) 7 pF 7 pF 7 pF 7 pF 7 pF 7 pF 5.1.2 Connecting Ceramic Resonator Figure 5.5 shows a typical method of connecting a ceramic resonator. C1 OSC1 C2 OSC2 C1 = 5 to 30 pF C2 = 5 to 30 pF Figure 5.5 Typical Connection to Ceramic Resonator 5.1.
Section 5 Clock Pulse Generators 5.2 Subclock Generator Figure 5.7 shows a block diagram of the subclock generator. X2 8MΩ X1 Note : Registance is a reference value. Figure 5.7 Block Diagram of Subclock Generator 5.2.1 Connecting 32.768-kHz Crystal Resonator Clock pulses can be supplied to the subclock divider by connecting a 32.768-kHz crystal resonator, as shown in figure 5.8. Figure 5.9 shows the equivalent circuit of the 32.768-kHz crystal resonator. C1 X1 C2 X2 C1 = C 2 = 15 pF (typ.
Section 5 Clock Pulse Generators 5.2.2 Pin Connection when Not Using Subclock When the subclock is not used, connect pin X1 to VCL or VSS and leave pin X2 open, as shown in figure 5.10. VCL or VSS X1 X2 Open Figure 5.10 Pin Connection when not Using Subclock 5.3 Prescalers 5.3.1 Prescaler S Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once per clock period.
Section 5 Clock Pulse Generators 5.4 Usage Notes 5.4.1 Note on Resonators Resonator characteristics are closely related to board design and should be carefully evaluated by the user, referring to the examples shown in this section. Resonator circuit constants will differ depending on the resonator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator element manufacturer.
Section 6 Power-Down Modes Section 6 Power-Down Modes This LSI has six modes of operation after a reset. These include a normal active mode and four power-down modes, in which power consumption is significantly reduced. Module standby mode reduces power consumption by selectively halting on-chip module functions. • Active mode The CPU and all on-chip peripheral modules are operable on the system clock. The system clock frequency can be selected from φosc, φosc/8, φosc/16, φosc/32, and φosc/64.
Section 6 Power-Down Modes 6.1.1 System Control Register 1 (SYSCR1) SYSCR1 controls the power-down modes, as well as SYSCR2. Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W Software Standby This bit selects the mode to transit after the execution of the SLEEP instruction. 0: a transition is made to sleep mode or subsleep mode. 1: a transition is made to standby mode. For details, see table 6.2.
Section 6 Power-Down Modes Table 6.1 Operating Frequency and Waiting Time STS2 STS1 STS0 Waiting Time 20 MHz 16 MHz 10 MHz 8 MHz 4 MHz 2 MHz 1 MHz 0.5 MHz 0 0 1 1 0 1 0 8,192 states 0.4 0.5 0.8 1.0 2.0 4.1 8.1 16.4 1 16,384 states 0.8 1.0 1.6 2.0 4.1 8.2 16.4 32.8 0 32,768 states 1.6 2.0 3.3 4.1 8.2 16.4 32.8 65.5 1 65,536 states 3.3 4.1 6.6 8.2 16.4 32.8 65.5 131.1 0 131,072 states 6.6 8.2 13.1 16.4 32.8 65.5 131.1 262.1 1 1,024 states 0.
Section 6 Power-Down Modes 6.1.2 System Control Register 2 (SYSCR2) SYSCR2 controls the power-down modes, as well as SYSCR1. Bit Bit Name Initial Value R/W Description 7 SMSEL 0 R/W Sleep Mode Selection 6 LSON 0 R/W Low Speed on Flag 5 DTON 0 R/W Direct Transfer on Flag These bits select the mode to transit after the execution of a SLEEP instruction, as well as bit SSBY of SYSCR1. For details, see table 6.2.
Section 6 Power-Down Modes 6.1.3 Module Standby Control Register 1 (MSTCR1) MSTCR1 allows the on-chip peripheral modules to enter a standby state in module units. Bit Bit Name Initial Value R/W 7 0 Description Reserved This bit is always read as 0.
Section 6 Power-Down Modes 6.2 Mode Transitions and States of LSI Figure 6.1 shows the possible transitions among these operating modes. A transition is made from the program execution state to the program halt state of the program by executing a SLEEP instruction. Interrupts allow for returning from the program halt state to the program execution state of the program.
Section 6 Power-Down Modes Table 6.2 Transition Mode after SLEEP Instruction Execution and Interrupt Handling DTON SSBY SMSEL LSON Transition Mode after SLEEP Instruction Execution 0 0 0 0 Sleep mode 1 1 0 Legend: * Active mode Subactive mode Subsleep mode 1 1 Transition Mode due to Interrupt Active mode Subactive mode 1 X X Standby mode Active mode X 0* 0 Active mode (direct transition) — X X 1 Subactive mode (direct transition) — X : Don’t care.
Section 6 Power-Down Modes Table 6.
Section 6 Power-Down Modes 6.2.1 Sleep Mode In sleep mode, CPU operation is halted but the on-chip peripheral modules function at the clock frequency set by the MA2, MA1, and MA0 bits in SYSCR2. CPU register contents are retained. When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts. Sleep mode is not cleared if the I bit of the condition code register (CCR) is set to 1 or the requested interrupt is disabled in the interrupt enable register.
Section 6 Power-Down Modes cleared, a transition is made to active mode when the LSON bit in SYSCR2 is 0, and a transition is made to subactive mode when the bit is 1. When the RES pin goes low, the system clock pulse generator starts. Since system clock signals are supplied to the entire chip as soon as the system clock pulse generator starts functioning, the RES pin must be kept low until the pulse generator output stabilizes.
Section 6 Power-Down Modes 6.4 Direct Transition The CPU can execute programs in two modes: active and subactive mode. A direct transition is a transition between these two modes without stopping program execution. A direct transition can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. The direct transition also enables operating frequency modification in active or subactive mode. After the mode transition, direct transition interrupt exception handling starts.
Section 6 Power-Down Modes Example Direct transition time = (2 + 1) × 8tw + (8192 + 14) × tosc = 24tw + 8206tosc (when the CPU operating clock of φw/8 → φosc and a waiting time of 8192 states are selected) Legend tosc: OSC clock cycle time tw: watch clock cycle time tcyc: system clock (φ) cycle time tsubcyc: subclock (φSUB) cycle time 6.5 Module Standby Function The module-standby function can be set to any peripheral module.
Section 7 ROM Section 7 ROM The features of the 32-kbyte flash memory built into the flash memory version are summarized below. • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. The flash memory is configured as follows: 1 kbyte × 4 blocks and 28 kbytes × 1 block. To erase the entire flash memory, each block must be erased in turn. • Reprogramming capability The flash memory can be reprogrammed up to 1,000 times.
Section 7 ROM Erase unit H'0000 H'0001 H'0002 H'0080 H'0081 H'0082 H'0380 H'0381 H'0382 H'0400 H'0401 H'0402 H'0480 H'0481 H'0481 H'0780 H'0781 H'0782 H'0800 H'0801 H'0802 H'0880 H'0881 H'0882 H'0B80 H'0B81 H'0B82 H'0C00 H'0C01 H'0C02 H'0C80 H'0C81 H'0C82 H'0F80 H'0F81 H'0F82 H'1000 H'1001 H'1002 H'1080 H'1081 H'1082 H'10FF H'7F80 H'7F81 H'7F82 H'7FFF Programming unit: 128 bytes H'007F H'00FF 1kbyte Erase unit H'03FF Programming unit: 128 bytes H'047F H'
Section 7 ROM 7.2.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1 is a register that makes the flash memory change to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 7.4, Flash Memory Programming/Erasing. Bit Bit Name Initial Value R/W 7 — 0 — Description Reserved This bit is always read as 0. 6 SWE 0 R/W Software Write Enable When this bit is set to 1, flash memory programming/erasing is enabled.
Section 7 ROM Bit Bit Name Initial Value R/W Description 0 P 0 R/W Program When this bit is set to 1, and while the SWE=1 and PSU=1 bits are 1, the flash memory changes to program mode. When it is cleared to 0, program mode is cancelled. 7.2.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Section 7 ROM 7.2.3 Erase Block Register 1 (EBR1) EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR1 to be automatically cleared to 0. Bit Bit Name Initial Value R/W Description 7 to 5 — All 0 — Reserved These bits are always read as 0. 4 EB4 0 R/W When this bit is set to 1, 28 kbytes of H'1000 to H'7FFF will be erased.
Section 7 ROM 7.2.4 Flash Memory Power Control Register (FLPWCR) FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI switches to subactive mode. There are two modes: mode in which operation of the power supply circuit of flash memory is partly halted in power-down mode and flash memory can be read, and mode in which even if a transition is made to subactive mode, operation of the power supply circuit of flash memory is retained and flash memory can be read.
Section 7 ROM 7.3 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode. At reset-start in reset mode, this LSI changes to a mode depending on the TEST pin settings, NMI pin settings, and input level of each port, as shown in table 7.1.
Section 7 ROM 4. 5. 6. 7. 8. pulled up on the board if necessary. After the reset is complete, it takes approximately 100 states before the chip is ready to measure the low-level period. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the completion of bit rate adjustment. The host should confirm that this adjustment end indication (H'00) has been received normally, and transmit one H'55 byte to the chip.
Section 7 ROM Boot Mode Operation Host Operation Communication Contents Processing Contents Transfer of number of bytes of programming control program Flash memory erase Bit rate adjustment Boot mode initiation Item Table 7.2 LSI Operation Processing Contents Branches to boot program at reset-start. Boot program initiation Continuously transmits data H'00 at specified bit rate. Transmits data H'55 when data H'00 is received error-free. H'00, H'00 . . .
Section 7 ROM Table 7.3 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19,200 bps 16 to 20 MHz 9,600 bps 8 to 16 MHz 4,800 bps 4 to 16 MHz 2,400 bps 2 to 16 MHz 7.3.2 Programming/Erasing in User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program.
Section 7 ROM Reset-start No Program/erase? Yes Transfer user program/erase control program to RAM Branch to flash memory application program Branch to user program/erase control program in RAM Execute user program/erase control program (flash memory rewrite) Branch to flash memory application program Figure 7.2 Programming/Erasing Flowchart Example in User Program Mode Rev.5.00 Nov.
Section 7 ROM 7.4 Flash Memory Programming/Erasing A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
Section 7 ROM 8. The maximum number of repetitions of the program/program-verify sequence of the same bit is 1,000.
Section 7 ROM Table 7.4 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 — 1 1 1 Remains in erased state Table 7.5 Additional-Program Data Computation Table Reprogram Data Verify Data Additional-Program Data Comments 0 0 0 Additional-program bit 0 1 1 No additional programming 1 0 1 No additional programming 1 1 1 No additional programming Comments Table 7.
Section 7 ROM 5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two bits are B'00. Verify data can be read in longwords from the address to which a dummy write was performed. 6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify sequence is 100. 7.4.
Section 7 ROM Erase start SWE bit ← 1 Wait 1 µs n←1 Set EBR1 Enable WDT ESU bit ← 1 Wait 100 µs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 µs ESU bit ← 10 10 µs Disable WDT EV bit ← 1 Wait 20 µs Set block start address as verify address H'FF dummy write to verify address Wait 2 µs * n←n+1 Read verify data No Verify data + all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 µs Wait 4µs All erase block erased ? n ≤100 ? Yes Yes No Yes SWE bit ← 0 SWE b
Section 7 ROM 7.5 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 7.5.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, or standby mode.
Section 7 ROM entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be made to verify mode. Error protection can be cleared only by a reset. 7.6 Programmer Mode In programmer mode, a PROM programmer can be used to perform programming/erasing via a socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU device type with the on-chip 64-kbyte flash memory (FZTAT64V5). 7.
Section 7 ROM Table 7.7 Flash Memory Operating States Flash Memory Operating State LSI Operating State PDWND = 0 (Initial value) PDWND = 1 Active mode Normal operating mode Normal operating mode Subactive mode Power-down mode Normal operating mode Sleep mode Normal operating mode Normal operating mode Subsleep mode Standby mode Standby mode Standby mode Standby mode Standby mode Rev.5.00 Nov.
Section 7 ROM Rev.5.00 Nov.
Section 8 RAM Section 8 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling two-state access by the CPU to both byte data and word data.
Section 8 RAM Rev.5.00 Nov.
Section 9 I/O Ports Section 9 I/O Ports The group of this LSI has twenty-nine general I/O ports (twenty-seven general I/O ports in the H8/3694N) and eight general input-only ports. Port 8 is a large current port, which can drive 20 mA (@VOL = 1.5 V) when a low level signal is output. Any of these ports can become an input port immediately after a reset.
Section 9 I/O Ports 9.1.1 Port Mode Register 1 (PMR1) PMR1 switches the functions of pins in port 1 and port 2. Bit Bit Name Initial Value R/W Description 7 IRQ3 0 R/W P17/IRQ3/TRGV Pin Function Switch This bit selects whether pin P17/IRQ3/TRGV is used as P17 or as IRQ3/TRGV. 0: General I/O port 1: IRQ3/TRGV input pin 6 IRQ2 0 R/W P16/IRQ2 Pin Function Switch This bit selects whether pin P16/IRQ2 is used as P16 or as IRQ2.
Section 9 I/O Ports 9.1.2 Port Control Register 1 (PCR1) PCR1 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 1. Bit Bit Name Initial Value R/W Description 7 PCR17 0 W 6 PCR16 0 W 5 PCR15 0 W When the corresponding pin is designated in PMR1 as a general I/O pin, setting a PCR1 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 4 PCR14 0 W Bit 3 is a reserved bit.
Section 9 I/O Ports 9.1.4 Port Pull-Up Control Register 1 (PUCR1) PUCR1 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7 PUCR17 0 R/W 6 PUCR16 0 R/W 5 PUCR15 0 R/W Only bits for which PCR1 is cleared are valid. The pull-up MOS of P17 to P14 and P12 to P10 pins enter the onstate when these bits are set to 1, while they enter the off-state when these bits are cleared to 0. 4 PUCR14 0 R/W Bit 3 is a reserved bit.
Section 9 I/O Ports P15/IRQ1 pin Register PMR1 PCR1 Bit Name IRQ1 PCR15 Pin Function 0 P15 input pin Setting value 0 1 1 P15 output pin X IRQ1 input pin Legend: X: Don't care. P14/IRQ0 pin Register PMR1 PCR1 Bit Name IRQ0 PCR14 Pin Function 0 P14 input pin 1 P14 output pin X IRQ0 input pin Setting value 0 1 Legend: X: Don't care.
Section 9 I/O Ports P10/TMOW pin Register PMR1 PCR1 Bit Name TMOW PCR10 Pin Function 0 P10 input pin 1 P10 output pin X TMOW output pin Setting value 0 1 Legend: X: Don't care. 9.2 Port 2 Port 2 is a general I/O port also functioning as a SCI3 I/O pin. Each pin of the port 2 is shown in figure 9.2. The register settings of PMR1 and SCI3 have priority for functions of the pins for both uses. P22/TXD Port 2 P21/RXD P20/SCK3 Figure 9.
Section 9 I/O Ports 9.2.1 Port Control Register 2 (PCR2) PCR2 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 2. Bit Bit Name Initial Value R/W 7 to 3 Reserved 2 PCR22 0 W 1 PCR21 0 W 0 PCR20 0 W When each of the port 2 pins P22 to P20 functions as an general I/O port, setting a PCR2 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. 9.2.
Section 9 I/O Ports 9.2.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P22/TXD pin Register PMR1 PCR2 Bit Name TXD PCR22 Pin Function Setting Value 0 0 P22 input pin 1 P22 output pin X TXD output pin 1 Legend: X: Don't care. P21/RXD pin Register SCR3 PCR2 Bit Name RE PCR21 Pin Function Setting Value 0 0 P21 input pin 1 P21 output pin X RXD input pin 1 Legend: X: Don't care.
Section 9 I/O Ports 9.3 Port 5 Port 5 is a general I/O port also functioning as an I2C bus interface I/O pin, an A/D trigger input pin, wakeup interrupt input pin. Each pin of the port 5 is shown in figure 9.3. The register setting of the I2C bus interface register has priority for functions of the pins P57/SCL and P56/SDA.
Section 9 I/O Ports 9.3.1 Port Mode Register 5 (PMR5) PMR5 switches the functions of pins in port 5. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved 5 WKP5 0 R/W P55/WKP5/ADTRG Pin Function Switch These bits are always read as 0. Selects whether pin P55/WKP5/ADTRG is used as P55 or as WKP5/ADTRG input. 0: General I/O port 1: WKP5/ADTRG input pin 4 WKP4 0 R/W P54/WKP4 Pin Function Switch Selects whether pin P54/WKP4 is used as P54 or as WKP4.
Section 9 I/O Ports 9.3.2 Port Control Register 5 (PCR5) PCR5 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 5. Bit Bit Name Initial Value R/W Description 7 PCR57 0 W 6 PCR56 0 W 5 PCR55 0 W When each of the port 5 pins P57 to P50 functions as an general I/O port, setting a PCR5 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
Section 9 I/O Ports 9.3.4 Port Pull-Up Control Register 5 (PUCR5) PUCR5 controls the pull-up MOS in bit units of the pins set as the input ports. Bit Bit Name Initial Value R/W Description 7, 6 All 0 Reserved These bits are always read as 0. 5 PUCR55 0 R/W 4 PUCR54 0 R/W 3 PUCR53 0 R/W 2 PUCR52 0 R/W 1 PUCR51 0 R/W 0 PUCR50 0 R/W 9.3.5 Pin Functions Only bits for which PCR5 is cleared are valid.
Section 9 I/O Ports P56/SDA pin Register ICCR1 PCR5 Bit Name ICE PCR56 Pin Function Setting Value 0 0 P56 input pin 1 P56 output pin X SDA I/O pin 1 Legend: X: Don't care. SDA performs the NMOS open-drain output, that enables a direct bus drive. P55/WKP5/ADTRG pin Register PMR5 PCR5 Bit Name WKP5 PCR55 Pin Function Setting Value 0 0 P55 input pin 1 P55 output pin X WKP5/ADTRG input pin 1 Legend: X: Don't care.
Section 9 I/O Ports P53/WKP3 pin Register PMR5 PCR5 Bit Name WKP3 PCR53 Pin Function Setting Value 0 0 P53 input pin 1 P53 output pin X WKP3 input pin 1 Legend: X: Don't care. P52/WKP2 pin Register PMR5 PCR5 Bit Name WKP2 PCR52 Pin Function Setting Value 0 0 P52 input pin 1 P52 output pin X WKP2 input pin 1 Legend: X: Don't care.
Section 9 I/O Ports P50/WKP0 pin Register PMR5 PCR5 Bit Name WKP0 PCR50 Pin Function Setting Value 0 0 P50 input pin 1 P50 output pin X WKP0 input pin 1 Legend: X: Don't care. 9.4 Port 7 Port 7 is a general I/O port also functioning as a timer V I/O pin. Each pin of the port 7 is shown in figure 9.4. The register setting of TCSRV in timer V has priority for functions of pin P76/TMOV.
Section 9 I/O Ports 9.4.1 Port Control Register 7 (PCR7) PCR7 selects inputs/outputs in bit units for pins to be used as general I/O ports of port 7. Bit Bit Name Initial Value R/W Description 7 Reserved 6 PCR76 0 W 5 PCR75 0 W 4 PCR74 0 W Setting a PCR7 bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. Note that the TCSRV setting of the timer V has priority for deciding input/output direction of the P76/TMOV pin.
Section 9 I/O Ports 9.4.3 Pin Functions The correspondence between the register specification and the port functions is shown below. P76/TMOV pin Register TCSRV Bit Name OS3 to OS0 PCR76 Pin Function Setting Value 0000 0 P76 input pin 1 P76 output pin X TMOV output pin Other than the above values PCR7 Legend: X: Don't care.
Section 9 I/O Ports 9.5 Port 8 Port 8 is a general I/O port also functioning as a timer W I/O pin. Each pin of the port 8 is shown in figure 9.5. The register setting of the timer W has priority for functions of the pins P84/FTIOD, P83/FTIOC, P82/FTIOB, and P81/FTIOA. P80/FTCI also functions as a timer W input port that is connected to the timer W regardless of the register setting of port 8. P87 P86 P85 Port 8 P84/FTIOD P83/FTIOC P82/FTIOB P81/FTIOA P80/FTCI Figure 9.
Section 9 I/O Ports 9.5.2 Port Data Register 8 (PDR8) PDR8 is a general I/O port data register of port 8. Bit Bit Name Initial Value R/W Description 7 P87 0 R/W PDR8 stores output data for port 8 pins. 6 P86 0 R/W 5 P85 0 R/W 4 P84 0 R/W If PDR8 is read while PCR8 bits are set to 1, the value stored in PDR8 is read. If PDR8 is read while PCR8 bits are cleared to 0, the pin states are read regardless of the value stored in PDR8.
Section 9 I/O Ports P85 pin Register PCR8 Bit Name PCR85 Pin Function Setting Value 0 P85 input pin 1 P85 output pin P84/FTIOD pin Register TIOR1 PCR8 Bit Name IOD2 IOD1 IOD0 PCR84 Pin Function Setting Value 0 0 0 0 P84 input/FTIOD input pin 1 P84 output/FTIOD input pin X FTIOD output pin 0 0 1 0 1 X X FTIOD output pin 1 X X 0 P84 input/FTIOD input pin 1 P84 output/FTIOD input pin Legend: X: Don't care.
Section 9 I/O Ports P82/FTIOB pin Register TIOR0 PCR8 Bit Name IOB2 IOB1 IOB0 PCR82 Pin Function Setting Value 0 0 0 0 P82 input/FTIOB input pin 1 P82 output/FTIOB input pin 0 0 1 X FTIOB output pin 0 1 X X FTIOB output pin 1 X X 0 P82 input/FTIOB input pin 1 P82 output/FTIOB input pin Legend: X: Don't care.
Section 9 I/O Ports 9.6 Port B Port B is an input port also functioning as an A/D converter analog input pin. Each pin of the port B is shown in figure 9.6. PB7/AN7 PB6/AN6 PB5/AN5 Port B PB4/AN4 PB3/AN3 PB2/AN2 PB1/AN1 PB0/AN0 Figure 9.6 Port B Pin Configuration Port B has the following register. • Port data register B (PDRB) 9.6.1 Port Data Register B (PDRB) PDRB is a general input-only port data register of port B.
Section 10 Timer A Section 10 Timer A Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock time-base function is available when a 32.768kHz crystal oscillator is connected. Figure 10.1 shows a block diagram of timer A. 10.1 Features • Timer A can be used as an interval timer or a clock time base. • An interrupt is requested when the counter overflows. • Any of eight clock signals can be output from pin TMOW: 32.
Section 10 Timer A 1/4 PSW φW/4 φW/32 φW/16 φW/8 φW/4 TMA Internal data bus φW φW/128 φ ÷256* ÷64* φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32, φ/8 ÷8* φW/32 φW/16 φW/8 φW/4 ÷128* TCA TMOW PSS IRRTA [Legend] TMA: Timer mode register A TCA: Timer counter A IRRTA: Timer A overflow interrupt request flag PSW: Prescaler W PSS: Prescaler S Note: * Can be selected only when the prescaler W output (φW/128) is used as the TCA input clock. Figure 10.1 Block Diagram of Timer A 10.
Section 10 Timer A 10.3 Register Descriptions Timer A has the following registers. • Timer mode register A (TMA) • Timer counter A (TCA) 10.3.1 Timer Mode Register A (TMA) TMA selects the operating mode, the divided clock output, and the input clock. Bit Bit Name Initial Value R/W Description 7 TMA7 0 R/W Clock Output Select 7 to 5 6 TMA6 0 R/W These bits select the clock output at the TMOW pin.
Section 10 Timer A Bit Bit Name Initial Value R/W Description 2 TMA2 0 R/W Internal Clock Select 2 to 0 1 TMA1 0 R/W These bits select the clock input to TCA when TMA3 = 0. 0 TMA0 0 R/W 000: φ/8192 001: φ/4096 010: φ/2048 011: φ/512 100: φ/256 101: φ/128 110: φ/32 111: φ/8 These bits select the overflow period when TMA3 = 1 (when a 32.768 kHz crystal oscillator with is used as φW). 000: 1s 001: 0.5 s 010: 0.25 s 011: 0.03125 s 1XX: Both PSW and TCA are reset Legend: X: Don't care. 10.
Section 10 Timer A 10.4 Operation 10.4.1 Interval Timer Operation When bit TMA3 in TMA is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting of timer A resume immediately as an interval timer. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected.
Section 10 Timer A Rev.5.00 Nov.
Section 11 Timer V Section 11 Timer V Timer V is an 8-bit timer based on an 8-bit counter. Timer V counts external events. Comparematch signals with two registers can also be used to reset the counter, request an interrupt, or output a pulse signal with an arbitrary duty cycle. Counting can be initiated by a trigger input at the TRGV pin, enabling pulse output control to be synchronized to the trigger, with an arbitrary delay from the trigger input. Figure 11.1 shows a block diagram of timer V. 11.
Section 11 Timer V TCRV1 TCORB Trigger control TRGV Comparator Clock select TCNTV Internal data bus TMCIV Comparator φ PSS TCORA Clear control TMRIV TCRV0 Interrupt request control Output control TMOV [Legend] TCORA: TCORB: TCNTV: TCSRV: TCRV0: TCRV1: PSS: CMIA: CMIB: OVI: TCSRV CMIA CMIB OVI Time constant register A Time constant register B Timer counter V Timer control/status register V Timer control register V0 Timer control register V1 Prescaler S Compare-match interrupt A Compare-match
Section 11 Timer V 11.3 Register Descriptions Time V has the following registers. • • • • • • Timer counter V (TCNTV) Timer constant register A (TCORA) Timer constant register B (TCORB) Timer control register V0 (TCRV0) Timer control/status register V (TCSRV) Timer control register V1 (TCRV1) 11.3.1 Timer Counter V (TCNTV) TCNTV is an 8-bit up-counter. The clock source is selected by bits CKS2 to CKS0 in timer control register V0 (TCRV0).
Section 11 Timer V 11.3.3 Timer Control Register V0 (TCRV0) TCRV0 selects the input clock signals of TCNTV, specifies the clearing conditions of TCNTV, and controls each interrupt request. Bit Bit Name Initial Value R/W Description 7 CMIEB 0 R/W Compare Match Interrupt Enable B When this bit is set to 1, interrupt request from the CMFB bit in TCSRV is enabled. 6 CMIEA 0 R/W Compare Match Interrupt Enable A When this bit is set to 1, interrupt request from the CMFA bit in TCSRV is enabled.
Section 11 Timer V Table 11.
Section 11 Timer V 11.3.4 Timer Control/Status Register V (TCSRV) TCSRV indicates the status flag and controls outputs by using a compare match.
Section 11 Timer V OS3 and OS2 select the output level for compare match B. OS1 and OS0 select the output level for compare match A. The two output levels can be controlled independently. After a reset, the timer output is 0 until the first compare match. 11.3.5 Timer Control Register V1 (TCRV1) TCRV1 selects the edge at the TRGV pin, enables TRGV input, and selects the clock input to TCNTV. Bit Bit Name Initial Value R/W Description 7 to 5 All 1 Reserved These bits are always read as 1.
Section 11 Timer V 11.4 Operation 11.4.1 Timer V Operation 1. According to table 11.2, six internal/external clock signals output by prescaler S can be selected as the timer V operating clock signals. When the operating clock signal is selected, TCNTV starts counting-up. Figure 11.2 shows the count timing with an internal clock signal selected, and figure 11.3 shows the count timing with both edges of an external clock signal selected. 2.
Section 11 Timer V φ Internal clock TCNTV input clock TCNTV N–1 N N+1 Figure 11.2 Increment Timing with Internal Clock φ TMCIV (External clock input pin) TCNTV input clock TCNTV N–1 N N+1 Figure 11.3 Increment Timing with External Clock φ TCNTV H'FF H'00 Overflow signal OVF Figure 11.4 OVF Set Timing Rev.5.00 Nov.
Section 11 Timer V φ TCNTV N TCORA or TCORB N N+1 Compare match signal CMFA or CMFB Figure 11.5 CMFA and CMFB Set Timing φ Compare match A signal Timer V output pin Figure 11.6 TMOV Output Timing φ Compare match A signal TCNTV N H'00 Figure 11.7 Clear Timing by Compare Match Rev.5.00 Nov.
Section 11 Timer V φ TMRIV(External counter reset input pin ) TCNTV reset signal TCNTV N–1 N H'00 Figure 11.8 Clear Timing by TMRIV Input Rev.5.00 Nov.
Section 11 Timer V 11.5 Timer V Application Examples 11.5.1 Pulse Output with Arbitrary Duty Cycle Figure 11.9 shows an example of output of pulses with an arbitrary duty cycle. 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORA. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3. Set bits CKS2 to CKS0 in TCRV0 and bit ICKS0 in TCRV1 to select the desired clock source. 4.
Section 11 Timer V 11.5.2 Pulse Output with Arbitrary Pulse Width and Delay from TRGV Input The trigger function can be used to output a pulse with an arbitrary pulse width at an arbitrary delay from the TRGV input, as shown in figure 11.10. To set up this output: 1. Set bits CCLR1 and CCLR0 in TCRV0 so that TCNTV will be cleared by compare match with TCORB. 2. Set bits OS3 to OS0 in TCSRV so that the output will go to 1 at compare match with TCORA and to 0 at compare match with TCORB. 3.
Section 11 Timer V 11.6 Usage Notes The following types of contention or operation can occur in timer V operation. 1. 2. 3. 4. Writing to registers is performed in the T3 state of a TCNTV write cycle. If a TCNTV clear signal is generated in the T3 state of a TCNTV write cycle, as shown in figure 11.11, clearing takes precedence and the write to the counter is not carried out. If counting-up is generated in the T3 state of a TCNTV write cycle, writing takes precedence.
Section 11 Timer V TCORA write cycle by CPU T2 T1 T3 φ Address TCORA address Internal write signal TCNTV N N+1 TCORA N M TCORA write data Compare match signal Inhibited Figure 11.12 Contention between TCORA Write and Compare Match Clock before switching Clock after switching Count clock TCNTV N N+1 N+2 Write to CKS1 and CKS0 Figure 11.13 Internal Clock Switching and TCNTV Operation Rev.5.00 Nov.
Section 11 Timer V Rev.5.00 Nov.
Section 12 Timer W Section 12 Timer W The timer W has a 16-bit timer having output compare and input capture functions. The timer W can count external events and output pulses with an arbitrary duty cycle by compare match between the timer counter and four general registers. Thus, it can be applied to various systems. 12.
Section 12 Timer W Table 12.
Section 12 Timer W Internal clock: φ φ/2 φ/4 φ/8 External clock: FTCI FTIOA Clock selector FTIOB FTIOC Control logic FTIOD Comparator TIOR TSRW TIERW TCRW TMRW GRD GRC GRB Bus interface [Legend] TMRW: TCRW: TIERW: TSRW: TIOR: TCNT: GRA: GRB: GRC: GRD: IRRTW: GRA TCNT IRRTW Internal data bus Timer mode register W (8 bits) Timer control register W (8 bits) Timer interrupt enable register W (8 bits) Timer status register W (8 bits) Timer I/O control register (8 bits) Timer counter (16 bits
Section 12 Timer W 12.2 Input/Output Pins Table 12.2 summarizes the timer W pins. Table 12.
Section 12 Timer W 12.3.1 Timer Mode Register W (TMRW) TMRW selects the general register functions and the timer output mode. Bit Bit Name Initial Value R/W Description 7 CTS 0 R/W Counter Start The counter operation is halted when this bit is 0, while it can be performed when this bit is 1. 6 1 Reserved This bit is always read as 1. 5 BUFEB 0 R/W Buffer Operation B Selects the GRD function.
Section 12 Timer W 12.3.2 Timer Control Register W (TCRW) TCRW selects the timer counter clock source, selects a clearing condition, and specifies the timer output levels. Bit Bit Name Initial Value R/W Description 7 CCLR 0 R/W Counter Clear The TCNT value is cleared by compare match A when this bit is 1. When it is 0, TCNT operates as a freerunning counter. 6 CKS2 0 R/W Clock Select 2 to 0 5 CKS1 0 R/W Select the TCNT clock source.
Section 12 Timer W Bit Bit Name Initial Value R/W Description 0 TOA 0 R/W Timer Output Level Setting A Sets the output value of the FTIOA pin until the first compare match A is generated. 0: Output value is 0* 1: Output value is 1* Legend: Note: * 12.3.3 X: Don't care. The change of the setting is immediately reflected in the output value. Timer Interrupt Enable Register W (TIERW) TIERW controls the timer W interrupt request.
Section 12 Timer W 12.3.4 Timer Status Register W (TSRW) TSRW shows the status of interrupt requests. Bit Bit Name Initial Value R/W Description 7 OVF 0 R/W Timer Overflow Flag [Setting condition] When TCNT overflows from H'FFFF to H'0000 [Clearing condition] Read OVF when OVF = 1, then write 0 in OVF 6 to 4 All 1 Reserved These bits are always read as 1.
Section 12 Timer W Bit Bit Name Initial Value R/W Description 1 IMFB 0 R/W Input Capture/Compare Match Flag B [Setting conditions] • TCNT = GRB when GRB functions as an output compare register • The TCNT value is transferred to GRB by an input capture signal when GRB functions as an input capture register [Clearing condition] Read IMFB when IMFB = 1, then write 0 in IMFB 0 IMFA 0 R/W Input Capture/Compare Match Flag A [Setting conditions] • TCNT = GRA when GRA functions as an output compa
Section 12 Timer W Bit Bit Name Initial Value R/W Description 5 IOB1 0 R/W I/O Control B1 and B0 4 IOB0 0 R/W When IOB2 = 0, 00: No output at compare match 01: 0 output to the FTIOB pin at GRB compare match 10: 1 output to the FTIOB pin at GRB compare match 11: Output toggles to the FTIOB pin at GRB compare match When IOB2 = 1, 00: Input capture at rising edge at the FTIOB pin 01: Input capture at falling edge at the FTIOB pin 1X: Input capture at rising and falling edges of the FTIOB pin 3
Section 12 Timer W 12.3.6 Timer I/O Control Register 1 (TIOR1) TIOR1 selects the functions of GRC and GRD, and specifies the functions of the FTIOC and FTIOD pins. Bit Bit Name Initial Value R/W Description 7 1 Reserved 6 IOD2 0 R/W This bit is always read as 1. I/O Control D2 Selects the GRD function.
Section 12 Timer W Bit Bit Name Initial Value R/W Description 1 IOC1 0 R/W I/O Control C1 and C0 0 IOC0 0 R/W When IOC2 = 0, 00: No output at compare match 01: 0 output to the FTIOC pin at GRC compare match 10: 1 output to the FTIOC pin at GRC compare match 11: Output toggles to the FTIOC pin at GRC compare match When IOC2 = 1, 00: Input capture to GRC at rising edge of the FTIOC pin 01: Input capture to GRC at falling edge of the FTIOC pin 1X: Input capture to GRC at rising and falling edges
Section 12 Timer W (IMIEA, IMIEB, IMIEC, or IMIED) in TSRW is set to 1 at this time, an interrupt request is generated. The edge of the input-capture signal is selected in TIOR. GRC and GRD can be used as buffer registers of GRA and GRB, respectively, by setting BUFEA and BUFEB in TMRW. For example, when GRA is set as an output-compare register and GRC is set as the buffer register for GRA, the value in the buffer register GRC is sent to GRA whenever compare match A is generated.
Section 12 Timer W TCNT value H'FFFF H'0000 Time CTS bit Flag cleared by software OVF Figure 12.2 Free-Running Counter Operation Periodic counting operation can be performed when GRA is set as an output compare register and bit CCLR in TCRW is set to 1. When the count matches GRA, TCNT is cleared to H'0000, the IMFA flag in TSRW is set to 1. If the corresponding IMIEA bit in TIERW is set to 1, an interrupt request is generated. TCNT continues counting from H'0000. Figure 12.3 shows periodic counting.
Section 12 Timer W TCNT value H'FFFF GRA GRB Time H'0000 FTIOA FTIOB No change No change No change No change Figure 12.4 0 and 1 Output Example (TOA = 0, TOB = 1) Figure 12.5 shows an example of toggle output when TCNT operates as a free-running counter, and toggle output is selected for both compare match A and B. TCNT value H'FFFF GRA GRB Time H'0000 FTIOA Toggle output FTIOB Toggle output Figure 12.5 Toggle Output Example (TOA = 0, TOB = 1) Figure 12.
Section 12 Timer W The TCNT value can be captured into a general register (GRA, GRB, GRC, or GRD) when a signal level changes at an input-capture pin (FTIOA, FTIOB, FTIOC, or FTIOD). Capture can take place on the rising edge, falling edge, or both edges. By using the input-capture function, the pulse width and periods can be measured. Figure 12.7 shows an example of input capture when both edges of FTIOA and the falling edge of FTIOB are selected as capture edges. TCNT operates as a free-running counter.
Section 12 Timer W TCNT value H'FFFF H'DA91 H'5480 H'0245 H'0000 Time FTIOA GRA GRC H'0245 H'5480 H'DA91 H'0245 H'5480 Figure 12.8 Buffer Operation Example (Input Capture) 12.4.2 PWM Operation In PWM mode, PWM waveforms are generated by using GRA as the period register and GRB, GRC, and GRD as duty registers. PWM waveforms are output from the FTIOB, FTIOC, and FTIOD pins. Up to three-phase PWM waveforms can be output.
Section 12 Timer W TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.9 PWM Mode Example (1) Figure 12.10 shows another example of operation in PWM mode. The output signals go to 0 and TCNT is cleared at compare match A, and the output signals go to 1 at compare match B, C, and D (TOB, TOC, and TOD = 0: initial output values are set to 1). TCNT value Counter cleared by compare match A GRA GRB GRC GRD H'0000 Time FTIOB FTIOC FTIOD Figure 12.
Section 12 Timer W Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB outputs 1 at compare match B and 0 at compare match A. Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD is transferred to GRB whenever compare match B occurs. This procedure is repeated every time compare match B occurs.
Section 12 Timer W TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 0% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 100% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 100% FTIOB Duty 0% Figure 12.
Section 12 Timer W TCNT value Write to GRB GRA GRB Write to GRB H'0000 Time Duty 100% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 Time Duty 0% FTIOB TCNT value Output does not change when cycle register and duty register compare matches occur simultaneously. Write to GRB GRA Write to GRB Write to GRB GRB H'0000 FTIOB Time Duty 0% Duty 100% Figure 12.
Section 12 Timer W 12.5 Operation Timing 12.5.1 TCNT Count Timing Figure 12.14 shows the TCNT count timing when the internal clock source is selected. Figure 12.15 shows the timing when the external clock source is selected. The pulse width of the external clock signal must be at least two system clock (φ) cycles; shorter pulses will not be counted correctly. φ Internal clock Rising edge TCNT input clock TCNT N N+1 N+2 Figure 12.
Section 12 Timer W Figure 12.16 shows the output compare timing. φ TCNT input clock TCNT N GRA to GRD N N+1 Compare match signal FTIOA to FTIOD Figure 12.16 Output Compare Output Timing 12.5.3 Input Capture Timing Input capture on the rising edge, falling edge, or both edges can be selected through settings in TIOR0 and TIOR1. Figure 12.17 shows the timing when the falling edge is selected.
Section 12 Timer W 12.5.4 Timing of Counter Clearing by Compare Match Figure 12.18 shows the timing when the counter is cleared by compare match A. When the GRA value is N, the counter counts from 0 to N, and its cycle is N + 1. φ Compare match signal TCNT N GRA N H'0000 Figure 12.18 Timing of Counter Clearing by Compare Match 12.5.5 Buffer Operation Timing Figures 12.19 and 12.20 show the buffer operation timing. φ Compare match signal TCNT N GRC, GRD M GRA, GRB N+1 M Figure 12.
Section 12 Timer W φ Input capture signal TCNT N GRA, GRB M GRC, GRD N+1 N N+1 M N Figure 12.20 Buffer Operation Timing (Input Capture) 12.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match If a general register (GRA, GRB, GRC, or GRD) is used as an output compare register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when TCNT matches the general register.
Section 12 Timer W 12.5.7 Timing of IMFA to IMFD Setting at Input Capture If a general register (GRA, GRB, GRC, or GRD) is used as an input capture register, the corresponding IMFA, IMFB, IMFC, or IMFD flag is set to 1 when an input capture occurs. Figure 12.22 shows the timing of the IMFA to IMFD flag setting at input capture. φ Input capture signal N TCNT N GRA to GRD IMFA to IMFD IRRTW Figure 12.22 Timing of IMFA to IMFD Flag Setting at Input Capture 12.5.
Section 12 Timer W 12.6 Usage Notes The following types of contention or operation can occur in timer W operation. 1. The pulse width of the input clock signal and the input capture signal must be at least two system clock (φ) cycles; shorter pulses will not be detected correctly. 2. Writing to registers is performed in the T2 state of a TCNT write cycle.
Section 12 Timer W Previous clock New clock Count clock TCNT N N+1 N+2 N+3 The change in signal level at clock switching is assumed to be a rising edge, and TCNT increments the count. Figure 12.25 Internal Clock Switching and TCNT Operation Rev.5.00 Nov.
Section 12 Timer W 5. The TOA to TOD bits in TCRW decide the value of the FTIO pin, which is output until the first compare match occurs. Once a compare match occurs and this compare match changes the values of FTIOA to FTIOD output, the values of the FTIOA to FTIOD pin output and the values read from the TOA to TOD bits may differ. Moreover, when the writing to TCRW and the generation of the compare match A to D occur at the same timing, the writing to TCRW has the priority.
Section 12 Timer W Rev.5.00 Nov.
Section 13 Watchdog Timer Section 13 Watchdog Timer The watchdog timer is an 8-bit timer that can generate an internal reset signal for this LSI if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. The block diagram of the watchdog timer is shown in figure 13.1.
Section 13 Watchdog Timer 13.2 Register Descriptions The watchdog timer has the following registers. • Timer control/status register WD (TCSRWD) • Timer counter WD (TCWD) • Timer mode register WD (TMWD) 13.2.1 Timer Control/Status Register WD (TCSRWD) TCSRWD performs the TCSRWD and TCWD write control. TCSRWD also controls the watchdog timer operation and indicates the operating state. TCSRWD must be rewritten by using the MOV instruction.
Section 13 Watchdog Timer Bit Bit Name Initial Value R/W Description 2 WDON 0 R/W Watchdog Timer On TCWD starts counting up when WDON is set to 1 and halts when WDON is cleared to 0.
Section 13 Watchdog Timer 13.2.3 Timer Mode Register WD (TMWD) TMWD selects the input clock. Bit Bit Name Initial Value R/W 7 to 4 All 1 Description Reserved These bits are always read as 1. 3 CKS3 1 R/W Clock Select 3 to 0 2 CKS2 1 R/W Select the clock to be input to TCWD.
Section 13 Watchdog Timer 13.3 Operation The watchdog timer is provided with an 8-bit counter. If 1 is written to WDON while writing 0 to B2WI when the TCSRWE bit in TCSRWD is set to 1, TCWD begins counting up. (To operate the watchdog timer, two write accesses to TCSRWD are required.) When a clock pulse is input after the TCWD count value has reached H'FF, the watchdog timer overflows and an internal reset signal is generated. The internal reset signal is output for a period of 256 φosc clock cycles.
Section 13 Watchdog Timer Rev.5.00 Nov.
Section 14 Serial Communication Interface 3 (SCI3) Section 14 Serial Communication Interface 3 (SCI3) Serial Communication Interface 3 (SCI3) can handle both asynchronous and clocked synchronous serial communication. In the asynchronous method, serial data communication can be carried out using standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface Adapter (ACIA).
Section 14 Serial Communication Interface 3 (SCI3) SCK3 External clock Internal clock (φ/64, φ/16, φ/4, φ) Baud rate generator BRC BRR SMR Transmit/receive control circuit SCR3 SSR TXD TSR TDR RXD RSR RDR [Legend] Receive shift register RSR: Receive data register RDR: Transmit shift register TSR: Transmit data register TDR: Serial mode register SMR: SCR3: Serial control register 3 Serial status register SSR: Bit rate register BRR: Bit rate counter BRC: Figure 14.1 Block Diagram of SCI3 Rev.
Section 14 Serial Communication Interface 3 (SCI3) 14.2 Input/Output Pins Table 14.1 shows the SCI3 pin configuration. Table 14.1 Pin Configuration Pin Name Abbreviation I/O Function SCI3 clock SCK3 I/O SCI3 clock input/output SCI3 receive data input RXD Input SCI3 receive data input SCI3 transmit data output TXD Output SCI3 transmit data output 14.3 Register Descriptions The SCI3 has the following registers.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.1 Receive Shift Register (RSR) RSR is a shift register that is used to receive serial data input from the RxD pin and convert it into parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 14.3.2 Receive Data Register (RDR) RDR is an 8-bit register that stores received data.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.5 Serial Mode Register (SMR) SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator clock source. Bit Bit Name Initial Value R/W Description 7 COM 0 R/W Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode 6 CHR 0 R/W Character Length (enabled only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 0 and 1 0 CKS0 0 R/W These bits select the clock source for the on-chip baud rate generator. 00: φ clock (n = 0) 01: φ/4 clock (n = 1) 10: φ/16 clock (n = 2) 11: φ/64 clock (n = 3) For the relationship between the bit rate register setting and the baud rate, see section 14.3.8, Bit Rate Register (BRR). n is the decimal representation of the value of n in BRR (see section 14.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and OER status flags in SSR is prohibited. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed.
Section 14 Serial Communication Interface 3 (SCI3) 14.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI3 and multiprocessor bits for transfer. 1 cannot be written to flags TDRE, RDRF, OER, PER, and FER; they can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/W Transmit Data Register Empty Displays whether TDR contains transmit data.
Section 14 Serial Communication Interface 3 (SCI3) Bit Bit Name Initial Value R/W Description 3 PER 0 R/W Parity Error [Setting condition] • When a parity error is generated during reception [Clearing condition] • 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] • When the TE bit in SCR3 is 0 • When TDRE = 1 at transmission of the last bit of a 1byte serial transmit character [Clearing conditions] 1 MPBR 0 R • When 0 is written to TEND af
Section 14 Serial Communication Interface 3 (SCI3) 14.3.8 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. The initial value of BRR is H'FF. Table 14.2 shows the relationship between the N setting in BRR and the n setting in bits CKS1 and CKS0 of SMR in asynchronous mode. Table 14.3 shows the maximum bit rate for each frequency in asynchronous mode. The values shown in both tables 14.2 and 14.3 are values in active (highspeed) mode. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 2 2.097152 2.4576 3 Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 1 141 0.03 1 148 –0.04 1 174 –0.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728 8 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.2 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (3) Operating Frequency φ (MHz) 14 14.7456 16 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 248 –0.17 3 64 0.70 3 70 0.03 150 2 181 0.16 2 191 0.00 2 207 0.16 300 2 90 0.16 2 95 0.00 2 103 0.16 600 1 181 0.16 1 191 0.00 1 207 0.16 1200 1 90 0.16 1 95 0.00 1 103 0.16 2400 0 181 0.16 0 191 0.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.3 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) n N φ (MHz) Maximum Bit Rate (bit/s) n N 2 62500 0 0 8 250000 0 0 2.097152 65536 0 0 9.8304 307200 0 0 2.4576 76800 0 0 10 312500 0 0 3 93750 0 0 12 375000 0 0 3.6864 115200 0 0 12.288 384000 0 0 4 125000 0 0 14 437500 0 0 4.9152 153600 0 0 14.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.4 Examples of BBR Setting for Various Bit Rates (Clocked Synchronous Mode) (1) Operating Frequency φ (MHz) 2 4 8 10 Bit Rate (bit/s) n N n N n N n N 110 3 70 — — — — — — 250 2 124 2 249 3 124 — 500 1 249 2 124 2 249 — 16 n N — 3 249 — 3 124 1k 1 124 1 249 2 124 — — 2 249 2.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.4 Examples of BRR Settings for Various Bit Rates (Clocked Synchronous Mode) (2) Operating Frequency φ (MHz) 18 20 Bit Rate (bit/s) n N n N 110 — — — — 250 — — — — 500 3 140 3 155 1k 3 69 3 77 2.5k 2 112 2 124 5k 1 224 1 249 10k 1 112 1 124 25k 0 179 0 199 50k 0 89 0 99 100k 0 44 0 49 250k 0 17 0 19 500k 0 8 0 9 1M 0 4 0 4 2M — — — — 2.
Section 14 Serial Communication Interface 3 (SCI3) 14.4 Operation in Asynchronous Mode Figure 14.2 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), followed by data (in LSB-first order), a parity bit (high or low level), and finally stop bits (high level). Inside the SCI3, the transmitter and receiver are independent units, enabling full duplex.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.2 SCI3 Initialization Follow the flowchart as shown in figure 14.4 to initialize the SCI3. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and OER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.3 Data Transmission Figure 14.5 shows an example of operation for transmission in asynchronous mode. In transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI3 recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI3 sets the TDRE flag to 1 and starts transmission.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] Read TDRE flag in SSR No TDRE = 1 Yes Write transmit data to TDR Yes [2] All data transmitted? [1] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automaticaly cleared to 0. [2] To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 14 Serial Communication Interface 3 (SCI3) 14.4.4 Serial Data Reception Figure 14.7 shows an example of operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI3 monitors the communication line. If a start bit is detected, the SCI3 performs internal synchronization, receives data in RSR, and checks the parity bit and stop bit. 2.
Section 14 Serial Communication Interface 3 (SCI3) Table 14.5 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the OER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 14.8 shows a sample flowchart for serial data reception. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) Start reception Read OER, PER, and FER flags in SSR [1] Yes OER+PER+FER = 1 [4] No Error processing (Continued on next page) Read RDRF flag in SSR [2] No RDRF = 1 Yes Read receive data in RDR [1] Read the OER, PER, and FER flags in SSR to identify the error. If a receive error occurs, performs the appropriate error processing. [2] Read SSR and check that RDRF = 1, then read the receive data in RDR. The RDRF flag is cleared automatically.
Section 14 Serial Communication Interface 3 (SCI3) [4] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing No PER = 1 Yes Parity error processing (A) Clear OER, PER, and FER flags in SSR to 0 Figure 14.8 Sample Serial Reception Data Flowchart (2) Rev.5.00 Nov.
Section 14 Serial Communication Interface 3 (SCI3) 14.5 Operation in Clocked Synchronous Mode Figure 14.9 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received synchronous with clock pulses. A single character in the transmit data consists of the 8-bit data starting from the LSB. In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.3 Serial Data Transmission Figure 14.10 shows an example of SCI3 operation for transmission in clocked synchronous mode. In serial transmission, the SCI3 operates as described below. 1. The SCI3 monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. The SCI3 sets the TDRE flag to 1 and starts transmission.
Section 14 Serial Communication Interface 3 (SCI3) Serial clock Serial data Bit 0 Bit 1 1 frame Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 1 frame TDRE TEND LSI TXI interrupt operation request generated TDRE flag cleared to 0 User processing Data written to TDR TXI interrupt request generated TEI interrupt request generated Figure 14.10 Example of SCI3 Operation in Transmission in Clocked Synchronous Mode Rev.5.00 Nov.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 Yes [2] Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0 and clocks are output to start the data transmission. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.4 Serial Data Reception (Clocked Synchronous Mode) Figure 14.12 shows an example of SCI3 operation for reception in clocked synchronous mode. In serial reception, the SCI3 operates as described below. 1. The SCI3 performs internal initialization synchronous with a synchronous clock input or output, starts receiving data. 2. The SCI3 stores the received data in RSR. 3.
Section 14 Serial Communication Interface 3 (SCI3) Start reception [1] [1] Read OER flag in SSR [2] Yes OER = 1 [4] No Error processing [3] (Continued below) Read RDRF flag in SSR [2] [4] No RDRF = 1 Yes Read the OER flag in SSR to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR. When data is read from RDR, the RDRF flag is automatically cleared to 0.
Section 14 Serial Communication Interface 3 (SCI3) 14.5.5 Simultaneous Serial Data Transmission and Reception Figure 14.14 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI3 has finished transmission and the TDRE and TEND flags are set to 1, clear TE to 0.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission/reception Read TDRE flag in SSR [1] [1] No TDRE = 1 Yes Write transmit data to TDR Read OER flag in SSR OER = 1 No Read RDRF flag in SSR Yes [4] Error processing [2] No RDRF = 1 Yes Read receive data in RDR Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0.
Section 14 Serial Communication Interface 3 (SCI3) 14.6 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer between a number of processors sharing communication lines by asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is performed, each receiving station is addressed by a unique ID code.
Section 14 Serial Communication Interface 3 (SCI3) Transmitting station Serial transmission line Receiving station A Receiving station B Receiving station C Receiving station D (ID = 01) (ID = 02) (ID = 03) (ID = 04) Serial data H'01 H'AA (MPB = 1) (MPB = 0) ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit Figure 14.
Section 14 Serial Communication Interface 3 (SCI3) Start transmission [1] [1] Read TDRE flag in SSR No TDRE = 1 [2] Yes Set MPBT bit in SSR [3] Write transmit data to TDR Yes [2] Read SSR and check that the TDRE flag is set to 1, set the MPBT bit in SSR to 0 or 1, then write transmit data to TDR. When data is written to TDR, the TDRE flag is automatically cleared to 0. To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR.
Section 14 Serial Communication Interface 3 (SCI3) 14.6.2 Multiprocessor Serial Data Reception Figure 14.17 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR3 is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI3 operations are the same as in asynchronous mode. Figure 14.
Section 14 Serial Communication Interface 3 (SCI3) [1] [2] Start reception Set MPIE bit in SCR3 to 1 [1] Read OER and FER flags in SSR [2] [3] Yes FER+OER = 1 No Read RDRF flag in SSR [3] No [4] [5] RDRF = 1 Yes Read receive data in RDR No This station’s ID? Set the MPIE bit in SCR3 to 1. Read OER and FER in SSR to check for errors. Receive error processing is performed in cases where a receive error occurs.
Section 14 Serial Communication Interface 3 (SCI3) [5] Error processing No OER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No [A] Framing error processing Clear OER, and FER flags in SSR to 0 Figure 14.17 Sample Multiprocessor Serial Reception Flowchart (2) Rev.5.00 Nov.
Section 14 Serial Communication Interface 3 (SCI3) Start bit Serial data 1 0 Receive data (ID1) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Receive data (Data1) D0 1 frame D1 D7 MPB Stop bit Mark state (idle state) 0 1 1 1 frame MPIE RDRF RDR value ID1 LSI operation RDRF flag cleared to 0 RXI interrupt request MPIE cleared to 0 User processing RXI interrupt request is not generated, and RDR retains its state RDR data read When data is not this station's ID, MPIE is set to 1 again (a
Section 14 Serial Communication Interface 3 (SCI3) 14.7 Interrupts The SCI3 creates the following six interrupt requests: transmission end, transmit data empty, receive data full, and receive errors (overrun error, framing error, and parity error). Table 14.6 shows the interrupt sources. Table 14.
Section 14 Serial Communication Interface 3 (SCI3) 14.8 Usage Notes 14.8.1 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0, setting the FER flag, and possibly the PER flag. Note that as the SCI3 continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 14.8.
Section 14 Serial Communication Interface 3 (SCI3) 14.8.4 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI3 operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI3 samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock as shown in figure 14.19.
2 Section 15 I C Bus Interface 2 (IIC2) Section 15 I2C Bus Interface 2 (IIC2) The I2C bus interface 2 conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 15.1 shows a block diagram of the I2C bus interface 2. Figure 15.2 shows an example of I/O pin connections to external circuits. 15.
2 Section 15 I C Bus Interface 2 (IIC2) Transfer clock generation circuit SCL Transmission/ reception control circuit Output control ICCR1 ICCR2 ICMR Internal data bus Noise canceler ICDRT SDA Output control ICDRS SAR Address comparator Noise canceler ICDRR Bus state decision circuit Arbitration decision circuit ICSR ICIER [Legend] ICCR1 : I2C bus control register 1 ICCR2 : I2C bus control register 2 ICMR : I2C bus mode register ICSR : I2C bus status register ICIER : I2C bus interrupt enabl
2 Section 15 I C Bus Interface 2 (IIC2) Vcc SCL in Vcc SCL SCL SDA SDA SCL out SDA in SCL in SCL out SCL SDA (Master) SCL SDA SDA out SCL in SCL out SDA in SDA in SDA out SDA out (Slave 1) (Slave 2) Figure 15.2 External Circuit Connections of I/O Pins 15.2 Input/Output Pins Table 15.1 summarizes the input/output pins used by the I2C bus interface 2. Table 15.
2 Section 15 I C Bus Interface 2 (IIC2) • I2C bus transmit data register (ICDRT) • I2C bus receive data register (ICDRR) • I2C bus shift register (ICDRS) 15.3.1 I2C Bus Control Register 1 (ICCR1) ICCR1 enables or disables the I2C bus interface 2, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I2C Bus Interface Enable 0: This module is halted.
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 3 CKS3 0 R/W Transfer Clock Select 3 to 0 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W These bits should be set according to the necessary transfer rate (see table 15.2) in master mode. In slave mode, these bits are used for reservation of the setup time in transmit mode. The time is 10 tcyc when CKS3 = 0 and 20 tcyc when CKS3 = 1. Table 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.3.2 I2C Bus Control Register 2 (ICCR2) ICCR1 issues start/stop conditions, manipulates the SDA pin, monitors the SCL pin, and controls reset in the control part of the I2C bus interface 2. Bit Bit Name Initial Value R/W Description 7 BBSY 0 R/W Bus Busy 2 This bit enables to confirm whether the I C bus is occupied or released and to issue start/stop conditions in master mode. With the clocked synchronous serial 2 format, this bit has no meaning.
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 SDAOP 1 R/W SDAO Write Protect This bit controls change of output level of the SDA pin by modifying the SDAO bit. To change the output level, clear SDAO and SDAOP to 0 or set SDAO to 1 and clear SDAOP to 0 by the MOV instruction. This bit is always read as 1. 3 SCLO 1 R This bit monitors SCL output level. When SCLO is 1, SCL pin outputs high. When SCLO is 0, SCL pin outputs low.
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 5, 4 All 1 Reserved 3 BCWP 1 R/W These bits are always read as 1, and cannot be modified. BC Write Protect This bit controls the BC2 to BC0 modifications. When modifying BC2 to BC0, this bit should be cleared to 0 and use the MOV instruction. In clock synchronous serial mode, BC should not be modified. 0: When writing, values of BC2 to BC0 are set. 1: When reading, 1 is always read.
2 Section 15 I C Bus Interface 2 (IIC2) 15.3.4 I2C Bus Interrupt Enable Register (ICIER) ICIER enables or disables interrupt sources and acknowledge bits, sets acknowledge bits to be transferred, and confirms acknowledge bits to be received. Bit Bit Name Initial Value R/W Description 7 TIE 0 R/W Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI). 0: Transmit data empty interrupt request (TXI) is disabled.
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 3 STIE 0 R/W Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt request (STPI) is disabled. 1: Stop condition detection interrupt request (STPI) is enabled. 2 ACKE 0 R/W Acknowledge Bit Judgement Select 0: The value of the receive acknowledge bit is ignored, and continuous transfer is performed. 1: If the receive acknowledge bit is 1, continuous transfer is halted.
2 Section 15 I C Bus Interface 2 (IIC2) 15.3.5 I2C Bus Status Register (ICSR) ICSR performs confirmation of interrupt request flags and status.
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 4 NACKF 0 R/W No Acknowledge Detection Flag [Setting condition] • When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is 1 [Clearing condition] • 3 STOP 0 R/W When 0 is written in NACKF after reading NACKF = 1 Stop Condition Detection Flag [Setting conditions] • In master mode, when a stop condition is detected after frame transfer • In slave mode, when a st
2 Section 15 I C Bus Interface 2 (IIC2) Bit Bit Name Initial Value R/W Description 2 AL/OVE 0 R/W Arbitration Lost Flag/Overrun Error Flag This flag indicates that arbitration was lost in master mode with the I2C bus format and that the final bit has been received while RDRF = 1 with the clocked synchronous format.
2 Section 15 I C Bus Interface 2 (IIC2) 15.3.6 Slave Address Register (SAR) SAR selects the communication format and sets the slave address. When the chip is in slave mode with the I2C bus format, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the chip operates as the slave device.
2 Section 15 I C Bus Interface 2 (IIC2) 15.3.7 I2C Bus Transmit Data Register (ICDRT) ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to ICDRS and starts transferring data. If the next transfer data is written to ICDRT during transferring data of ICDRS, continuous transfer is possible.
2 Section 15 I C Bus Interface 2 (IIC2) 15.4 Operation The I2C bus interface can communicate either in I2C bus mode or clocked synchronous serial mode by setting FS in SAR. 15.4.1 I2C Bus Format Figure 15.3 shows the I2C bus formats. Figure 15.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
2 Section 15 I C Bus Interface 2 (IIC2) R/W: Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA to low. DATA: Transfer data P: Stop condition. The master device drives SDA from low to high while SCL is high. 15.4.
2 Section 15 I C Bus Interface 2 (IIC2) SCL (Master output) 1 2 3 4 5 6 SDA (Master output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 7 8 Bit 1 Slave address 9 1 Bit 0 Bit 7 2 Bit 6 R/W SDA (Slave output) A TDRE TEND Address + R/W ICDRT ICDRS User processing Data 1 Address + R/W [2] Instruction of start condition issuance Data 2 Data 1 [4] Write data to ICDRT (second byte) [5] Write data to ICDRT (third byte) [3] Write data to ICDRT (first byte) Figure 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.4.3 Master Receive Operation In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. For master receive mode operation timing, refer to figures 15.7 and 15.8. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCR1 to 0 to switch from master transmit mode to master receive mode.
2 Section 15 I C Bus Interface 2 (IIC2) Master transmit mode SCL (Master output) Master receive mode 9 1 2 3 4 5 6 7 8 SDA (Master output) 9 1 A SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS RDRF ICDRS Data 1 ICDRR User processing Data 1 [3] Read ICDRR [1] Clear TDRE after clearing TEND and TRS [2] Read ICDRR (dummy read) Figure 15.7 Master Receive Mode Operation Timing (1) Rev.5.00 Nov.
2 Section 15 I C Bus Interface 2 (IIC2) SCL (Master output) 9 SDA (Master output) A SDA (Slave output) 1 2 3 4 5 6 7 8 9 A/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RDRF RCVD ICDRS Data n Data n-1 ICDRR Data n Data n-1 User processing [5] Read ICDRR after setting RCVD [7] Read ICDRR, and clear RCVD [6] Issue stop condition [8] Set slave receive mode Figure 15.8 Master Receive Mode Operation Timing (2) 15.4.
2 Section 15 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 1 2 3 4 5 6 7 8 9 SDA (Master output) 1 A SCL (Slave output) SDA (Slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 TDRE TEND TRS Data 1 ICDRT ICDRS Data 2 Data 1 Data 3 Data 2 ICDRR User processing [2] Write data to ICDRT (data 1) [2] Write data to ICDRT (data 2) [2] Write data to ICDRT (data 3) Figure 15.
2 Section 15 I C Bus Interface 2 (IIC2) Slave receive mode Slave transmit mode SCL (Master output) 9 SDA (Master output) A 1 2 3 4 5 6 7 8 9 A SCL (Slave output) SDA (Slave output) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TDRE TEND TRS ICDRT ICDRS Data n ICDRR User processing [3] Clear TEND [4] Read ICDRR (dummy read) after clearing TRS [5] Clear TDRE Figure 15.10 Slave Transmit Mode Operation Timing (2) 15.4.
2 Section 15 I C Bus Interface 2 (IIC2) 3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be returned to the master device, is reflected to the next transmit frame. 4. The last byte data is read by reading ICDRR.
2 Section 15 I C Bus Interface 2 (IIC2) 15.4.6 Clocked Synchronous Serial Format This module can be operated with the clocked synchronous serial format, by setting the FS bit in SAR to 1. When the MST bit in ICCR1 is 1, the transfer clock output from SCL is selected. When MST is 0, the external clock input is selected. Data Transfer Format Figure 15.13 shows the clocked synchronous serial transfer format.
2 Section 15 I C Bus Interface 2 (IIC2) SCL 1 2 7 8 1 7 8 1 SDA (Output) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 Bit 0 TRS TDRE Data 1 ICDRT Data 1 ICDRS User processing Data 2 [3] Write data [3] Write data to ICDRT to ICDRT [2] Set TRS Data 3 Data 2 Data 3 [3] Write data to ICDRT [3] Write data to ICDRT Figure 15.14 Transmit Mode Operation Timing Receive Operation In receive mode, data is latched at the rise of the transfer clock.
2 Section 15 I C Bus Interface 2 (IIC2) SCL 1 2 7 8 1 7 8 SDA (Input) Bit 0 Bit 1 Bit 6 Bit 7 Bit 0 Bit 6 Bit 7 1 2 Bit 0 MST TRS RDRF Data 2 Data 1 ICDRS Data 3 Data 1 ICDRR User processing [2] Set MST (when outputting the clock) [3] Read ICDRR Data 2 [3] Read ICDRR Figure 15.15 Receive Mode Operation Timing 15.4.7 Noise Canceler The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched internally. Figure 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.4.8 Example of Use Flowcharts in respective modes that use the I2C bus interface are shown in figures 15.17 to 15.20. Start Initialize Read BBSY in ICCR2 [1] Test the status of the SCL and SDA lines. [2] Set master transmit mode. [3] Issue the start condition. [1] No BBSY=0 ? Yes Set MST and TRS in ICCR1 to 1. [2] [4] Set the first byte (slave address + R/W) of transmit data. Write 1 to BBSY and 0 to SCP.
2 Section 15 I C Bus Interface 2 (IIC2) Mater receive mode [1] Clear TEND, select master receive mode, and then clear TDRE.* [2] Set acknowledge to the transmit device.* [3] Dummy-read ICDDR.* [4] Wait for 1 byte to be received [5] Check whether it is the (last receive - 1). [6] Read the receive data last. [7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1). [8] Read the (final byte - 1) of receive data. [9] Wait for the last byte to be receive.
2 Section 15 I C Bus Interface 2 (IIC2) [1] Clear the AAS flag. Slave transmit mode Clear AAS in ICSR [1] Write transmit data in ICDRT [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. Read TDRE in ICSR [5] Wait for the last byte to be transmitted. [3] No TDRE=1 ? Yes Yes [6] Clear the TEND flag . [7] Set slave receive mode. Last byte? No [2] Set transmit data for ICDRT (except for the last data). [8] Dummy-read ICDRR to release the SCL line.
2 Section 15 I C Bus Interface 2 (IIC2) Slave receive mode [1] Clear the AAS flag. Clear AAS in ICSR [1] Clear ACKBT in ICIER to 0 [2] Dummy-read ICDRR [3] [2] Set acknowledge to the transmit device. [3] Dummy-read ICDRR. [5] Check whether it is the (last receive - 1). Read RDRF in ICSR No [4] RDRF=1 ? [6] Read the receive data. [7] Set acknowledge of the last byte. Yes Last receive - 1? [4] Wait for 1 byte to be received.
2 Section 15 I C Bus Interface 2 (IIC2) 15.5 Interrupt Request There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK receive, STOP recognition, and arbitration lost/overrun. Table 15.3 shows the contents of each interrupt request. Table 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.6 Bit Synchronous Circuit In master mode,this module has a possibility that high level period may be short in the two states described below. • When SCL is driven to low by the slave device • When the rising speed of SCL is lowered by the load of the SCL line (load capacitance or pullup resistance) Therefore, it monitors SCL and communicates by bit with synchronization. Figure 15.21 shows the timing of the bit synchronous circuit and table 15.
2 Section 15 I C Bus Interface 2 (IIC2) 15.7 Usage Notes 15.7.1 Issue (Retransmission) of Start/Stop Conditions In master mode, when the start/stop conditions are issued (retransmitted) at the specific timing under the following condition 1 or 2, such conditions may not be output successfully. To avoid this, issue (retransmit) the start/stop conditions after the fall of the ninth clock is confirmed. Check the SCLO bit in the I2C control register 2 (IICR2) to confirm the fall of the ninth clock. 1.
Section 16 A/D Converter Section 16 A/D Converter This LSI includes a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. The block diagram of the A/D converter is shown in figure 16.1. 16.1 • • • • • • • • Features 10-bit resolution Eight input channels Conversion time: at least 3.
Section 16 A/D Converter Module data bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Analog multiplexer 10-bit D/A Bus interface Successive approximations register AVCC Internal data bus A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + φ/4 Control circuit Comparator Sample-andhold circuit ADTRG [Legend] ADCR: ADCSR: ADDRA: ADDRB: ADDRC: ADDRD: A/D control register A/D control/status register A/D data register A A/D data register B A/D data register C A/D data register D Figure 16.
Section 16 A/D Converter 16.2 Input/Output Pins Table 16.1 summarizes the input pins used by the A/D converter. The 8 analog input pins are divided into two groups; analog input pins 0 to 3 (AN0 to AN3) comprising group 0, analog input pins 4 to 7 (AN4 to AN7) comprising group 1. The AVcc pin is the power supply pin for the analog block in the A/D converter. Table 16.
Section 16 A/D Converter 16.3 Register Descriptions The A/D converter has the following registers. • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers; ADDRA to ADDRD, used to store the results of A/D conversion.
Section 16 A/D Converter 16.3.2 A/D Control/Status Register (ADCSR) ADCSR consists of the control bits and conversion end status bits of the A/D converter.
Section 16 A/D Converter Bit Bit Name Initial Value R/W Description 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W Select analog input channels. 0 CH0 0 R/W When SCAN = 0 When SCAN = 1 000: AN0 000: AN0 001: AN1 001: AN0 and AN1 010: AN2 010: AN0 to AN2 011: AN3 011: AN0 to AN3 100: AN4 100: AN4 101: AN5 101: AN4 and AN5 110: AN6 110: AN4 to AN6 111: AN7 111: AN4 to AN7 16.3.
Section 16 A/D Converter 16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes; single mode and scan mode. When changing the operating mode or analog input channel, in order to prevent incorrect operation, first clear the bit ADST in ADCSR to 0. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 16.4.
Section 16 A/D Converter 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) has passed after the ADST bit is set to 1, then starts conversion. Figure 16.2 shows the A/D conversion timing. Table 16.3 shows the A/D conversion time. As indicated in figure 16.2, the A/D conversion time includes tD and the input sampling time.
Section 16 A/D Converter Table 16.3 A/D Conversion Time (Single Mode) CKS = 0 Item Symbol Min CKS = 1 Typ Max Min Typ Max A/D conversion start delay time tD 6 — 9 4 — 5 Input sampling time tSPL — 31 — — 15 — A/D conversion time tCONV 131 — 134 69 — 70 Note: All values represent the number of states. 16.4.4 External Trigger Input Timing A/D conversion can also be started by an external trigger input.
Section 16 A/D Converter 16.5 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 16.4). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 16.5).
Section 16 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 6 8 7 FS 8 Analog input voltage Figure 16.4 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 16.5 A/D Conversion Accuracy Definitions (2) Rev.5.00 Nov.
Section 16 A/D Converter 16.6 Usage Notes 16.6.1 Permissible Signal Source Impedance This LSI's analog input is designed such that conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 17 EEPROM Section 17 EEPROM The H8/3694N has an on-chip 512-byte EEPROM. The block diagram of the EEPROM is shown in figure 17.1. 17.1 Features • Two writing methods: 1-byte write Page write: Page size 8 bytes • Three reading methods: Current address read Random address read Sequential read • Acknowledge polling possible • Write cycle time: 10 ms (power supply voltage Vcc = 2.
Section 17 EEPROM EEPROM Data bus Y decoder H'FF10 SDA SCL I2C bus interface control circuit Y-select/ Sense amp. Memory array User area (512 bytes) X decoder Key control circuit Address bus EEPROM Key register (EKR) Slave address register ESAR Power-on reset Booster circuit EEPROM module [Legend] ESAR: Register for referring the slave address (specifies the slave address of the memory array) Figure 17.1 Block Diagram of EEPROM Rev.5.00 Nov.
Section 17 EEPROM 17.2 Input/Output Pins Pins used in the EEPROM are listed in table 17.1. Table 17.1 Pin Configuration Pin name Symbol Input/Output Function Serial clock pin SCL Input The SCL pin is used to control serial input/output data timing. The data is input at the rising edge of the clock and output at the falling edge of the clock. The SCL pin needs to be pulled up by resistor as that 2 pin is open-drain driven structure of the I C pin.
Section 17 EEPROM 17.4 Operation 17.4.1 EEPROM Interface The HD64N3694G has a multi-chip structure with two internal chips of the HD64F3694G (FZTAT™ version) and 512-byte EEPROM. The HD6483694G has a multi-chip structure with two internal chips of the HD6433694G (mask-ROM version) and 512-byte EEPROM. The EEPROM interface is the I2C bus interface. This I2C bus is open to the outside, so the communication with the external devices connected to the I2C bus can be made. 17.4.
Section 17 EEPROM 17.4.4 Stop Condition A low-to-high transition of the SDA input with the SCL input high is needed to generate the stop condition for stopping read, write operation. The standby operation starts after a read sequence by a stop condition. In the case of write operation, a stop condition terminates the write data inputs and place the device in an internallytimed write cycle to the memories.
Section 17 EEPROM The initial value of the slave address code written in the EEPROM is H'00. It can be written in the range of H'00 to H'07. Be sure to write the data by the byte write method. The next one bit of the slave address is the R/W code. 0 is for a write and 1 is for a read. The EEPROM turns to a standby state if the device code is not "1010" or slave address code doesn’t coincide. Table 17.
Section 17 EEPROM 17.4.7 Write Operations There are two types write operations; byte write operation and page write operation. To initiate the write operation, input 0 to R/W code following the slave address. 1. Byte Write A write operation requires an 8-bit data of a 7-bit slave address with R/W code = "0". Then the EEPROM sends acknowledgement "0" at the ninth bit. This enters the write mode. Then, two bytes of the memory address are received from the MSB side in the order of upper and lower.
Section 17 EEPROM Addresses in the page are incremented at each receipt of the write data and the write data can be input up to 8 bytes. If the LSB 3 bits (A2 to A0) in the EEPROM address reach the last address of the page, the address will roll over to the first address of the same page. When the address is rolled over, write data is received twice or more to the same address, however, the last received data is valid.
Section 17 EEPROM 17.4.9 Read Operation There are three read operations; current address read, random address read, and sequential read. Read operations are initiated in the same way as write operations with the exception of R/W = 1. 1. Current Address Read The internal address counter maintains the (n+1) address that is made by the last address (n) accessed during the last read or write operation, with incremented by one.
Section 17 EEPROM 2. Random Address Read This is a read operation with defined read address. A random address read requires a dummy write to set read address. The EEPROM receives a start condition, slave address + R/W code (R/W = 0), memory address (upper) and memory address (lower) sequentially. The EEPROM outputs acknowledgement "0" after receiving memory address (lower) then enters a current address read with receiving a start condition again.
Section 17 EEPROM SCL 1 2 3 4 5 6 7 8 9 SDA Slave address R/W ACK 1 8 9 D7 D0 Read Data ACK · · · · 1 8 D7 D0 Read Data 9 ACK Start condition Stop conditon [Legend] R/W: R/W code (0 is for a write and 1 is for a read) ACK: acknowledge Figure 17.7 Sequential Read Operation (when current address read is used) Rev.5.00 Nov.
Section 17 EEPROM 17.5 Usage Notes 17.5.1 Data Protection at VCC On/Off When VCC is turned on or off, the data might be destroyed by malfunction. Be careful of the notices described below to prevent the data to be destroyed. 1. SCL and SDA should be fixed to VCC or VSS during VCC on/off. 2. VCC should be turned off after the EEPROM is placed in a standby state. 3. When VCC is turned on from the intermediate level, malfunction is caused, so VCC should be turned on from the ground level (VSS). 4.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) This LSI can include a power-on reset circuit and low-voltage detection circuit as optional circuits. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) φ CK R OVF PSS R RES Internal reset signal Q Noise canceler S CRES Power-on reset circuit Noise canceler Vcc Ladder resistor Internal data bus LVDCR Vreset + − Vint LVDRES + − LVDINT Interrupt control circuit LVDSR Reference voltage generator Interrupt request Low-voltage detection circuit [Legend] PSS: LVDCR: LVDSR: LVDRES: LVDINT: Vreset: Vint: Prescaler S Low-voltage-detection control register Low-voltage-de
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Table 18.1 shows the relationship between the LVDCR settings and select functions. LVDCR should be set according to table 18.1. Bit Bit Name Initial Value R/W Description 7 LVDE 0* R/W LVD Enable 0: The low-voltage detection circuit is not used (In standby mode) 1: The low-voltage detection circuit is used 6 to 4 All 1 Reserved These bits are always read as 1, and cannot be modified.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Table 18.1 LVDCR Settings and Select Functions LVDCR Settings Select Functions LVDE LVDSEL LVDRE LVDDE LVDUE Power-On Reset LVDR Low-VoltageDetection Falling Interrupt 0 * * * * O 1 1 1 0 0 O O 1 0 0 1 0 O O 1 0 0 1 1 O O O 1 0 1 1 1 O O O O Legend: 18.2.2 Low-VoltageDetection Rising Interrupt *: means invalid.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) 18.3 Operation 18.3.1 Power-On Reset Circuit Figure 18.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 150 kΩ). Since the state of the RES pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) tPWON Vcc Vpor Vss RES Vss PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 18.2 Operational Timing of Power-On Reset Circuit 18.3.2 Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detect) Circuit: Figure 18.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) VCC Vreset VLVDRmin VSS LVDRES PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 18.3 Operational Timing of LVDR Circuit LVDI (Interrupt by Low Voltage Detect) Circuit: Figure 18.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated. If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function is performed. Vint (U) Vint (D) Vcc Vreset1 VSS LVDINT LVDDE LVDDF LVDUE LVDUF IRQ0 interrupt generated IRQ0 interrupt generated Figure 18.4 Operational Timing of LVDI Circuit Rev.5.00 Nov.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Procedures for Clearing Settings when Using LVDR and LVDI: To operate or release the low-voltage detection circuit normally, follow the procedure described below. Figure 18.5 shows the timing for the operation and release of the low-voltage detection circuit. 1. To operate the low-voltage detection circuit, set the LVDE bit in LVDCR to 1. 2.
Section 18 Power-On Reset and Low-Voltage Detection Circuits (Optional) Rev.5.00 Nov.
Section 19 Power Supply Circuit Section 19 Power Supply Circuit This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.0 V or above can be held down to virtually the same low level as when used at approximately 3.0 V.
Section 19 Power Supply Circuit 19.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the VCL pin and VCC pin, as shown in figure 19.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 3.0 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.6 V) is input.
Section 20 List of Registers Section 20 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. Register addresses (address order) • Registers are listed from the lower allocation addresses. • The symbol in the register-name column represents a reserved address or range of reserved addresses. Do not attempt to access reserved addresses.
Section 20 List of Registers 20.1 Register Addresses (Address Order) The data-bus width column indicates the number of bits. The access-state column shows the number of states of the selected basic clock that is required for access to the register. Note: Access to undefined or reserved addresses should not take place. Correct operation of the access itself or later operations is not guaranteed when such a register is accessed.
Section 20 List of Registers Register Name Abbreviation Bit No General register B GRB 16 General register C GRC 16 16 Address Module Name Data Bus Width Access State H'FF8A Timer W 16*2 2 Timer W 2 2 H'FF8C 16* 2 General register D GRD H'FF8E Timer W 16* 2 Flash memory control register 1 FLMCR1 8 H'FF90 ROM 8 2 Flash memory control register 2 FLMCR2 8 H'FF91 ROM 8 2 Flash memory power control register FLPWCR 8 H'FF92 ROM 8 2 Erase block register 1 EBR1 8 H'F
Section 20 List of Registers Data Bus Width Access State A/D converter 8 3 H'FFB4 A/D converter 8 3 16 H'FFB6 A/D converter 8 3 ADCSR 8 H'FFB8 A/D converter 8 3 A/D control register ADCR 8 H'FFB9 A/D converter 8 3 — — — H'FFBA to — H'FFBF — — Timer control/status register WD TCSRW D 8 H'FFC0 WDT*3 8 2 Timer counter WD TCWD 8 H'FFC1 WDT*3 8 2 3 Register Name Abbreviation Bit No Address A/D data register B ADDRB 16 H'FFB2 A/D data register C ADDRC 16
Section 20 List of Registers Address Module Name Data Bus Width Access State 8 H'FFD0 I/O port 8 2 PUCR5 8 H'FFD1 I/O port 8 2 — — — H'FFD2, H'FFD3 I/O port — — Port data register 1 PDR1 8 H'FFD4 I/O port 8 2 Port data register 2 PDR2 8 H'FFD5 I/O port 8 2 — — 8 H'FFD6, H'FFD7 I/O port — — Register Name Abbreviation Bit No Port pull-up control register 1 PUCR1 Port pull-up control register 5 Port data register 5 PDR5 8 H'FFD8 I/O port 8 2 — — — H'F
Section 20 List of Registers Bit No Address Module Name Data Bus Access Width State Register Name Abbreviation System control register 1 SYSCR1 8 H'FFF0 Power-down 8 2 System control register 2 SYSCR2 8 H'FFF1 Power-down 8 2 Interrupt edge select register 1 IEGR1 8 H'FFF2 Interrupts 8 2 Interrupt edge select register 2 IEGR2 8 H'FFF3 Interrupts 8 2 Interrupt enable register 1 IENR1 8 H'FFF4 Interrupts 8 2 — — — H'FFF5 I/O port — — Interrupt flag register 1 IRR
Section 20 List of Registers 20.2 Register Bits The addresses and bit names of the registers in the on-chip peripheral modules are listed below. The 16-bit register is indicated in two rows, 8 bits for each row.
Section 20 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name FLMCR1 — SWE ESU PSU EV PV E P ROM FLMCR2 FLER — — — — — — — FLPWCR PDWND — — — — — — — EBR1 — — — EB4 EB3 EB2 EB1 EB0 FENR FLSHE — — — — — — — TCRV0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCSRV CMFB CMFA OVF — OS3 OS2 OS1 OS0 TCORA TCORA7 TCORA6 TCORA5 TCORA4 TCORA3 TCORA2 TCORA1 TCORA0 TCORB TCORB7 TCORB6 TCORB5 TCORB4 TCORB
Section 20 List of Registers Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name TMWD — — — — CKS3 CKS2 CKS1 CKS0 WDT*2 — — — — — — — — — — ABRKCR RTINTE CSEL1 CSEL0 ACMP2 ACMP1 ACMP0 DCMP1 DCMP0 Address break ABRKSR ABIF ABIE — — — — — — BARH BARH7 BARH6 BARH5 BARH4 BARH3 BARH2 BARH1 BARH0 BARL BARL7 BARL6 BARL5 BARL4 BARL3 BARL2 BARL1 BARL0 BDRH BDRH7 BDRH6 BDRH5 BDRH4 BDRH3 BDRH2 BDRH1 BDRH0 BDRL BDRL7 BDR
Section 20 List of Registers • EEPROM Register Name Bit 7 Bit 6 Bit 5 EKR Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name EEPROM Notes: 1. LVDC: Low-voltage detection circuits (optional) 2. WDT: Watchdog timer TM 3. These bits are reserved in the EEPROM stacked F-ZTAT and mask-ROM versions. Rev.5.00 Nov.
Section 20 List of Registers 20.
Section 20 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module TCNTV Initialized — — Initialized Initialized Initialized Timer V TCRV1 Initialized — — Initialized Initialized Initialized TMA Initialized — — — — — TCA Initialized — — — — — SMR Initialized — — Initialized Initialized Initialized BRR Initialized — — Initialized Initialized Initialized SCR3 Initialized — — Initialized Initialized Initialized TDR Initiali
Section 20 List of Registers Register Name Reset Active Sleep Subactive Subsleep Standby Module PMR1 Initialized — — — — — I/O port PMR5 Initialized — — — — — PCR1 Initialized — — — — — PCR2 Initialized — — — — — PCR5 Initialized — — — — — PCR7 Initialized — — — — — PCR8 Initialized — — — — — SYSCR1 Initialized — — — — — Power-down SYSCR2 Initialized — — — — — Power-down IEGR1 Initialized — — — — — Interrupts IEGR2 Initialize
Section 20 List of Registers Rev.5.00 Nov.
Section 21 Electrical Characteristics Section 21 Electrical Characteristics 21.1 Absolute Maximum Ratings Table 21.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +7.0 V * Analog power supply voltage AVCC –0.3 to +7.0 V Input voltage VIN –0.3 to VCC +0.3 V Port B –0.3 to AVCC +0.3 V X1 –0.3 to 4.
Section 21 Electrical Characteristics Power Supply Voltage and Operating Frequency Range φ (MHz) φSUB (kHz) 20.0 16.384 10.0 8.192 4.096 1.0 3.0 4.0 5.5 VCC (V) 3.0 • AVCC = 3.3 to 5.5 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 0 ) 4.0 5.5 • AVCC = 3.3 to 5.5 V • Subactive mode • Subsleep mode φ (kHz) 2500 1250 78.125 3.0 4.0 5.5 VCC (V) • AVCC = 3.3 to 5.
Section 21 Electrical Characteristics Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used φosc (MHz) 20.0 16.0 2.0 Vcc(V) 3.0 4.5 5.5 Operation guarantee range Operation guarantee range except A/D conversion accuracy Rev.5.00 Nov.
Section 21 Electrical Characteristics 21.2.2 DC Characteristics Table 21.2 DC Characteristics (1) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins Input high VIH voltage Test Condition Min Typ Max Unit VCC × 0.8 — VCC + 0.3 V VCC × 0.9 — VCC + 0.3 VCC × 0.7 — VCC + 0.3 VCC × 0.8 — VCC + 0.3 VCC × 0.7 — AVCC + 0.3 V VCC × 0.8 — AVCC + 0.3 VCC – 0.5 — VCC + 0.3 VCC – 0.3 — VCC + 0.3 VCC = 4.0 to 5.
Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Output high voltage VOH P10 to P12, P14 to P17, P20 to P22, P50 to P55, P74 to P76, P80 to P87 VCC = 4.0 to 5.5 V VCC – 1.0 — — V VCC – 0.5 — — P56, P57 VCC = 4.0 to 5.5 V VCC – 2.5 — — — — Notes –IOH = 1.5 mA –IOH = 0.1 mA V –IOH = 0.1 mA VCC = 3.0 to 4.0 V VCC – 2.0 –IOH = 0.1 mA Output low voltage VOL VCC = 4.0 to 5.5 VIOL = 1.6 mA — — 0.6 IOL = 0.4 mA — — 0.
Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes Pull-up MOS current –Ip P10 to P12, P14 to P17, P50 to P55 VCC = 5.0 V, VIN = 0.0 V 50.0 — 300.0 µA VCC = 3.0 V, VIN = 0.0 V — 60.0 — Input capacitance Cin All input pins except power supply pins f = 1 MHz, VIN = 0.0 V, Ta = 25°C — — 15.0 pF — — 25.0 pF HD64N3694G Active mode 1 VCC = 5.0 V, fOSC = 20 MHz — 20.0 30.0 mA * Active mode 1 VCC = 3.
Section 21 Electrical Characteristics Values Item Applicable Pins Test Condition Min Typ Max Unit Notes Subsleep ISUBSP mode current consumption VCC VCC = 3.0 V 32-kHz crystal resonator (φSUB = φW/2) — 30.0 50.0 µA * ISTBY Standby mode current consumption VCC 32-kHz crystal resonator not used — — 5.0 µA * RAM data VRAM retaining voltage VCC 2.
Section 21 Electrical Characteristics Table 21.2 DC Characteristics (2) VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes EEPROM current consumption IEEW VCC VCC = 5.0 V, tSCL = 2.5 µs (when writing) — — 2.0 mA * IEER VCC VCC = 5.0 V, tSCL = 2.5 µs (when reading) — — 0.3 mA IEESTBY VCC VCC = 5.0 V, tSCL = 2.5 µs (at standby) — — 3.
Section 21 Electrical Characteristics Table 21.2 DC Characteristics (3) VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Applicable Item Symbol Pins Test Condition Allowable output low current (per pin) IOL Output pins except port 8, SCL, and SDA Port 8 Allowable output low current (total) ∑IOL Allowable output high –IOH current (total) Typ Max Unit VCC = 4.0 to 5.5 V — — 2.0 mA — — 20.0 Port 8 — — 10.0 SCL and SDA — — 6.
Section 21 Electrical Characteristics 21.2.3 AC Characteristics Table 21.3 AC Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins System clock oscillation fOSC OSC1, OSC2 VCC = 4.0 to 5.5 V Test Condition frequency System clock (φ) Min Typ Max Unit Reference Figure 2.0 — 20.0 MHz * tOSC * 2.0 tcyc 1 cycle time 10.0 — 64 12.8 — — Subclock oscillation fW frequency X1, X2 — 32.
Section 21 Electrical Characteristics Item Symbol Input pin high width tIH Input pin low width tIL Applicable Pins Values Test Condition Min Typ Max Unit NMI, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD 2 — — tcyc tsubcyc NMI, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD 2 — — tcyc tsubcyc Reference Figure Figure 21.3 Notes: 1. When an external clock is input, the minimum system clock oscillation frequency is 1.0 MHz. 2.
Section 21 Electrical Characteristics Table 21.4 I2C Bus Interface Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Test Condition Values Max Unit Reference Figure 12tcyc + 600 — — ns Figure 21.
Section 21 Electrical Characteristics Table 21.5 Serial Communication Interface (SCI) Timing VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Section 21 Electrical Characteristics 21.2.4 A/D Converter Characteristics Table 21.6 A/D Converter Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol Applicable Pins Test Condition Values Min Typ Max Unit Reference Figure V * Analog power supply AVCC voltage AVCC 3.3 VCC 5.5 Analog input voltage AVIN AN0 to AN7 VSS – 0.3 — AVCC + 0.3 V Analog power supply AIOPE current AVCC — 2.0 mA AVCC = 5.
Section 21 Electrical Characteristics Item Symbol Applicable Pins Conversion time (single mode) Test Condition Values Min AVCC = 4.0 to 134 5.5 V Typ Max Unit — — tcyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Reference Figure Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2.
Section 21 Electrical Characteristics 21.2.6 Flash Memory Characteristics Table 21.8 Flash Memory Characteristics VCC = 3.0 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated.
Section 21 Electrical Characteristics Item Erasing Symbol Test Condition Values Min Typ Max Unit Wait time after SWE 1 bit setting* x 1 — — µs Wait time after ESU 1 bit setting* y 100 — — µs Wait time after E bit 1 6 setting* * z 10 — 100 ms Wait time after E bit clear* α 10 — — µs Wait time after ESU 1 bit clear* β 10 — — µs Wait time after EV 1 bit setting* γ 20 — — µs Wait time after 1 dummy write* ε 2 — — µs Wait time after EV bit clear* η 4 — — µs
Section 21 Electrical Characteristics 21.2.7 EEPROM Characteristics Table 21.9 EEPROM Characteristics VCC = 3.0 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise specified.
Section 21 Electrical Characteristics 21.2.8 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 21.10 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Test Condition Min Typ Max Unit Power-supply falling detection voltage Vint (D) LVDSEL = 0 3.3 3.7 — V Power-supply rising detection voltage Vint (U) LVDSEL = 0 — 4.0 4.5 V Reset detection voltage 1*1 Vreset1 LVDSEL = 0 — 2.
Section 21 Electrical Characteristics 21.2.9 Power-On Reset Circuit Characteristics (Optional) Table 21.11 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Pull-up resistance of RES pin Power-on reset start voltage* Note: * Test Condition Min Typ Max Unit RRES 100 150 — kΩ Vpor — — 100 mV The power-supply voltage (Vcc) must fall below Vpor = 100 mV and then rise after charge of the RES pin is removed completely.
Section 21 Electrical Characteristics Power Supply Voltage and Operating Frequency Range φ (MHz) φSUB (kHz) 20.0 16.384 10.0 8.192 4.096 1.0 2.7 φ (kHz) 4.0 5.5 VCC (V) • AVCC = 3.0 to 5.5 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 0) 2.7 4.0 5.5 VCC (V) • AVCC = 3.0 to 5.5 V • Subactive mode • Subsleep mode 2500 1250 78.125 2.7 4.0 5.5 VCC (V) • AVCC = 3.0 to 5.5 V • Active mode • Sleep mode (When MA2 in SYSCR2 = 1) Rev.5.00 Nov.
Section 21 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Accuracy Guarantee Range φ (MHz) 20.0 10.0 2.0 3.0 4.0 5.5 AVCC (V) • VCC = 2.7 to 5.5 V • Active mode • Sleep mode Range of Power Supply Voltage and Oscillation Frequency when Low-Voltage Detection Circuit is Used φosc (MHz) 20.0 16.0 2.0 Vcc(V) 3.0 4.5 5.5 Operation guarantee range Operation guarantee range except A/D conversion accuracy Rev.5.00 Nov.
Section 21 Electrical Characteristics 21.3.2 DC Characteristics Table 21.12 DC Characteristics (1) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Input high VIH voltage Applicable Pins RXD, SCL, SDA, P10 to P12, P14 to P17, P20 to P22, P50 to P57, P74 to P76, P80 to P87 VCC = 4.0 to 5.5 V PB0 to PB7 VCC = 4.0 to 5.5 V OSC1 Input low VIL voltage Test Condition RES, NMI, VCC = 4.0 to 5.
Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Output high voltage VOH P10 to P12, P14 to P17, P20 to P22, VCC = 4.0 to 5.5 V VCC – 1.0 Min Typ Max Unit — — V P50 to P55, P74 to P76, P80 to P87 –IOH = 0.1 mA VCC – 0.5 — — P56, P57 VCC = 4.0 to 5.5 V VCC – 2.5 — — — — — 0.6 –IOH = 1.5 mA V –IOH = 0.1 mA VCC =2.7 to 4.0 V VCC – 2.0 –IOH = 0.1 mA Output low voltage VOL P10 to P12, P14 to P17, P20 to P22, VCC = 4.0 to 5.
Section 21 Electrical Characteristics Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Pull-up MOS current –Ip P10 to P12, P14 to P17, P50 to P55 VCC = 5.0 V, VIN = 0.0 V 50.0 — 300.0 µA VCC = 3.0 V, VIN = 0.0 V — 60.0 — Input capacitance Cin All input pins except power supply pins f = 1 MHz, VIN = 0.0 V, Ta = 25°C — — 15.0 pF — — 25.0 pF HD6483694G Active mode 1 VCC = 5.0 V, fOSC = 20 MHz — 20.0 30.0 mA * Active mode 1 VCC = 3.
Section 21 Electrical Characteristics Values Item Applicable Pins Test Condition Min Typ Max Unit Notes Subsleep ISUBSP mode current consumption VCC VCC = 3.0 V 32-kHz crystal resonator (φSUB = φW/2) — 30.0 50.0 µA * ISTBY Standby mode current consumption VCC 32-kHz crystal — resonator not used — 5.0 µA * RAM data VRAM retaining voltage VCC — — V Note: Symbol * 2.
Section 21 Electrical Characteristics Table 21.12 DC Characteristics (2) VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated. Values Item Symbol Applicable Pins Test Condition Min Typ Max Unit Notes EEPROM current consumption IEEW VCC VCC = 5.0 V, tSCL = 2.5 µs (when writing) — — 2.0 mA * IEER VCC VCC = 5.0 V, tSCL = 2.5 µs (when reading) — — 0.3 mA IEESTBY VCC VCC = 5.0 V, tSCL = 2.5 µs (at standby) — — 3.
Section 21 Electrical Characteristics Table 21.12 DC Characteristics (3) VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Applicable Item Symbol Pins Allowable output low current (per pin) IOL Allowable output low current (total) ∑IOL Typ Max Unit Output pins except port VCC = 4.0 to 5.5 V — 8, SCL, and SDA — 2.0 mA Port 8 — — 20.0 Port 8 — — 10.0 SCL, and SDA — — 6.0 Output pins except port 8, SCL, and SDA — — 0.
Section 21 Electrical Characteristics 21.3.3 AC Characteristics Table 21.13 AC Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol System clock oscillation fOSC Applicable Pins Test Condition OSC1, OSC2 VCC = 4.0 to 5.5 V frequency System clock (φ) cycle time Values Min Typ Max Unit Reference Figure 2.0 — 20.0 MHz * tOSC * 2.0 tcyc 1 10.0 — 64 12.8 — — Subclock oscillation fW frequency X1, X2 — 32.
Section 21 Electrical Characteristics Item Symbol Input pin high width tIH Input pin low width tIL Applicable Pins Values Min Typ Max Unit NMI, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD 2 — — tcyc tsubcyc NMI, IRQ0 to IRQ3, WKP0 to WKP5, TMCIV, TMRIV, TRGV, ADTRG, FTCI, FTIOA to FTIOD 2 — — tcyc tsubcyc Notes: 1 Test Condition Reference Figure Figure 21.3 When an external clock is input, the minimum system clock oscillation frequency is 1.0 MHz. 2.
Section 21 Electrical Characteristics Table 21.14 I2C Bus Interface Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified. Test Condition Min Values Max Unit Reference Figure 12tcyc + 600 — — ns Figure 21.
Section 21 Electrical Characteristics Table 21.15 Serial Communication Interface (SCI) Timing VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise specified. Item Input clock cycle Asynchronous Symbol Min Typ Max Unit Reference Figure tScyc SCK3 4 — — Figure 21.5 6 — — 0.4 — 0.6 tScyc — — 1 tcyc — — 1 50.0 — — 100.0 — — 50.0 — — 100.
Section 21 Electrical Characteristics 21.3.4 A/D Converter Characteristics Table 21.16 A/D Converter Characteristics VCC = 2.7 to 5.5 V, VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Item Symbol Applicable Pins Test Condition Values Min Typ Max Unit Reference Figure VCC 5.5 V * Analog power supply AVCC voltage AVCC 3.0 Analog input voltage AVIN AN0 to AN7 VSS – 0.3 — Analog power supply AIOPE current AVCC AVCC = 5.0 V — 1 AVCC + 0.3 V — 2.
Section 21 Electrical Characteristics Item Symbol Values Applicable Test Pins Condition Conversion time (single mode) Min AVCC = 4.0 to 5.5 V 134 Typ Max Unit — — tcyc Nonlinearity error — — ±3.5 LSB Offset error — — ±3.5 LSB Full-scale error — — ±3.5 LSB Quantization error — — ±0.5 LSB Absolute accuracy — — ±4.0 LSB Reference Figure Notes: 1 Set AVCC = VCC when the A/D converter is not used. 2.
Section 21 Electrical Characteristics 21.3.6 EEPROM Characteristics Table 21.18 EEPROM Characteristics VCC = 2.7 V to 5.5 V, VSS = 0.0 V, Ta = –20°C to +75°C, unless otherwise indicated.
Section 21 Electrical Characteristics 21.3.7 Power-Supply-Voltage Detection Circuit Characteristics (Optional) Table 21.19 Power-Supply-Voltage Detection Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Values Item Symbol Test Condition Power-supply falling detection voltage Vint (D) LVDSEL = 0 3.3 3.7 — V Power-supply rising detection voltage Vint (U) LVDSEL = 0 — 4.0 4.5 V Reset detection voltage 1*1 Vreset1 LVDSEL = 0 — 2.3 2.
Section 21 Electrical Characteristics 21.3.8 Power-On Reset Circuit Characteristics (Optional) Table 21.20 Power-On Reset Circuit Characteristics VSS = 0.0 V, Ta = –20 to +75°C, unless otherwise indicated. Typ Max Unit RRES 100 150 — kΩ Vpor — — 100 mV Symbol Pull-up resistance of RES pin Power-on reset start voltage* 21.
Section 21 Electrical Characteristics VCC × 0.7 VCC OSC1 tREL RES VIL VIL tREL Figure 21.2 RES Low Width Timing NMI IRQ0 to IRQ3 WKP0 to WKP5 ADTRG FTCI FTIOA to FTIOD TMCIV, TMRIV TRGV VIH VIL t IL t IH Figure 21.3 Input Timing VIH SDA VIL tBUF tSTAH tSCLH tSTAS tSP tSTOS SCL P* S* tSf Sr* tSCLL P* tSDAS tSCL tSDAH Note: * S, P, and Sr represent the following: S: Start condition P: Stop condition Sr: Retransmission start condition Figure 21.
Section 21 Electrical Characteristics t SCKW SCK3 t Scyc Figure 21.5 SCK3 Input Clock Timing t Scyc SCK3 VIH or VOH * VIL or VOL * t TXD * TXD (transmit data) VOH VOL * t RXS t RXH RXD (receive data) Note: * Output timing reference levels Output high: V OH= 2.0 V Output low: V OL= 0.8 V Load conditions are shown in figure 21.8. Figure 21.6 SCI Input/Output Timing in Clocked Synchronous Mode Rev.5.00 Nov.
Section 21 Electrical Characteristics 1/fSCL tSf tSCLH tSP tSCLL SCL tSTAS tSDAH tSTAH tSTOS tSDAS tSr SDA (in) tBUF tAA tDH SDA (out) Figure 21.7 EEPROM Bus Timing 21.5 Output Load Condition VCC 2.4 kΩ LSI output pin 30 pF 12 k Ω Figure 21.8 Output Load Circuit Rev.5.00 Nov.
Appendix Appendix A Instruction Set A.
Appendix Symbol Description ↔ Condition Code Notation (cont) Changed according to execution result * Undetermined (no guaranteed value) 0 Cleared to 0 1 Set to 1 — Not affected by execution of the instruction ∆ Varies depending on conditions, described in notes Rev.5.00 Nov.
Appendix Table A.1 Instruction Set 1. Data Transfer Instructions Condition Code — — MOV.B @(d:16, ERs), Rd B 4 @(d:16, ERs) → Rd8 — — MOV.B @(d:24, ERs), Rd B 8 @(d:24, ERs) → Rd8 — — MOV.B @ERs+, Rd B @ERs → Rd8 ERs32+1 → ERs32 — — MOV.B @aa:8, Rd B 2 @aa:8 → Rd8 — — MOV.B @aa:16, Rd B 4 @aa:16 → Rd8 — — MOV.B @aa:24, Rd B 6 @aa:24 → Rd8 — — MOV.B Rs, @ERd B Rs8 → @ERd — — MOV.B Rs, @(d:16, ERd) B 4 Rs8 → @(d:16, ERd) — — MOV.
Appendix No. of States*1 Condition Code — — @(d:24, ERs) → ERd32 — — @ERs → ERd32 ERs32+4 → ERs32 — — 6 @aa:16 → ERd32 — — 8 @aa:24 → ERd32 — — ERs32 → @ERd — — ERs32 → @(d:16, ERd) — — ERs32 → @(d:24, ERd) — — ERd32–4 → ERd32 ERs32 → @ERd — — 6 ERs32 → @aa:16 — — 8 ERs32 → @aa:24 — — 0 — 0 — POP POP.W Rn W 2 @SP → Rn16 SP+2 → SP — — POP.L ERn L 4 @SP → ERn32 SP+4 → SP — — 0 — PUSH PUSH.W Rn W 2 SP–2 → SP Rn16 → @SP — — 0 — PUSH.
Appendix 2. Arithmetic Instructions No. of States*1 Condition Code Z V C ↔ ↔ — (2) ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ERd32+ERs32 → ERd32 — (2) ↔ ↔ (3) ↔ ↔ Rd16+Rs16 → Rd16 — (1) ERd32+#xx:32 → ERd32 Rd8+#xx:8 +C → Rd8 — 2 B 2 Rd8+Rs8 +C → Rd8 — ADDS ADDS.L #1, ERd L 2 ERd32+1 → ERd32 — — — — — — 2 ADDS.L #2, ERd L 2 ERd32+2 → ERd32 — — — — — — 2 ADDS.L #4, ERd L 2 ERd32+4 → ERd32 — — — — — — 2 INC.B Rd B 2 Rd8+1 → Rd8 — — INC.W #1, Rd W 2 Rd16+1 → Rd16 — — INC.
Appendix No. of States*1 Condition Code Advanced V C ERd32–1 → ERd32 — — L 2 ERd32–2 → ERd32 — — ↔ ↔ — 2 DAS.Rd B 2 Rd8 decimal adjust → Rd8 — * ↔ ↔ ↔ 2 DEC.L #2, ERd ↔ ↔ ↔ — * — 2 B 2 Rd8 × Rs8 → Rd16 (unsigned multiplication) — — — — — — 14 W 2 Rd16 × Rs16 → ERd32 (unsigned multiplication) — — — — — — 22 B 4 Rd8 × Rs8 → Rd16 (signed multiplication) — — ↔ W 4 Rd16 × Rs16 → ERd32 (signed multiplication) — — B 2 W DIVXU DIVXU. B Rs, Rd DIVXU.
Appendix No. of States*1 Condition Code W 2 0–Rd16 → Rd16 — NEG.L ERd L 2 0–ERd32 → ERd32 — EXTU EXTU.W Rd W 2 0 → ( of Rd16) — — 0 EXTU.L ERd L 2 0 → ( of ERd32) — — 0 EXTS EXTS.W Rd W 2 ( of Rd16) → ( of Rd16) — — EXTS.L ERd L 2 ( of ERd32) → ( of ERd32) — — Advanced ↔ ↔ ↔ NEG.W Rd Normal C ↔ ↔ ↔ — ↔ ↔ ↔ V ↔ ↔ ↔ ↔ 0–Rd8 → Rd8 2 0 — 2 ↔ 2 0 — 2 ↔ H B 0 — 2 ↔ Z ↔ I NEG NEG.
Appendix 3. Logic Instructions AND.B Rs, Rd B AND.W #xx:16, Rd W 4 AND.W Rs, Rd W AND.L #xx:32, ERd L AND.L ERs, ERd L OR.B #xx:8, Rd B OR.B Rs, Rd B OR.W #xx:16, Rd W 4 OR.W Rs, Rd W OR.L #xx:32, ERd L OR.L ERs, ERd L XOR.B #xx:8, Rd B XOR.B Rs, Rd B XOR.W #xx:16, Rd W 4 XOR.W Rs, Rd W XOR.L #xx:32, ERd L XOR.L ERs, ERd L 4 ERd32⊕ERs32 → ERd32 — — NOT.B Rd B 2 ¬ Rd8 → Rd8 — — NOT.W Rd W 2 ¬ Rd16 → Rd16 — — NOT.
Appendix 4. Shift Instructions W 2 SHAL.L ERd L 2 SHAR SHAR.B Rd B 2 SHAR.W Rd W 2 SHAR.L ERd L 2 SHLL SHLL.B Rd B 2 SHLL.W Rd W 2 SHLL.L ERd L 2 SHLR SHLR.B Rd B 2 SHLR.W Rd W 2 SHLR.L ERd L 2 ROTXL ROTXL.B Rd B 2 ROTXL.W Rd W 2 ROTXL.L ERd L 2 B 2 ROTXR.W Rd W 2 ROTXR.L ERd L 2 ROTL ROTL.B Rd B 2 ROTL.W Rd W 2 ROTL.L ERd L 2 ROTR ROTR.B Rd B 2 ROTR.W Rd W 2 ROTR.L ERd L 2 ROTXR ROTXR.
Appendix 5.
Appendix B BLD #xx:3, @aa:8 B BILD BILD #xx:3, Rd BST BILD #xx:3, @ERd B BILD #xx:3, @aa:8 B BST #xx:3, Rd B BST #xx:3, @ERd B BST #xx:3, @aa:8 B BIST BIST #xx:3, Rd B BIST #xx:3, @ERd B BIST #xx:3, @aa:8 B BAND BAND #xx:3, Rd B BAND #xx:3, @ERd B BAND #xx:3, @aa:8 B BIAND BIAND #xx:3, Rd BOR B B BIAND #xx:3, @ERd B BIAND #xx:3, @aa:8 B BOR #xx:3, Rd B BOR #xx:3, @ERd B BOR #xx:3, @aa:8 B BIOR BIOR #xx:3, Rd B BIOR #xx:3, @ERd B BIOR #xx:3, @aa:8 B BXOR BXOR #
Appendix 6. Branching Instructions Bcc No.
Appendix JMP BSR JSR RTS JMP @ERn — JMP @aa:24 — JMP @@aa:8 — BSR d:8 — BSR d:16 — JSR @ERn — JSR @aa:24 — JSR @@aa:8 — RTS — No.
Appendix 7. System Control Instructions No.
Appendix 8. Block Transfer Instructions EEPMOV No. of States*1 H N Z V C Normal — @@aa @(d, PC) I EEPMOV. B — 4 if R4L ≠ 0 then repeat @R5 → @R6 R5+1 → R5 R6+1 → R6 R4L–1 → R4L until R4L=0 else next — — — — — — 8+ 4n*2 EEPMOV.
REJ09B0028-0500 Rev.5.00 Nov. 02, 2005 Page 370 of 418 MULXU 5 STC Table A-2 (2) LDC 3 BVC 8 SUBX OR XOR AND MOV C D E F BILD BIST BLD BST MOV BVS 9 B JMP BPL BMI MOV Table A-2 Table A-2 (2) (2) Table A-2 Table A-2 (2) (2) A Table A-2 Table A-2 EEPMOV (2) (2) SUB ADD Table A-2 TRAPA (2) BEQ B BIAND BAND AND RTE BNE CMP BIXOR BXOR XOR BSR BCS A BIOR BOR OR RTS BCC MOV.B Table A-2 (2) LDC 7 ADDX BTST DIVXU BLS AND.B ANDC 6 9 BCLR MULXU BHI XOR.
ADD MOV 7A BRN ADD BRA 58 MOV DAS 1F 1 79 SUBS 1B NOT 17 DEC ROTXR 13 1A ROTXL 12 DAA 0F SHLR ADDS 0B 11 INC 0A SHLL MOV 01 10 0 CMP CMP BHI 2 SUB SUB BLS NOT ROTXR ROTXL SHLR SHLL 3 4 OR OR BCC LDC/STC 1st byte 2nd byte AH AL BH BL XOR XOR BCS DEC EXTU INC 5 AND AND BNE 6 BEQ DEC EXTU INC 7 BVC SUB NEG 9 BVS ROTR ROTL SHAR SHAL ADDS SLEEP 8 BPL A MOV BMI NEG CMP SUB ROTR ROTL SHAR C D BGE BLT DEC EXTS INC Table
REJ09B0028-0500 Rev.5.00 Nov. 02, 2005 Page 372 of 418 DIVXS 3 BSET 7Faa7 * 2 BNOT BNOT BCLR BCLR Notes: 1. r is the register designation field. 2. aa is the absolute address field.
Appendix A.3 Number of Execution States The status of execution for each instruction of the H8/300H CPU and the method of calculating the number of states required for instruction execution are shown below. Table A.4 shows the number of cycles of each type occurring in each instruction, such as instruction fetch and data read/write. Table A.3 shows the number of states required for each cycle.
Appendix Table A.3 Number of Cycles in Each Instruction Access Location Execution Status (Instruction Cycle) On-Chip Memory On-Chip Peripheral Module 2 — Instruction fetch SI Branch address read SJ Stack operation SK Byte data access SL 2 or 3* Word data access SM 2 or 3* Internal operation SN Note: * 1 Depends on which on-chip peripheral module is accessed. See section 20.1, Register Addresses (Address Order). Rev.5.00 Nov.
Appendix Table A.4 Number of Cycles in Each Instruction Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N ADD ADD.B #xx:8, Rd 1 ADD.B Rs, Rd 1 ADD.W #xx:16, Rd 2 ADD.W Rs, Rd 1 ADD.L #xx:32, ERd 3 ADD.L ERs, ERd 1 ADDS ADDS #1/2/4, ERd 1 ADDX ADDX #xx:8, Rd 1 ADDX Rs, Rd 1 AND.B #xx:8, Rd 1 AND.B Rs, Rd 1 AND.W #xx:16, Rd 2 AND.W Rs, Rd 1 AND.L #xx:32, ERd 3 AND Stack K AND.
Appendix Instruction Mnemonic Bcc BCLR BIAND BILD Instruction Branch Byte Data Word Data Internal Fetch Addr.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N BTST BTST #xx:3, Rd 1 BTST #xx:3, @ERd 2 1 BTST #xx:3, @aa:8 2 1 BTST Rn, Rd 1 BTST Rn, @ERd 2 1 1 BXOR CMP Stack K BTST Rn, @aa:8 2 BXOR #xx:3, Rd 1 BXOR #xx:3, @ERd 2 1 BXOR #xx:3, @aa:8 2 1 CMP.B #xx:8, Rd 1 CMP.B Rs, Rd 1 CMP.W #xx:16, Rd 2 CMP.W Rs, Rd 1 CMP.L #xx:32, ERd 3 CMP.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N INC INC.B Rd 1 INC.W #1/2, Rd 1 INC.L #1/2, ERd 1 JMP @ERn 2 JMP @aa:24 2 JMP @@aa:8 2 JSR @ERn 2 1 JSR @aa:24 2 1 JSR @@aa:8 2 LDC #xx:8, CCR 1 LDC Rs, CCR 1 LDC@ERs, CCR 2 1 LDC@(d:16, ERs), CCR 3 1 LDC@(d:24,ERs), CCR 5 1 LDC@ERs+, CCR 2 1 LDC@aa:16, CCR 3 1 LDC@aa:24, CCR 4 1 MOV.B #xx:8, Rd 1 MOV.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N MOV MOV.B Rs, @aa:16 2 1 MOV.B Rs, @aa:24 3 1 MOV.W #xx:16, Rd 2 MOV.W Rs, Rd 1 MOV.W @ERs, Rd 1 1 MOV.W @(d:16,ERs), Rd 2 1 MOV.W @(d:24,ERs), Rd 4 1 MOV.W @ERs+, Rd 1 1 MOV.W @aa:16, Rd 2 1 MOV.W @aa:24, Rd 3 1 MOV.W Rs, @ERd 1 1 MOV.W Rs, @(d:16,ERd) 2 1 MOV.W Rs, @(d:24,ERd) 4 1 MOV.W Rs, @-ERd 1 1 MOV.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N MULXS MULXS.B Rs, Rd 2 12 MULXS.W Rs, ERd 2 20 MULXU MULXU.B Rs, Rd 1 12 MULXU.W Rs, ERd 1 20 NEG.B Rd 1 NEG.W Rd 1 NEG NEG.L ERd 1 NOP NOP 1 NOT NOT.B Rd 1 NOT.W Rd 1 NOT.L ERd 1 OR Stack K OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 OR.W #xx:16, Rd 2 OR.W Rs, Rd 1 OR.L #xx:32, ERd 3 OR.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J L M N ROTXR ROTXR.B Rd 1 ROTXR.W Rd 1 ROTXR.L ERd 1 RTE RTE 2 2 2 RTS RTS 2 1 2 SHAL SHAL.B Rd 1 SHAL.W Rd 1 SHAL.L ERd 1 SHAR.B Rd 1 SHAR.W Rd 1 SHAR.L ERd 1 SHAR SHLL SHLR SHLL.B Rd 1 SHLL.W Rd 1 SHLL.L ERd 1 SHLR.B Rd 1 SHLR.W Rd 1 Stack K SHLR.
Appendix Instruction Branch Byte Data Word Data Internal Fetch Addr. Read Operation Access Access Operation Instruction Mnemonic I J K L M N SUBX SUBX #xx:8, Rd 1 1 2 SUBX. Rs, Rd 1 TRAPA TRAPA #xx:2 2 XOR XOR.B #xx:8, Rd 1 XOR.B Rs, Rd 1 XOR.W #xx:16, Rd 2 XOR.W Rs, Rd 1 XOR.L #xx:32, ERd 3 XOR.L ERs, ERd 2 XORC #xx:8, CCR 1 XORC Stack 4 Notes: 1. n: Specified value in R4L. The source and destination operands are accessed n+1 times respectively. 2.
Appendix A.4 Combinations of Instructions and Addressing Modes Table A.5 Combinations of Instructions and Addressing Modes Arithmetic operations MOVTPE ADD, CMP SUB ADDX, SUBX ADDS, SUBS INC, DEC DAA, DAS MULXU, — @aa:24 @@aa:8 BWL BWL WL BWL B B — L — BWL BWL BWL — — — — @(d:16.PC) B — — @aa:16 @aa:8 @ERn+/@ERn @ERn BWL BWL BWL BWL BWL BWL — — — — — — — — — — — — @(d:8.PC) Data MOV transfer POP, PUSH instructions MOVFPE, Rn #xx Instructions @(d:24.ERn) Functions @(d:16.
Appendix Appendix B I/O Port Block Diagrams B.1 I/O Port Block Diagrams RES goes low in a reset, and SBY goes low in a reset and in standby mode. Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ TRGV [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.1 Port 1 Block Diagram (P17) Rev.5.00 Nov.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR IRQ [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.2 Port 1 Block Diagram (P16 to P14) Rev.5.00 Nov.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PDR PCR [Legend] PUCR: Port pull-up control register PDR: Port data register PCR: Port control register Figure B.3 Port 1 Block Diagram (P12, P11) Rev.5.00 Nov.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR Timer A TMOW [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.4 Port 1 Block Diagram (P10) Rev.5.00 Nov.
Appendix Internal data bus SBY PMR PDR PCR SCI3 TxD [Legend] PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.5 Port 2 Block Diagram (P22) Rev.5.00 Nov.
Appendix SBY Internal data bus PDR PCR SCI3 RE RxD [Legend] PDR: Port data register PCR: Port control register Figure B.6 Port 2 Block Diagram (P21) Rev.5.00 Nov.
Appendix SBY SCI3 SCKIE SCKOE Internal data bus PDR PCR SCKO SCKI [Legend] PDR: Port data register PCR: Port control register Figure B.7 Port 2 Block Diagram (P20) Rev.5.00 Nov.
Appendix Internal data bus SBY PDR PCR IIC2 ICE SDAO/SCLO SDAI/SCLI [Legend] PDR: Port data register PCR: Port control register Figure B.8 Port 5 Block Diagram (P57, P56)* Note: * This diagram is applied to the SCL and SDA pins in the H8/3694N. Rev.5.00 Nov.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP ADTRG [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.9 Port 5 Block Diagram (P55) Rev.5.00 Nov.
Appendix Internal data bus RES SBY PUCR Pull-up MOS PMR PDR PCR WKP [Legend] PUCR: Port pull-up control register PMR: Port mode register PDR: Port data register PCR: Port control register Figure B.10 Port 5 Block Diagram (P54 to P50) Rev.5.00 Nov.
Appendix Internal data bus SBY Timer V OS3 OS2 OS1 OS0 PDR PCR TMOV [Legend] PDR: Port data register PCR: Port control register Figure B.11 Port 7 Block Diagram (P76) Rev.5.00 Nov.
Appendix Internal data bus SBY PDR PCR Timer V TMCIV [Legend] PDR: Port data register PCR: Port control register Figure B.12 Port 7 Block Diagram (P75) Rev.5.00 Nov.
Appendix Internal data bus SBY PDR PCR Timer V TMRIV [Legend] PDR: Port data register PCR: Port control register Figure B.13 Port 7 Block Diagram (P74) Rev.5.00 Nov.
Appendix Internal data bus SBY PDR PCR [Legend] PDR: Port data register PCR: Port control register Figure B.14 Port 8 Block Diagram (P87 to P85) Rev.5.00 Nov.
Appendix Internal data bus SBY Timer W Output control signals A to D PDR PCR FTIOA FTIOB FTIOC FTIOD [Legend] PDR: Port data register PCR: Port control register Figure B.15 Port 8 Block Diagram (P84 to P81) Rev.5.00 Nov.
Appendix Internal data bus SBY PDR PCR Timer W FTCI [Legend] PDR: Port data register PCR: Port control register Figure B.16 Port 8 Block Diagram (P80) Rev.5.00 Nov.
Appendix Internal data bus A/D converter CH3 to CH0 DEC VIN Figure B.17 Port B Block Diagram (PB7 to PB0) B.
Appendix Appendix C Product Code Lineup Product Classification Product Code Model Marking Package Code H8/3694 HD64F3694H HD64F3694H QFP-64 (FP-64A) HD64F3694FP HD64F3694FP LQFP-64 (FP-64E) HD64F3694FX HD64F3694FX LQFP-48 (FP-48F) Flash memory Standard version product Mask ROM version HD64F3694FY HD64F3694FY LQFP-48 (FP-48B) HD64F3694FT HD64F3694FT QFN-48(TNP-48) Product with HD64F3694GH HD64F3694GH POR & LVDC HD64F3694GFP HD64F3694GFP LQFP-64 (FP-64E) HD64F3694GFX HD64F3694GFX LQFP
Appendix Product Classification H8/3692 Mask ROM version H8/3691 Mask ROM version Product Code Model Marking Package Code HD6433692H HD6433692(***)H QFP-64 (FP-64A) HD6433692FP HD6433692(***)FP LQFP-64 (FP-64E) HD6433692FX HD6433692(***)FX LQFP-48 (FP-48F) HD6433692FY HD6433692(***)FY LQFP-48 (FP-48B) HD6433692FT HD6433692(***)FT QFN-48(TNP-48) Product with HD6433692GH POR & LVDC HD6433692G(***)H QFP-64 (FP-64A) HD6433692GFP HD6433692G(***)FP LQFP-64 (FP-64E) HD6433692GFX HD643369
Appendix Product Classification Product Code Model Marking H8/3694N EEPROM Flash Product with HD64N3694GFP HD64N3694GFP stacked memory POR & LVDC version version Mask ROM version HD6483694GFP REJ09B0028-0500 LQFP-64 (FP-64E) HD6483694G(***)FP LQFP-64 (FP-64E) Legend: (***): ROM code. POR & LVDC: Power-on reset and low-voltage detection circuits. Rev.5.00 Nov.
64 e ZD 1 y *3 bp Index mark D 16 33 x F M 17 32 E *2 49 48 *1 MASS[Typ.] 0.4g Detail F L1 L Terminal cross section b1 bp θ 11.8 0.5 L 1.0 1.25 ZE L1 1.25 ZD 0.7 0.08 8° 0.10 0.5 0.22 y 0.3 0° 0.15 0.27 x e θ c1 0.20 0.17 c 0.22 b1 0.12 0.17 0.20 bp 1.70 0.10 A1 12.2 12.2 Max A 0.00 12.0 12.0 HD 11.8 A2 HE 10 1.45 E 10 Nom Dimension in Millimeters Min D Reference Symbol NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2.
Figure D.2 FP-64A Package Dimensions 64 e 1 ZD D HD y *3 bp 16 33 x F M 17 32 E *2 49 48 *1 Previous Code FP-64A/FP-64AV MASS[Typ.] 1.2g Detail F L1 L Terminal cross section b1 bp θ 17.2 16.9 16.9 A2 HD HE 0.5 1.6 0.8 L L1 1.0 ZE 1.1 0.10 1.0 ZD 0.15 8° y 0.8 0.22 x e θ 0° 0.17 0.15 c c1 0.35 b1 0.12 0.29 bp 0.45 0.25 0.00 A1 0.37 3.05 17.5 17.5 Max A 0.10 17.2 14 2.70 E 14 Nom Dimension in Millimeters Min D Reference Symbol NOTE) 1.
48 e ZD 1 *3 bp y Index mark D HD 12 25 x M F 13 24 E *2 37 36 *1 MASS[Typ.] 0.4g Detail F L1 L Terminal cross section b1 bp θ 11.8 0.1 0.5 L 1.0 1.425 ZE L1 1.425 ZD 0.6 0.10 8° 0.22 0.13 0.65 0.15 0.17 0.37 y 0.4 0° 0.12 0.30 0.32 x e θ c1 c b1 0.27 0.15 bp A1 12.2 12.2 1.70 0.05 12.0 12.0 Max A HE HD 11.8 10 1.45 E A2 10 Nom Dimension in Millimeters Min D Reference Symbol NOTE) 1.
Figure D.4 FP-48B Package Dimensions 48 e ZD 1 D HD *3 bp y 12 25 x M F 13 24 E *2 37 36 *1 Previous Code FP-48B/FP-48BV MASS[Typ.] 0.2g Detail F L1 L Terminal cross section b1 bp θ 0.10 0.17 L1 1.0 0.5 0.75 ZE L 0.75 ZD 0.6 0.08 8° 0.22 0.27 0.08 0.5 0.15 0.17 0.20 0.22 y 0.4 0° 0.12 0.17 1.70 9.2 9.2 Max x e θ c1 c b1 bp A1 0.03 9.0 8.8 A 9.0 8.8 A2 HE 7 1.40 E HD 7 Nom Dimension in Millimeters Min D Reference Symbol NOTE) 1.
E c c1 HE 48 37 1 36 x4 D y y1 t HD ZD 12 25 RENESAS Code PVQN0048KA-A 13 24 ZE A2 A 1 Previous Code TNP-48/TNP-48V MASS[Typ.] 0.1g b b1 ×M e Lp A JEITA Package Code P-VQFN48-7x7-0.50 7.0 0.5 0.47 0.05 c 1 E Z 0.15 0.17 0.75 D c 7.2 0.75 HE Z 7.2 HD t 0.22 0.20 0.20 0.35 0.05 0.12 0.23 0.20 y 1 p 1 y x L e b 0.04 0.27 0.17 b 0.22 1.00 0.02 0.005 A1 Max A 0.90 E A2 7.
Appendix Appendix E EEPROM Stacked-Structure Cross-Sectional View Figure E.1 EEPROM Stacked-Structure Cross-Sectional View Rev.5.00 Nov.
Main Revisions and Additions in this Edition Item Page Revision (See Manual for Details) Preface vi, vii Notes: When using the on-chip emulator (E7, E8) for H8/3694 program development and debugging, the following restrictions must be noted. 1. The NMI pin is reserved for the E7 or E8, and cannot be used. 3. Area H'7000 to H'7FFF is used by the E7 or E8, and is not available to the user. 5. When the E7 or E8 is used, address breaks can be set as either available to the user or for use by the E7 or E8.
Item Page Revision (See Manual for Details) Section 5 Clock Pulse Generators 70 C1 OSC 1 Figure 5.3 Typical Connection to Crystal Resonator Figure 5.5 Typical Connection to Ceramic Resonator OSC 2 71 C2 C1 = C 22 = 10 to 22 pF C1 OSC1 C2 OSC2 Section 6 Power-Down Modes 6.1.
Item Page Revision (See Manual for Details) 2 Section 15 I C Bus Interface 2 (IIC2) 15.3.5 I2C Bus Status Register (ICSR) 242 Bit Bit Name Description 3 STOP Stop Condition Detection Flag [Setting conditions] • In master mode, when a stop condition is detected after frame transfer • In slave mode, when a stop condition is detected after the general call address or the first byte slave address, next to detection of start condition, accords with the address set in SAR 15.
Item Page Table 21.2 DC Characteristics (1) 321 Revision (See Manual for Details) Mode RES Pin Internal State Active mode 1 VCC Operates Active mode 2 Operates (φOSC/64) Sleep mode 1 VCC Only timers operate Sleep mode 2 Table 21.12 DC Characteristics (1) Only timers operate (φOSC/64) 337 Item Input high voltage Values Applicable Symbol Pins Test Condition Min VIH VCC = 4.0 to 5.5 V VCC × 0.7 PB0 to PB7 VCC × 0.
Index A A/D converter ......................................... 265 Sample-and-hold circuit...................... 272 Scan mode........................................... 271 Single mode ........................................ 271 Address break ........................................... 63 Addressing modes..................................... 34 Absolute address................................... 36 Immediate ............................................. 36 Memory indirect ................................
I/O port block diagrams ...................... 385 I C bus data format ................................. 246 I2C bus interface 2 (IIC2) ....................... 231 Acknowledge...................................... 247 Bit synchronous circuit....................... 263 Clocked synchronous serial format..... 255 Noise canceler .................................... 257 Slave address ...................................... 246 Start condition .................................... 246 Stop condition................
EBR1 ............................ 91, 303, 308, 311 EKR ............................ 279, 306, 310, 313 FENR............................ 92, 303, 308, 311 FLMCR1....................... 89, 303, 308, 311 FLMCR2....................... 90, 303, 308, 311 FLPWCR ...................... 92, 303, 308, 311 GRA............................ 165, 302, 307, 311 GRB............................ 165, 303, 307, 311 GRC............................ 165, 303, 307, 311 GRD............................ 165, 303, 307, 311 ICCR1....
Mark state ........................................... 229 Multiprocessor communication function............................................... 221 Overrun error ...................................... 209 Parity error.......................................... 209 Stacked-structure cross sectional view of H8/3694N .................................. 410 Stack pointer (SP)..................................... 19 Timer V................................................... 137 Timer W............................
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8/3694 Group Publication Date: 1st Edition, Jul, 2001 Rev.5.00, Nov. 02, 2005 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. 2005. Renesas Technology Corp. All rights reserved. Printed in Japan.
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H8/3694Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0028-0500
