Datasheet

Section 11 Timer V
Rev.5.00 Nov. 02, 2005 Page 151 of 418
REJ09B0028-0500
φ
Address
TCORA address
Internal write signal
TCNTV
TCORA
N
N
N+1
M
TCORA write data
Inhibited
T
1
T
2
T
3
TCORA write cycle by CPU
Compare match signal
Figure 11.12 Contention between TCORA Write and Compare Match
Clock before
switching
Clock after
switching
Count clock
TCNTV N N+1 N+2
Write to CKS1 and CKS0
Figure 11.13 Internal Clock Switching and TCNTV Operation