Datasheet

Section 20 List of Registers
Rev.5.00 Nov. 02, 2005 Page 302 of 418
REJ09B0028-0500
20.1 Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Note: Access to undefined or reserved addresses should not take place. Correct operation of the
access itself or later operations is not guaranteed when such a register is accessed.
Register Name
Abbre-
viation
Bit
No
Address
Module
Name
Data
Bus
Width
Access
State
— — — H'F000 to
H'F72F
— — —
Low-voltage detection control
register
LVDCR 8 H'F730 LVDC*
1
8 2
Low-voltage detection status register LVDSR 8 H'F731 LVDC*
1
8 2
— — — H'F732 to
H'F747
— — —
I
2
C bus control register 1 ICCR1 8 H'F748 IIC2 8 2
I
2
C bus control register 2 ICCR2 8 H'F749 IIC2 8 2
I
2
C bus mode register ICMR 8 H'F74A IIC2 8 2
I
2
C bus interrupt enable register ICIER 8 H'F74B IIC2 8 2
I
2
C bus status register ICSR 8 H'F74C IIC2 8 2
Slave address register SAR 8 H'F74D IIC2 8 2
I
2
C bus transmit data register ICDRT 8 H'F74E IIC2 8 2
I
2
C bus receive data register ICDRR 8 H'F74F IIC2 8 2
— — — H'F750 to
H'FF7F
— — —
Timer mode register W TMRW 8 H'FF80 Timer W 8 2
Timer control register W TCRW 8 H'FF81 Timer W 8 2
Timer interrupt enable register W TIERW 8 H'FF82 Timer W 8 2
Timer status register W TSRW 8 H'FF83 Timer W 8 2
Timer I/O control register 0 TIOR0 8 H'FF84 Timer W 8 2
Timer I/O control register 1 TIOR1 8 H'FF85 Timer W 8 2
Timer counter TCNT 16 H'FF86 Timer W 16*
2
2
General register A GRA 16 H'FF88 Timer W 16*
2
2