Datasheet

Rev.5.00 Nov. 02, 2005 Page 413 of 418
REJ09B0028-0500
Item Page Revision (See Manual for Details)
Bit Bit Name Description
3 STOP Stop Condition Detection Flag
[Setting conditions]
• In master mode, when a stop condition is
detected after frame transfer
• In slave mode, when a stop condition is
detected after the general call address or
the first byte slave address, next to
detection of start condition, accords with
the address set in SAR
Section 15 I
2
C Bus
Interface 2 (IIC2)
15.3.5 I
2
C Bus Status
Register (ICSR)
242
15.7 Usage Notes 264 Added
Section 16 A/D Converter
16.3.1 A/D Data Registers
A to D (ADDRA to
ADDRD)
268 Therefore byte access to ADDR should be done by reading the
upper byte first then the lower one. Word access is also
possible. ADDR is initialized to H'0000.
Section 18 Power-On
Reset and Low-Voltage
Detection Circuits
(Optional)
Figure 18.1 Block
Diagram of Power-On
Reset Circuit and Low-
Voltage Detection Circuit
290
RES
C RES
Values
Item Symbol
Applicable
Pins Test Condition
Min
V
CC
= 4.0 to 5.5 V V
CC
× 0.7 Input high
voltage
V
IH
PB0 to PB7
V
CC
× 0.8
V
CC
= 4.0 to 5.5 V –0.3 Input low
voltage
V
IL
RXD,SCL,
SDA,
P10 to P12,
:
P80 to P87
PB0 to PB7
–0.3
Section 21 Electrical
Characteristics
Table 21.2 DC
Characteristics (1)
318