Datasheet

Section 12 Timer W
Rev.5.00 Nov. 02, 2005 Page 171 of 418
REJ09B0028-0500
Figure 12.11 shows an example of buffer operation when the FTIOB pin is set to PWM mode and
GRD is set as the buffer register for GRB. TCNT is cleared by compare match A, and FTIOB
outputs 1 at compare match B and 0 at compare match A.
Due to the buffer operation, the FTIOB output level changes and the value of buffer register GRD
is transferred to GRB whenever compare match B occurs. This procedure is repeated every time
compare match B occurs.
TCNT value
GRA
H'0000
GRD
Time
GRB
H'0200 H'0520
FTIOB
H'0200
H'0450
H'0520
H'0450
GRB
H'0450 H'0520
H'0200
Figure 12.11 Buffer Operation Example (Output Compare)
Figures 12.12 and 12.13 show examples of the output of PWM waveforms with duty cycles of 0%
and 100%.