Datasheet

Section 3 Exception Handling
Rev.5.00 Nov. 02, 2005 Page 50 of 418
REJ09B0028-0500
Relative Module Exception Sources
Vector
Number Vector Address Priority
CPU Direct transition by executing
the SLEEP instruction
13 H'001A to H'001B High
External interrupt
pin
IRQ0
Low-voltage detection
interrupt*
14 H'001C to H'001D
IRQ1 15 H'001E to H'001F
IRQ2 16 H'0020 to H'0021
IRQ3 17 H'0022 to H'0023
WKP 18 H'0024 to H'0025
Timer A Overflow 19 H’0026 to H’0027
 Reserved for system use 20 H’0028 to H’0029
Timer W Timer W input capture A
/compare match A
Timer W input capture B
/compare match B
Timer W input capture C
/compare match C
Timer W input capture D
/compare match D
Timer W overflow
21 H’002A to H’002B
Timer V Timer V compare match A
Timer V compare match B
Timer V overflow
22 H'002C to H'002D
SCI3 SCI3 receive data full
SCI3 transmit data empty
SCI3 transmit end
SCI3 receive error
23 H'002E to H'002F
IIC2 Transmit data empty
Transmit end
Receive data full
Arbitration lost/Overrun error
NACK detection
Stop conditions detected
24 H'0030 to H'0031
A/D converter A/D conversion end 25 H'0032 to H'0033 Low
Note * A low-voltage detection interrupt is enabled only in the product with an on-chip power-
on reset and low-voltage detection circuit.