Datasheet

Section 3 Exception Handling
Rev. 8.00 Mar. 09, 2010 Page 81 of 658
REJ09B0042-0800
Interrupt Enable Register 1 (IENR1)
Bit
Initial value
Read/Write
7
IENTA
0
R/W
6
⎯
⎯
W
5
IENWP
0
R/W
4
IEN4
0
R/W
3
IEN3
0
R/W
0
IEN0
0
R/W
2
IENEC2
0
R/W
1
IEN1
0
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7—Timer A Interrupt Enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA Description
0 Disables timer A interrupt requests (initial value)
1 Enables timer A interrupt requests
Bit 6—Reserved
Bit 6 is reserved: it can only be written with 0.
Bit 5—Wakeup Interrupt Enable (IENWP)
Bit 5 enables or disables WKP
7
to WKP
0
interrupt requests.
Bit 5
IENWP Description
0 Disables WKP
7
to WKP
0
interrupt requests (initial value)
1 Enables WKP
7
to WKP
0
interrupt requests
Bits 4 and 3—IRQ
4
and IRQ
3
Interrupt Enable (IEN4 and IEN3)
Bits 4 and 3 enable or disable IRQ
4
and IRQ
3
interrupt requests.
Bit n
IENn Description
0 Disables interrupt requests from pin IRQn (initial value)
1 Enables interrupt requests from pin IRQn
(n = 4 or 3)