Datasheet

Section 6 ROM
Rev. 8.00 Mar. 09, 2010 Page 153 of 658
REJ09B0042-0800
Figure 6.5 shows a PROM write/verify timing diagram.
Write
Input data Output data
Verify
Address
Data
V
PP
V PP
t AS t AH
t DS t DH t DF
t OE t OES t PW
t OPW
*
t
VPS
t VCS
t CES
V CC
V CC
CE
PGM
OE
V
CC
+1
V CC
Note: * t OPW is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
Figure 6.5 PROM Write/Verify Timing