Datasheet

Section 6 ROM
Rev. 8.00 Mar. 09, 2010 Page 175 of 658
REJ09B0042-0800
Erase start
Set EBR
Enable WDT
Wait 1 μs
Wait 100 μs
SWE bit ← 1
n ← 1
ESU bit ← 1
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 μs
ESU bit ← 0
Wait 10 μs
Disable WDT
Read verify data
Increment address
Verify data = all 1s ?
Last address of block ?
All erase block erased ?
Set block start address as verify address
H'FF dummy write to verify address
Wait 20 μs
Wait 2 μs
EV bit ← 1
Wait 100 μs
End of erasing
SWE bit ← 0
Wait 4 μs
EV bit ← 0
n ≤100 ?
Wait 100 μs
Erase failure
SWE bit ← 0
Wait 4μs
EV bit ← 0
n ← n + 1
Yes
No
Yes
Yes
Yes
No
No
No
Figure 6.11 Erase/Erase-Verify Flowchart