Datasheet

Section 9 Timers
Rev. 8.00 Mar. 09, 2010 Page 314 of 658
REJ09B0042-0800
Block Diagram
Figure 9.19 shows a block diagram of the asynchronous event counter.
AEVH
AEVL
IRQAEC
IECPWM
ECCR
PSS
ECCSR
OVH
OVL
ECPWCRH
ECPWDRH
AEGSR
ECPWCRL
Internal data bus
ECPWDRL
ECH
(8 bits)
CK
ECL
(8 bits)
CK
IRREC
To CPU interrupt
(IRREC2)
Edge sensing
circuit
Edge sensing
circuit
Edge sensing
circuit
PWM waveform generator
φ
φ/2
φ/4, φ/8
φ /2, φ /4,
φ /8, φ /16,
φ /32, φ /64
[Legend]
ECPWCRH: Event counter PWM compare register H
ECPWDRH: Event counter PWM data register H
AEGSR: Input pin edge select register
ECCSR: Event counter control/status register
ECH: Event counter H
ECL: Event counter L
ECPWCRL: Event counter PWM compare register L
E
CPWDRL: Event counter PWM data register L
ECCR: Event counter control register
Figure 9.19 Block Diagram of Asynchronous Event Counter