Datasheet

Section 16 Electrical Characteristics
Rev. 8.00 Mar. 09, 2010 Page 477 of 658
REJ09B0042-0800
Values
Item Symbol
Applicable
Pins
Min Typ Max Unit Test Condition
Reference
Figure
t
CPH
OSC
1
40 — — ns Figure 16.2 External clock high
width
X
1
— 15.26
or
13.02
— µs
t
CPL
OSC
1
40 — — ns Figure 16.2 External clock low
width
X
1
— 15.26
or
13.02
— µs
t
CPr
OSC
1
— — 10 ns Figure 16.2 External clock rise
time
X
1
— — 55.0 ns
t
CPf
OSC
1
— — 10 ns Figure 16.2 External clock fall
time
X
1
— — 55.0 ns
Pin RES low width t
REL
RES 10 — — t
cyc
Figure 16.3
Input pin high width t
IH
IRQ
0
, IRQ
1
,
IRQ
3
, IRQ
4
,
IRQAEC,
WKP
0
to
WKP
7
,
TMIC, TMIF,
TMIG, ADTRG
2 — — t
cyc
t
subcyc
Figure 16.4
AEVL, AEVH 0.5 — — t
osc
Input pin low width t
IL
IRQ
0
, IRQ
1
,
IRQ
3
, IRQ
4
,
IRQAEC,
WKP
0
to
WKP
7
,
TMIC, TMIF,
TMIG, ADTRG
2 — — t
cyc
t
subcyc
Figure 16.4
AEVL, AEVH 0.5 — — t
osc
UD pin minimum
transition width
t
UDH
t
UDL
UD 4 — — t
cyc
t
subcyc
Figure 16.7
Notes: 1. Selected with SA1 and SA0 of system control register 2 (SYSCR2).
2. The figure in parentheses applies when an external clock is used.
3. Applies to the HD64F38024R.
4. Applies to the HD64F38024.