Datasheet

Section 16 Electrical Characteristics
Rev. 8.00 Mar. 09, 2010 Page 516 of 658
REJ09B0042-0800
Values
Item Symbol
Applicable
Pins
Min Typ Max Unit Test Condition
Reference
Figure
Input pin high
width
t
IH
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7, TMIC,
TMIF, TMIG,
ADTRG
2 — — t
cyc
t
subcyc
Figure 16.4
AEVL, AEVH 0.5 — — t
OSC
Input pin low
width
t
IL
IRQ0, IRQ1,
IRQ3, IRQ4,
IRQAEC,
WKP0 to
WKP7, TMIC,
TMIF, TMIG,
ADTRG
2 — — t
cyc
t
subcyc
Figure 16.4
AEVL, AEVH 0.5 — — t
OSC
UD pin minimum
transition width
t
UDH
t
UDL
UD 4 — — t
cyc
t
subcyc
Figure 16.7
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. These characteristics are given as ranges between minimum and maximum values in
order to account for factors such as temperature, power supply voltage, and variation
among production lots. When designing systems, make sure to give due consideration
to the SPEC range. Please contact a Renesas sales or support representative for
actual performance data on the product.
Table 16.24 Serial Interface (SCI3) Timing
V
CC
= 2.7 V to 5.5 V, AV
CC
= 2.7 V to 5.5 V, V
SS
= AV
SS
= 0.0 V, unless otherwise specified
Values
Item Symbol Min Typ Max Unit
Test
Condition
Reference
Figure
Asynchronous t
scyc
4 — — Figure 16.5 Input clock
cycle
Clocked synchronous 6 — —
t
cyc
or
t
subcyc
Input clock pulse width t
SCKW
0.4 — 0.6 t
scyc
Figure 16.5
Transmit data delay time
(clocked synchronous)
t
TXD
— — 1 t
cyc
or
t
subcyc
Figure 16.6
Receive data setup time
(clocked synchronous)
t
RXS
150.0 — — ns Figure 16.6
Receive data hold time
(clocked synchronous)
t
RXH
150.0 — — ns Figure 16.6