Datasheet

Appendix B Internal I/O Registers
Rev. 8.00 Mar. 09, 2010 Page 568 of 658
REJ09B0042-0800
SSR—Serial Status Register H'AC SCI3
Bit
Initial value
Read/Write
Note: * Only a write of 0 for flag clearing is possible.
7
TDRE
1
R/(W)
*
6
RDRF
0
R/(W)
*
5
OER
0
R/(W)
*
0
⎯
0
R/W
2
TEND
1
R
1
⎯
0
R
4
FER
0
R/(W)
*
Receive Data Register Full
0 There is no receive data in RDR
[Clearing conditions]
· After reading RDRF = 1, cleared by writing 0 to RDRF
· When RDR data is read by an instruction
1
There is receive data in RDR
[Setting condition] When reception ends normally and receive data is transferred from RSR to RDR
Transmit Data Register Empty
0 Transmit data written in TDR has not been transferred to TSR
[Clearing conditions]
· After reading TDRE = 1, cleared by writing 0 to TDRE
· When data is written to TDR by an instruction
1 Transmit data has
not been written to TDR, or transmit data written in TDR has been transferred to TSR
[Setting conditions]
· When bit TE in serial control register3 (SCR3) is cleared to 0
· When data is transferred from TDR to TSR
Transmit End
0 Transmission in progress
[Clearing conditions]
1
Transmission ended
[Setting conditions]
Parity Error
0 Reception in progress or completed normally
[Clearing condition] After reading PER = 1, cleared by writing 0 to PER
1
A parity error has occurred during reception
[Setting condition]
Framing Error
0
Reception in progress or completed normally
[Clearing condition] After reading FER = 1, cleared by writing 0 to FER
1
A framing error has occurred during reception
[Setting condition]
When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
Overrun Error
0
Reception in progress or completed
[Clearing condition] After reading OER = 1, cleared by writing 0 to OER
1
An overrun error has occurred during reception
[Setting condition] When the next serial reception is completed with RDRF set to 1
3
PER
0
R/(W)
*
· After reading TDRE = 1, cleared by writing 0 to TDRE
· When data is written to TDR by an instruction
· When bit TE in serial control register3 (SCR3) is cleared to 0
· When bit TDRE is set to 1 when the
last bit of a transmit character is sent
When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM) in the serial mode register
(SMR)