Datasheet

Appendix B Internal I/O Registers
Rev. 8.00 Mar. 09, 2010 Page 600 of 658
REJ09B0042-0800
SYSCR1—System Control Register 1 H'F0 System Control
Bit
Initial value
Read/Write
Notes: 1. Applies to products other than the H8/38124 Group.
2. Applies to the H8/38124 Group.
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
3
LSON
0
R/W
0
MA0
1
R/W
2
⎯
1
⎯
1
MA1
1
R/W
4
STS0
0
R/W
Software Standby
0 • When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode
1
Standby Timer Select 2 to 0
0 Wait time = 8,192 states
*
1
Wait time = 16,384 states
*
1
0 0
1
Wait time = 1,024 states
*
1
Wait time = 2,048 states
*
1
10
1
Active (medium-speed)
Mode Clock Select
φ
osc
/16
φ
osc
/32
0
1
0
0
1
1
φ
osc
/64
φ
osc
/128
1
1
00
10
1
Wait time = 4,096 states
*
1
Wait time = 2 states
*
1
Wait time = 8 states
*
1
Wait time = 16 states
*
1
Wait time = 8,192 states
*
2
Wait time = 16,384 states
*
2
Wait time = 32,768 states
*
2
Wait time = 65,536 states
*
2
Wait time = 131,072 states
*
2
Wait time = 2 states
*
2
Wait time = 8 states
*
2
Wait time = 16 states
*
2
Low Speed on Flag
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ )
SUB
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
• When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode