Datasheet

Appendix B Internal I/O Registers
Rev. 8.00 Mar. 09, 2010 Page 606 of 658
REJ09B0042-0800
IRR1—Interrupt Request Register 1 H'F6 System Control
Bit
Initial value
Read/Write
7
IRRTA
0
R/(W)
*
6
⎯
⎯
W
5
⎯
1
⎯
3
IRRI3
0
R/(W)
*
0
IRRI0
0
R/(W)
*
2
IRREC2
0
R/(W)
*
1
IRRI1
0
R/(W)
*
4
IRRI4
0
R/(W)
*
IRQ1 and IRQ0 Interrupt Request Flags
0 Clearing condition:
When IRRIn = 1, it is cleared by writing 0
(n = 1 or 0)
Note: * Bits 7 and 4 to 0 can only be written with 0, for flag clearing.
1 Setting condition:
When pin IRQn is designated for interrupt
input and the designated signal edge is input
IRQ4 and IRQ3 Interrupt Request Flags
0 Clearing condition:
When IRRIm = 1, it is cleared by writting 0
(m = 4 or 3)
1 Setting condition:
When pin IRQm is designated for interrupt
input and the designated signal edge is input
Timer A Interrupt Request Flag
0 Clearing condition:
When IRRTA = 1, it is cleared by writing 0
1 Setting condition:
When the timer A counter value overflows (from H'FF to H'00)
IRQAEC Interrupt Request Flag
0 Clearing condition:
When IRREC2 = 1, it is cleared by writing 0
1 Setting condition:
When pin IRQAEC is designated for interrupt
input and the designated signal edge is input