Datasheet

Appendix B Internal I/O Registers
Rev. 8.00 Mar. 09, 2010 Page 611 of 658
REJ09B0042-0800
CKSTPR2—Clock Stop Register 2 H'FB System Control
Bit
Initial value
Read/Write
7
LVDCKSTP *
1
R/W
6
⎯
1
⎯
5
⎯
1
⎯
3
AECKSTP
1
R/W
0
LDCKSTP
1
R/W
2
WDCKSTP
1
R/W
1
PW1CKSTP
1
R/W
4
PW2CKSTP
1
R/W
LCD Module Standby Mode Control
PWM2 Module Standby Mode Control
0 PWM2 is set to module standby mode
PWM2 module standby mode is cleared
1
LVD Module Standby Mode Control
0 LVD is set to module standby mode
LVD module standby mode is cleared
Note: * Control using the LVDCKST bit is implemented on the H8/38124 Group only.
1
Asynchronous Event Counter Module Standby Mode Control
0 Asynchronous event counter is set to module standby mode
Asynchronous event counter module standby mode is cleared
1
PWM1 Module Standby Mode Control
0 PWM1 is set to module standby mode
PWM1 module standby mode is cleared
1
WDT Module Standby Mode Control
0 WDT is set to module standby mode
WDT module standby mode is cleared
1
0 LCD is set to module standby mode
LCD module standby mode is cleared
1