Datasheet

Section 2 CPU
Rev. 8.00 Mar. 09, 2010 Page 45 of 658
REJ09B0042-0800
Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15 087
op rm rn
ADD, SUB, CMP,
ADDX, SUBX (Rm)
[Legend]
op:
rm, rn:
IMM:
Operation field
Register field
Immediate data
15 087
op rn
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
15 087
op rn
MULXU, DIVXU
rm
15 087
rn IMM
ADD, ADDX, SUBX,
CMP (#XX:8)
op
15 087
op rn
AND, OR, XOR (Rm)
rm
15 087
rn IMM
AND, OR, XOR (#xx:8)
op
15 087
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
op
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes