Datasheet

Rev. 8.00 Mar. 09, 2010 Page 650 of 658
REJ09B0042-0800
Item Page Revision (See Manual for Details)
10.1.1 Features 333 Table amended
Data length
Stop bit length
Parity
Receive error detection
Break detection
7, 8, 5 bits
1 or 2 bits
Even, odd, or none
Parity, overrun, and framing errors
Break detected by reading the RXD
32 pin level directly when a
framing error occurs
10.2.5 Serial Mode
Register (SMR)
341 Description amended
Bit 2—5 Bit Communication (MP)
When this bit is one, the format of 5 bits communication
becomes possible.
In the case of writing 1 to this bit, bit 5 (PE) should be written
with 1 all at once.
Table amended
5 bit communication disabled
5 bit communication enabled
0
1
Bit 2
MP Description
(initial value)
10.2.6 Serial Control
Register 3 (SCR3)
344 Description amended
Bit 3—Reserved (MPIE)
It’s a reserved bit.
Table deleted
10.2.7 Serial Status
Register (SSR)
346 Description amended
SSR is an 8-bit register containing status flags that indicate the
operational status of SCI3 .
349 Description amended
Bit 1—Reserved (MPBR)
It’s a reserved read-only bit.
Table deleted
Description amended
Bit 0—Reserved (MPBT)
The write value should always be 0.
Table deleted