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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Configuration of This Manual This manual comprises the following items: 1. General Precautions in the Handling of MPU/MCU Products 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8/38024 Group is a single-chip microcomputer built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. The H8/38024 Group incorporates peripheral functions including ROM, RAM, timer, serial communications interface (SCI), 10-bit PWM, A/D converter, LCD controller/driver, and I/O ports. It is a microcomputer allowing the implementation of a sophisticated control system.
Specifications Memory Operating voltage and operating frequency I/O ports Timers ZTAT Mask Flash 32 Kbytes 8 Kbytes to 32 Kbytes 32 Kbytes RAM 1 Kbyte 512 bytes or 1 Kbyte 1 Kbyte 1 Kbyte 512 bytes or 1 Kbyte 1 Kbyte 512 bytes or 1 Kbyte 4.5 to 5.5 V 16 MHz 16 MHz — — — 20 MHz 20 MHz 2.7 to 5.5 V 10 MHz 10 MHz — — — 20 MHz 20 MHz 1.8 to 5.5 V 4 MHz 4 MHz — — — — — 2.7 to 3.6 V — — 10 MHz 10 MHz 10 MHz — — 1.8 to 3.
Target Readers: This manual is designed for use by people who design application systems using the H8/38024 Group, H8/38024S Group, H8/38024R Group, and H8/38124 Group. To use this manual, basic knowledge of electric circuits, logic circuits and microcomputers is required. Purpose: This manual provides the information of the hardware functions and electrical characteristics of the H8/38024 Group, H8/38024S Group, H8/38024R Group, and H8/38124 Group.
• Application Note Name of Document Document No. H8S, H8/300 Series C/C++ Compiler Package Application Note REJ05B0464 Notes: The following limitations apply to H8/38024, H8/38024R, and H8/38124 programming and debugging when the on-chip emulator is used. 1. Pin 95 is not available because it is used exclusively by the on-chip emulator. 2. Pins 33, 34, and 35 are unavailable for use. In order to use these pins additional hardware must be mounted on the user board. 3.
Contents Section 1 Overview................................................................................................1 1.1 1.2 1.3 Overview................................................................................................................................ 1 Internal Block Diagram.......................................................................................................... 7 Pin Arrangement and Functions...........................................................................
2.8 2.9 2.7.3 Program Halt State.................................................................................................. 59 2.7.4 Exception-Handling State ....................................................................................... 59 Memory Map ....................................................................................................................... 60 2.8.1 Memory Map ........................................................................................................
4.6 Notes on H8/38124 Group ................................................................................................. 119 Section 5 Power-Down Modes ..........................................................................121 5.1 Overview............................................................................................................................ 121 5.1.1 System Control Registers...................................................................................... 124 5.
Section 6 ROM ..................................................................................................145 6.1 Overview............................................................................................................................ 145 6.1.1 Block Diagram ...................................................................................................... 145 6.2 H8/38024 PROM Mode .....................................................................................................
6.10.7 Status Polling ........................................................................................................ 189 6.10.8 Programmer Mode Transition Time...................................................................... 190 6.10.9 Notes on Memory Programming........................................................................... 190 6.11 Power-Down States for Flash Memory.............................................................................. 191 Section 7 RAM .................
8.7 8.8 8.9 8.10 8.11 8.12 8.13 Port 7.................................................................................................................................. 224 8.7.1 Overview............................................................................................................... 224 8.7.2 Register Configuration and Description................................................................ 224 8.7.3 Pin Functions .....................................................................
9.4 9.5 9.6 9.7 9.3.1 Overview............................................................................................................... 255 9.3.2 Register Descriptions ............................................................................................ 257 9.3.3 Timer Operation.................................................................................................... 260 9.3.4 Timer C Operation States.................................................................................
10.2.5 Serial Mode Register (SMR)................................................................................. 339 10.2.6 Serial Control Register 3 (SCR3).......................................................................... 342 10.2.7 Serial Status Register (SSR) ................................................................................. 346 10.2.8 Bit Rate Register (BRR) ....................................................................................... 350 10.2.
12.4 12.5 12.6 12.7 12.3.2 Start of A/D Conversion by External Trigger Input.............................................. 402 12.3.3 A/D Converter Operation Modes .......................................................................... 403 Interrupts ............................................................................................................................ 403 Typical Use ....................................................................................................................
14.3.1 Power-On Reset Circuit ........................................................................................ 439 14.3.2 Low-Voltage Detection Circuit............................................................................. 440 Section 15 Power Supply Circuit (H8/38124 Group Only)...............................447 15.1 When Using Internal Power Supply Step-Down Circuit.................................................... 447 15.2 When Not Using Internal Power Supply Step-Down Circuit...........
16.9 16.10 16.11 16.12 16.8.3 AC Characteristics ................................................................................................ 515 16.8.4 A/D Converter Characteristics .............................................................................. 517 16.8.5 LCD Characteristics.............................................................................................. 518 16.8.6 Flash Memory Characteristics ..............................................................................
Appendix G Specifications of Chip Form .........................................................643 Appendix H Form of Bonding Pads ..................................................................645 Appendix I Specifications of Chip Tray............................................................646 Main Revisions for This Edition .........................................................................649 Rev. 8.00 Mar.
Section 1 Overview Section 1 Overview 1.1 Overview The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip. Within the H8/300L Series, the H8/38024 Group, H8/38024S Group, and H8/38124 Group comprise single-chip microcomputers equipped with a LCD (Liquid Crystal Display) controller/driver.
Section 1 Overview Table 1.1 Features Item Specification CPU High-speed H8/300L CPU • General-register architecture General registers: Sixteen 8-bit registers (can be used as eight 16-bit registers) • Operating speed ⎯ Max. operating speed: 8 MHz (5 MHz for HD64F38024 and H8/38024S Group) ⎯ Add/subtract: 0.25 µs (operating at 8 MHz), 0.4 μs (operating at φ = 5 MHz) ⎯ Multiply/divide: 1.75 µs (operating at 8 MHz), 2.8 μs (operating at φ = 5 MHz) ⎯ Can run on 32.768 kHz or 38.4 kHz subclock (32.
Section 1 Overview Item Specification Clock pulse generators Two on-chip clock pulse generators Power-down modes Memory I/O ports • System clock pulse generator: 1.0 to 16 MHz: H8/38024 Group 1.0 to 10 MHz: HD64F38024, HD64F38024R, and H8/38024S Group 2.0 to 20 MHz: H8/38124 Group • Subclock pulse generator: 32.768 kHz, 38.
Section 1 Overview Item Specification Timers Six on-chip timers • Timer A: 8-bit timer Count-up timer with selection of eight internal clock signals divided from the system clock (φ)* and four clock signals divided from the watch clock (φw)* • Asynchronous event counter: 16-bit timer ⎯ Count-up timer able to count asynchronous external events independently of the MCU's internal clocks Asynchronous external events can be counted (both rising and falling edge detection possible) • Timer C: 8-bit timer
Section 1 Overview Item Specification Serial communication interface • 10-bit PWM Pulse-division PWM output for reduced ripple • A/D converter LCD controller/ driver SCI3: 8-bit synchronous/asynchronous serial interface Can be used as a 10-bit D/A converter by connecting to an external lowpass filter.
Section 1 Overview Item Specification Product lineup Product Code ROM/RAM Size (Byte) Mask ROM Version ZTAT Version F-ZTAT Version Package HD64338024 HD64738024 HD64F38024R HD64F38024 FP-80A FP-80B TFP-80C TLP-85V (HD64F38024R only) Die (mask ROM/F-ZTAT version only) 32K/1K HD64338023 — — FP-80A FP-80B TFP-80C Die 24K/1K HD64338022 — — FP-80A FP-80B TFP-80C Die 16K/1K HD64338021 — — FP-80A FP-80B TFP-80C Die 12K/512 HD64338020 — — FP-80A FP-80B TFP-80C Die 8K/512 HD64338024
Section 1 Overview 1.2 Internal Block Diagram Figure 1.1(1) shows a block diagram of the H8/38024 Group and H8/38024S Group. Figure 1.1(2) shows a block diagram of the H8/38124 Group.
Section 1 Overview System clock OSC 10-bit PWM1 Power-on reset and low-voltage detect circuits P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SEG6 P56/WKP6/SEG7 P57/WKP7/SEG8 P60/SEG9 P61/SEG10 P62/SEG11 P63/SEG12 P64/SEG13 P65/SEG14 P66/SEG15 P67/SEG16 10-bit PWM2 Port 4 P40/SCK32 P41/RXD32 P42/TXD32 P43/IRQ0 Timer A Timer C Timer F Port 5 P30/UD P31/TMOFL P32/TMOFH P33 P34 P35 P36/AEVH P37/AEVL Port 3 P17/IRQ3/TMIF Timer G WDT P77/SEG24 P76/SEG23 P75/SEG22 P
Section 1 Overview 1.3 Pin Arrangement and Functions 1.3.
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 FP-80A,TFP-80C (Top view) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 AVCC P13/TMIG P14/IRQ4/ADTRG CVCC P17/IRQ3/TMIF X1 X2 VSS=AVSS OSC2 OSC1 TEST RES P50/WKP0/SEG1 P51/WKP1/SEG2 P52/WKP2/SEG3 P53/WKP3/SEG4 P54/WKP4/SEG5 P55/WKP5/SE
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P31/TMOFL P30/UD IRQAEC P95 P94 P93 P92 P91/PWM2 P90/PWM1 VSS VCC V1 V2 V3 PA0/COM1 PA1/COM2 PA2/COM3 PA3/COM4 P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 P83/SEG28 P82/SEG27 Section 1 Overview 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 FP-80B (Top view) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P81/SEG26 P80/SEG25 P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 P67/SEG16 P66/SEG15 P65/SEG14
Section 1 Overview A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D8 D9 D10 E1 E2 E3 E8 E9 E10 F1 F2 F3 F8 F9 F10 G1 G2 G3 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 TLP-85V (Top view) Note: Pins are shown in transparent view. Figure 1.4 Pin Arrangement (TLP-85V, H8/38024R Group, H8/38024S Group) Rev. 8.
Section 1 Overview 81 79 80 77 78 75 76 73 74 71 72 69 67 70 68 65 66 63 64 62 Type code 61 1 2 60 59 3 4 58 5 57 6 7 56 Y 8 55 9 54 53 10 (0, 0) 11 52 X 51 12 50 13 49 14 15 48 16 47 17 46 18 45 19 44 20 43 21 42 22 24 23 26 25 28 27 29 30 31 32 33 34 36 35 37 38 40 39 41 Chip size: 3.99 mm × 3.99 mm Voltage level on the back of the chip: GND Figure 1.
Section 1 Overview Table 1.2 Bonding Pad Coordinates of HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 Coordinates Coordinates Pad No. Pad Name X (μm) Y (μm) Pad No.
Section 1 Overview 81 79 80 77 78 75 76 73 71 74 72 69 70 67 68 65 66 64 63 1 2 62 3 61 4 60 5 6 59 7 9 8 58 Y 10 11 13 15 57 12 56 14 (0, 0) 55 X 54 16 53 17 52 18 50 19 20 48 51 49 47 46 21 45 44 Type code 22 43 23 42 24 26 25 27 28 29 30 31 32 34 36 38 33 35 37 40 39 41 Chip size: 3.84 mm × 4.24 mm Voltage level on the back of the chip: GND : NC pad Figure 1.6 Bonding Pad Location Diagram of HCD64F38024, HCD64F38024R (Top View) Rev. 8.00 Mar.
Section 1 Overview Table 1.3 Bonding Pad Coordinates of HCD64F38024, HCD64F38024R Coordinates Coordinates Pad No. Pad Name X (μm) Y (μm) Pad No.
Section 1 Overview 79 80 77 78 75 76 73 74 71 72 69 70 67 68 65 66 63 64 61 62 60 1 59 2 58 3 57 4 56 5 55 6 54 7 Y 8 53 52 9 51 10 (0.0) 11 50 X 49 12 48 13 47 14 46 15 45 16 44 17 43 18 42 19 41 20 22 21 24 23 26 25 28 27 30 29 32 31 34 33 36 35 38 37 40 39 Chip size: 2.91 mm × 2.91 mm Voltage level on the back of the chip: GND Figure 1.
Section 1 Overview Table 1.4 Bonding Pad Coordinates of HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Coordinates Coordinates Pad No. Pad Name X (μm) Y (μm) Pad No.
Section 1 Overview 1.3.2 Pin Functions Table 1.5 outlines the pin functions of the H8/38024 Group. Table 1.5 Pin Functions Pin No. Type Symbol FP-80A TFP-80C FP-80B TLP-85V Pad Pad Pad No.*1 No.*2 No.*3 I/O Power source pins VCC 52 54 53 54 52 Input Power supply: All VCC pins should be connected to the system power supply. VSS 8 (= AVSS) 53 10 D8 (= AVSS) E1 55 (= AVSS) 9 54 10 55 8 53 Input Ground: All VSS pins should be connected to the system power supply (0 V).
Section 1 Overview Pin No. Type Clock pins System control Interrupt pins Symbol FP-80A TFP-80C FP-80B TLP-85V Pad Pad Pad No.*1 No.*2 No.*3 I/O Name and Functions These pins connect to a crystal or ceramic oscillator, or can be used to input an external clock. See section 4, Clock Pulse Generators, for a typical connection diagram.
Section 1 Overview Pin No. FP-80A TFP-80C FP-80B TLP-85V Pad Pad Pad No.*1 No.*2 No.*3 I/O Name and Functions Type Symbol Interrupt pins WKP7 to 20 to 13 WKP0 22 to 15 H1, J1, H3, G1, H2, G2, F2, G3 21 to 22 to 14 15 20 to 13 Input Wakeup interrupt request 7 to 0: These are input pins for rising or falling-edge-sensitive external interrupts.
Section 1 Overview Pin No. FP-80A TFP-80C FP-80B TLP-85V Pad Pad Pad No.*1 No.*2 No.*3 I/O 10-bit PWM1 PWM pin PWM2 54 55 56 57 E10 D9 55 56 56 57 54 55 Output 10-bit PWM output: These are output pins for waveforms generated by the channel 1 and 2 10-bit PWMs. I/O ports 5 4 3 2 7 6 5 4 D1 C2 B2 C1 5 4 3 2 6 5 4 3 5 4 3 2 I/O Type Symbol P17 P16 P14 P13 Name and Functions Port 1: This is a 4-bit I/O port.
Section 1 Overview Pin No. FP-80A TFP-80C FP-80B TLP-85V Pad Pad Pad No.*1 No.*2 No.*3 I/O P77 to P70 36 to 29 38 to 41 J8, J7 K6, H7 H6, J7 H6, J5 J6, H5 37 to 38 to 30 31 36 to 29 I/O Port 7: This is an 8-bit I/O port. Input or output can be designated for each bit by means of port control register 7 (PCR7). P87 to P80 44 to 37 46 to 39 H9, J9 H10, J10 K8, K9 H8, K7 45 to 46 to 38 39 44 to 37 I/O Port 8: This is an 8-bit I/O port.
Section 1 Overview Pin No. Type Symbol A/D ADTRG converter FP-80A TFP-80C FP-80B TLP-85V Pad Pad Pad No.*1 No.*2 No.*3 I/O 3 3 3 Input 46 to 47 to 49 50 45 to 48 Output LCD common output: These are the LCD common output pins. SEG32 to 44 to 13 SEG1 45 to 46 to 46 to 15 H9, J9, 15 H10, J10, 14 K8, K9, H8, K7, J8, J7, K6, H7, H6, J5, J6, H5, K5, J4, H4, K4, J3, J2, K3, K2, H1, J1, H3, G1, H2, G2, F1, G3 44 to 13 Output LCD segment output: These are the LCD segment output pins.
Section 2 CPU Section 2 CPU 2.1 Overview The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit registers. Its concise instruction set is designed for high-speed operation. 2.1.1 Features Features of the H8/300L CPU are listed below.
Section 2 CPU 2.1.2 Address Space The H8/300L CPU supports an address space of up to 64 Kbytes for storing program code and data. See section 2.8, Memory Map, for details of the memory map. 2.1.3 Register Configuration Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the general registers and control registers.
Section 2 CPU 2.2 Register Descriptions 2.2.1 General Registers All the general registers can be used as both data registers and address registers. When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes (R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers. When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
Section 2 CPU Condition Code Register (CCR) This 8-bit register contains internal status information, including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for conditional branching (Bcc) instructions. Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked.
Section 2 CPU 2.2.3 Initial Register Values When the CPU is reset, the program counter (PC) is initialized to the value stored at address H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be initialized by software, by the first instruction executed after a reset. 2.
Section 2 CPU 2.3.1 Data Formats in General Registers Data of all the sizes above can be stored in general registers as shown in figure 2.3. Data Type Register No.
Section 2 CPU 2.3.2 Memory Data Formats Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored in memory (MOV.W instruction), but the word data must always begin at an even address. If word data starting at an odd address is accessed, the least significant bit of the address is regarded as 0, and the word data starting at the preceding address is accessed. The same applies to instruction codes.
Section 2 CPU 2.4 Addressing Modes 2.4.1 Addressing Modes The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a subset of these addressing modes. Table 2.1 Addressing Modes No.
Section 2 CPU Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn: • Register indirect with post-increment—@Rn+ The @Rn+ mode is used with MOV instructions that load registers from memory. The register field of the instruction specifies a 16-bit general register containing the address of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
Section 2 CPU The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the address area is also used as a vector area. See section 3.3, Interrupts, for details on the vector area. If an odd address is specified as a branch destination or as the operand address of a MOV.
4 3 rm op 7 6 rm 4 3 4 3 rn 0 0 op disp 7 6 rm op 7 6 rm 4 3 4 3 0 0 15 op 7 6 rm 4 3 0 Register indirect with pre-decrement, @−Rn 15 Register indirect with post-increment, @Rn+ 15 Register indirect with displacement, @(d:16, Rn) 15 Register indirect, @Rn 8 7 0 0 0 Contents (16 bits) of register indicated by rm 0 1 or 2 Contents (16 bits) of register indicated by rm disp Contents (16 bits) of register indicated by rm Contents (16 bits) of register indicated by rm
Rev. 8.00 Mar. 09, 2010 Page 36 of 658 REJ09B0042-0800 7 6 5 No.
8 7 [Legend] rm, rn: Register field Operation field op: disp: Displacement IMM: Immediate data abs: Absolute address op abs Memory indirect, @@aa:8 8 15 Addressing Mode and Instruction Format No. 0 15 8 7 abs Memory contents (16 bits) H'00 0 Effective Address Calculation Method 15 Effective Address (EA) 0 Section 2 CPU Rev. 8.00 Mar.
Section 2 CPU 2.5 Instruction Set The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3. Table 2.
Section 2 CPU Notation Rd General register (destination) Rs General register (source) Rn General register (EAd), Destination operand (EAs), Source operand CCR Condition code register N N (negative) flag of CCR Z Z (zero) flag of CCR V V (overflow) flag of CCR C C (carry) flag of CCR PC Program counter SP Stack pointer #IMM Immediate data disp Displacement + Addition – Subtraction × Multiplication ÷ Division ∧ AND logical ∨ OR logical ⊕ Exclusive OR logica
Section 2 CPU 2.5.1 Data Transfer Instructions Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats. Table 2.4 Data Transfer Instructions Instruction Size* Function MOV B/W (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+ addressing modes are available for word data.
Section 2 CPU 15 8 7 0 op rm 15 8 rn 0 rm 8 Rm→Rn 7 op 15 MOV rn @Rm←→Rn 7 0 op rm rn @(d:16, Rm)←→Rn disp 15 8 7 0 op rm 15 8 op 7 0 rn 15 @Rm+→Rn, or Rn →@−Rm rn abs 8 @aa:8←→Rn 7 0 op rn @aa:16←→Rn abs 15 8 op 7 0 rn 15 IMM 8 #xx:8→Rn 7 0 op rn #xx:16→Rn IMM 15 8 op 7 0 1 1 1 rn PUSH, POP @SP+ → Rn, or Rn → @−SP [Legend] op: Operation field rm, rn: Register field disp: Displacement abs: Absolute address IMM: Immediate data Figure 2.
Section 2 CPU 2.5.2 Arithmetic Operations Table 2.5 describes the arithmetic instructions. Table 2.5 Arithmetic Instructions Instruction Size* Function ADD B/W Rd ± Rs → Rd, Rd + #IMM → Rd SUB Performs addition or subtraction on data in two general registers, or addition on immediate data and data in a general register. Immediate data cannot be subtracted from data in a general register. Word data can be added or subtracted only when both words are in general registers.
Section 2 CPU 2.5.3 Logic Operations Table 2.6 describes the four instructions that perform logic operations. Table 2.
Section 2 CPU 2.5.4 Shift Operations Table 2.7 describes the eight shift instructions. Table 2.
Section 2 CPU Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
Section 2 CPU 2.5.5 Bit Manipulations Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats. Table 2.8 Bit-Manipulation Instructions Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory to 0.
Section 2 CPU Instruction Size* Function BXOR B C ⊕ ( of ) → C XORs the C flag with a specified bit in a general register or memory, and stores the result in the C flag. BIXOR B C ⊕ [~( of )] → C XORs the C flag with the inverse of a specified bit in a general register or memory, and stores the result in the C flag. The bit number is specified by 3-bit immediate data. BLD B ( of ) → C Copies a specified bit in a general register or memory to the C flag.
Section 2 CPU BSET, BCLR, BNOT, BTST 15 8 7 op 0 IMM 15 8 7 op 0 rm 15 8 Operand: register direct (Rn) Bit No.: immediate (#xx:3) rn Operand: register direct (Rn) Bit No.: register direct (Rm) rn 7 op 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit No.: op rn 0 0 0 0 Operand: register indirect (@Rn) op rm 0 0 0 0 Bit No.: op 15 8 15 8 7 0 7 abs IMM 15 8 0 Operand: absolute (@aa:8) 0 0 7 0 Bit No.
Section 2 CPU BIAND, BIOR, BIXOR, BILD, BIST 15 8 7 op 0 IMM 15 8 7 op op 15 8 Operand: register direct (Rn) Bit No.: immediate (#xx:3) rn 0 rn 0 0 0 0 Operand: register indirect (@Rn) IMM 0 0 0 0 Bit No.: 7 0 op abs op immediate (#xx:3) IMM 0 Operand: absolute (@aa:8) 0 0 0 Bit No.: immediate (#xx:3) [Legend] op: Operation field rm, rn: Register field abs: Absolute address IMM: Immediate data Figure 2.7 Bit Manipulation Instruction Codes (cont) Rev. 8.00 Mar.
Section 2 CPU 2.5.6 Branching Instructions Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats. Table 2.9 Branching Instructions Instruction Size Function Bcc — Branches to the designated address if condition cc is true. The branching conditions are given below.
Section 2 CPU 15 8 op 7 0 cc 15 disp 8 7 op 0 rm 15 Bcc 8 0 0 0 7 0 JMP (@Rm) 0 op JMP (@aa:16) abs 15 8 7 0 op abs 15 8 JMP (@@aa:8) 7 0 op disp 15 8 7 op 0 rm 15 BSR 8 0 0 0 7 0 JSR (@Rm) 0 op JSR (@aa:16) abs 15 8 7 op 0 abs 15 8 7 JSR (@@aa:8) 0 op RTS [Legend] op: Operation field cc: Condition field rm: Register field disp: Displacement abs: Absolute address Figure 2.8 Branching Instruction Codes Rev. 8.00 Mar.
Section 2 CPU 2.5.7 System Control Instructions Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats. Table 2.10 System Control Instructions Instruction Size* Function RTE — Returns from an exception-handling routine SLEEP — Causes a transition from active mode to a power-down mode. See section 5, Power-Down Modes, for details.
Section 2 CPU 15 8 7 0 op 15 8 RTE, SLEEP, NOP 7 0 op 15 rn 8 7 LDC, STC (Rn) 0 op IMM ANDC, ORC, XORC, LDC (#xx:8) [Legend] op: Operation field rn: Register field IMM: Immediate data Figure 2.9 System Control Instruction Codes 2.5.8 Block Data Transfer Instruction Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format. Table 2.
Section 2 CPU 15 8 7 op op [Legend] op: Operation field Figure 2.10 Block Data Transfer Instruction Code Rev. 8.00 Mar.
Section 2 CPU 2.6 Basic Operational Timing CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). For details on these clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φSUB to the next rising edge is called one state. A bus cycle consists of two states or three states. The cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules. 2.6.
Section 2 CPU 2.6.2 Access to On-Chip Peripheral Modules On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits, so access is by byte size only. This means that for accessing word data, two instructions must be used. Figures 2.12 and 2.13 show the on-chip peripheral module access cycle.
Section 2 CPU Three-state access to on-chip peripheral modules Bus cycle T1 state T2 state T3 state φ or φSUB Internal address bus Address Internal read signal Internal data bus (read access) Read data Internal write signal Internal data bus (write access) Write data Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access) 2.7 CPU States 2.7.1 Overview There are four CPU states: the reset state, program execution state, program halt state, and exception-handling state.
Section 2 CPU CPU state Reset state The CPU is initialized Program execution state Active (high speed) mode The CPU executes successive program instructions at high speed, synchronized by the system clock Active (medium speed) mode The CPU executes successive program instructions at reduced speed, synchronized by the system clock Subactive mode The CPU executes successive program instructions at reduced speed, synchronized by the subclock Program halt state A state in which some or all of the chip funct
Section 2 CPU Reset cleared Reset state Exception-handling state Reset occurs Reset occurs Reset occurs Interrupt source occurs Program halt state Interrupt source occurs Exceptionhandling complete Program execution state SLEEP instruction executed Figure 2.15 State Transitions 2.7.2 Program Execution State In the program execution state the CPU executes program instructions in sequence. There are three modes in this state, two active modes (high speed and medium speed) and one subactive mode.
Section 2 CPU 2.8 Memory Map 2.8.1 Memory Map The memory map of the H8/38024, H8/38024S, and H8/38124 are shown in figure 2.16(1), that of the H8/38023, H8/38023S, and H8/38123 in figure 2.16(2), that of the H8/38022, H8/38022S, and H8/38122 in figure 2.16(3), that of the H8/38021, H8/38021S, and H8/38121 in figure 2.16(4), and that of the H8/38020, H8/38020S, and H8/38120 in figure 2.16(5). Rev. 8.00 Mar.
Section 2 CPU HD64F38024, HD64F38024R, HD64F38124 (flash memory version) H'0000 HD64338024 (mask ROM version) HD64338024S (mask ROM version) HD64338124 (mask ROM version) HD64738024 (PROM version) H'0000 Interrupt vector area Interrupt vector area H'0029 H'0029 H'002A H'002A On-chip ROM 32 Kbytes (32768 bytes) 32 Kbytes (32768 bytes) On-chip ROM H'7000 Firmware for on-chip emulator*1 H'7FFF H'7FFF Not used H'F020 H'F02B Not used Internal I/O register Not used H'F740 H'F740 H'F74F LCD RAM
Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 24 Kbytes On-chip ROM (24576 bytes) H'5FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FB80 On-chip RAM 1024 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(2) H8/38023, H8/38023S, and H8/38123 Memory Map Rev. 8.00 Mar.
Section 2 CPU Flash memory version Mask ROM version H'0000 H'0000 Interrupt vector area Interrupt vector area H'0029 H'0029 H'002A H'002A On-chip ROM On-chip ROM 16 Kbytes (16384 bytes) H'3FFF 16 Kbytes (16384 bytes) H'3FFF Not used H'7000 Firmware for on-chip emulator H'7FFF Not used Not used H'F020 H'F02B Internal I/O register Not used H'F740 H'F740 H'F74F LCD RAM (16 bytes) H'F74F LCD RAM (16 bytes) Not used H'F780 H'FB7F H'FB80 Not used (Workarea for reprogramming flash memory: 1
Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 12 Kbytes On-chip ROM (12288 bytes) H'2FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FD80 On-chip RAM 512 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(4) H8/38021, H8/38021S, and H8/38121 Memory Map Rev. 8.00 Mar.
Section 2 CPU H'0000 Interrupt vector area H'0029 H'002A 8 Kbytes On-chip ROM (8192 bytes) H'1FFF Not used H'F740 LCD RAM (16 bytes) H'F74F Not used H'FD80 On-chip RAM 512 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FFFF Figure 2.16(5) H8/38020, H8/38020S, and H8/38120 Memory Map Rev. 8.00 Mar.
Section 2 CPU 2.9 Application Notes 2.9.1 Notes on Data Access 1. Access to Empty Areas: The address space of the H8/300L CPU includes empty areas in addition to the RAM, registers, and ROM areas available to the user. If these empty areas are mistakenly accessed by an application program, the following results will occur. Data transfer from CPU to empty area: The transferred data will be lost. This action may also cause the CPU to misoperate.
Section 2 CPU Access States Word Byte H'0000 H'0029 Interrupt vector area (42 bytes) H'002A 2 32 Kbytes On-chip ROM *1 H'7FFF ⎯ Not used H'F020 H'F02B × Internal I/O registers*3 ⎯ Not used H'F740 H'F74F H'FB7F *2 H'FB80 ⎯ ⎯ 2 ⎯ (1-Kbyte work area for flash memory programming)*3 Internal RAM User Area ⎯ 2 LCD RAM (16 bytes) Not used H'F780 ⎯ ⎯ ⎯ 2 2 1024 bytes H'FF7F H'FF80 Internal I/O registers (128 bytes) H'FF98 to H'FF9F H'FFA8 to H'FFAF H'FFFF × × × × × 2 3 2 3 2 Notes: T
Section 2 CPU 2.9.2 Notes on Bit Manipulation The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data, then write the data byte again. Special care is required when using these instructions in cases where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port.
Section 2 CPU Example 2: BSET instruction executed designating port 3 P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P31, are output pins and output low-level signals. In this example, the BSET instruction is used to change pin P30 to high-level output.
Section 2 CPU To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PDR3. [A: Prior to executing BSET] MOV. B MOV. B MOV.
Section 2 CPU 2. Bit manipulation in a register containing a write-only bit Example 3: BCLR instruction executed designating port 3 control register PCR3 As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is assumed that a high-level signal will be input to this input pin.
Section 2 CPU To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit manipulation on the data in the work area, then write this data to PCR3. [A: Prior to executing BCLR] MOV. B MOV. B MOV. B #3F, R0L, R0L, P37 Input/output Input The PCR3 value (H'3F) is written to a work area in memory (RAM0) as well as to PCR3.
Section 2 CPU Table 2.12 Registers with Shared Addresses Register Name Abbreviation Address Timer counter C/Timer load register C Port data register 1* TCC/TLC H'FFB5 PDR1 H'FFD4 Port data register 3* PDR3 H'FFD6 Port data register 4* PDR4 H'FFD7 Port data register 5* PDR5 H'FFD8 Port data register 6* Port data register 7* PDR6 H'FFD9 PDR7 H'FFDA Port data register 8* PDR8 H'FFDB Port data register A* PDRA H'FFDD Note: * Port data registers have the same addresses as input pins.
Section 2 CPU 2.9.3 Notes on Use of the EEPMOV Instruction • The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes specified by R4L from the address specified by R5 to the address specified by R6. R5 → ← R6 R5 + R4L → ← R6 + R4L • When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of the instruction.
Section 3 Exception Handling Section 3 Exception Handling 3.1 Overview Exception handling is performed in the H8/38024 Group, H8/38024S Group, H8/38024F-ZTAT Group, and H8/38124 Group when a reset or interrupt occurs. Table 3.1 shows the priorities of these two types of exception handling. Table 3.
Section 3 Exception Handling When system power is turned on or off, the RES pin should be held low. Figure 3.1 shows the reset sequence starting from RES input. See section 14.3.1, Power-On Reset Circuit, for information on the reset sequence for the H8/38124 Group, which is equipped with an on-chip power-on reset circuit.
Section 3 Exception Handling 3.3 Interrupts 3.3.1 Overview The interrupt sources include 13 external interrupts (WKP7 to WKP0, IRQ4, IRQ3, IRQ1, IRQ0, IRQAEC) and 9 internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with the highest priority is processed.
Section 3 Exception Handling Table 3.
Section 3 Exception Handling 3.3.2 Interrupt Control Registers Table 3.3 lists the registers that control interrupts. Table 3.
Section 3 Exception Handling Bit 4—IRQ4 Edge Select (IEG4) Bit 4 selects the input sensing of the IRQ4 pin and ADTRG pin. Bit 4 IEG4 Description 0 Falling edge of IRQ4 and ADTRG pin input is detected 1 Rising edge of IRQ4 and ADTRG pin input is detected (initial value) Bit 3—IRQ3 Edge Select (IEG3) Bit 3 selects the input sensing of the IRQ3 pin and TMIF pin.
Section 3 Exception Handling Interrupt Enable Register 1 (IENR1) Bit 7 6 5 4 3 2 1 0 IENTA ⎯ IENWP IEN4 IEN3 IENEC2 IEN1 IEN0 Initial value 0 ⎯ 0 0 0 0 0 0 Read/Write R/W W R/W R/W R/W R/W R/W R/W IENR1 is an 8-bit read/write register that enables or disables interrupt requests. Bit 7—Timer A Interrupt Enable (IENTA) Bit 7 enables or disables timer A overflow interrupt requests.
Section 3 Exception Handling Bit 2—IRQAEC Interrupt Enable (IENEC2) Bit 2 enables or disables IRQAEC interrupt requests. Bit 2 IENEC2 Description 0 Disables IRQAEC interrupt requests 1 Enables IRQAEC interrupt requests (initial value) Bits 1 and 0—IRQ1 and IRQ0 Interrupt Enable (IEN1 and IEN0) Bits 1 and 0 enable or disable IRQ1 and IRQ0 interrupt requests.
Section 3 Exception Handling Bit 6—A/D Converter Interrupt Enable (IENAD) Bit 6 enables or disables A/D converter interrupt requests. Bit 6 IENAD Description 0 Disables A/D converter interrupt requests 1 Enables A/D converter interrupt requests (initial value) Bit 5—Reserved Bit 5 is reserved bit: it can only be written with 0. Bit 4—Timer G Interrupt Enable (IENTG) Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Section 3 Exception Handling Bit 1—Timer C Interrupt Enable (IENTC) Bit 1 enables or disables timer C overflow and underflow interrupt requests. Bit 1 IENTC Description 0 Disables timer C interrupt requests 1 Enables timer C interrupt requests (initial value) Bit 0—Asynchronous Event Counter Interrupt Enable (IENEC) Bit 0 enables or disables asynchronous event counter interrupt requests.
Section 3 Exception Handling Bit 7—Timer A Interrupt Request Flag (IRRTA) Bit 7 IRRTA Description 0 Clearing condition: When IRRTA = 1, it is cleared by writing 0 1 Setting condition: When the timer A counter value overflows (initial value) Bit 6—Reserved Bit 6 is reserved; it can only be written with 0. Bit 5—Reserved Bit 5 is reserved; it is always read as 1 and cannot be modified.
Section 3 Exception Handling Bits 1 and 0—IRQ1 and IRQ0 Interrupt Request Flags (IRRI1 and IRRI0) Bit n IRRIn Description 0 Clearing condition: When IRRIn = 1, it is cleared by writing 0 (initial value) 1 Setting condition: When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 1 or 0) Interrupt Request Register 2 (IRR2) Bit 7 6 5 4 3 2 1 0 IRRDT IRRAD ⎯ IRRTG IRRTC IRREC Initial value 0 0 ⎯ 0 0 0 0 0 Read/Write R/(W)* R/(W)* W R/(W)*
Section 3 Exception Handling Bit 6—A/D Converter Interrupt Request Flag (IRRAD) Bit 6 IRRAD Description 0 Clearing condition: When IRRAD = 1, it is cleared by writing 0 (initial value) 1 Setting condition: When A/D conversion is completed and ADSF is cleared to 0 in ADSR Bit 5—Reserved Bit 5 is reserved: it can only be written with 0.
Section 3 Exception Handling Bit 2—Timer FL Interrupt Request Flag (IRRTFL) Bit 2 IRRTFL Description 0 Clearing condition: When IRRTFL = 1, it is cleared by writing 0 1 Setting condition: When TCFL and OCRFL match in 8-bit timer mode (initial value) Bit 1—Timer C Interrupt Request Flag (IRRTC) Bit 1 IRRTC Description 0 Clearing condition: When IRRTC = 1, it is cleared by writing 0 1 Setting condition: When the timer C counter value overflows or underflows (initial value) Bit 0—Asynchronous Ev
Section 3 Exception Handling Wakeup Interrupt Request Register (IWPR) Bit 7 6 5 4 3 2 1 0 IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only a write of 0 for flag clearing is possible IWPR is an 8-bit read/write register containing wakeup interrupt request flags.
Section 3 Exception Handling Wakeup Edge Select Register (WEGR) Bit 7 6 5 4 3 2 1 0 WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn. WEGR is initialized to H'00 by a reset. Bit n—WKPn Edge Select (WKEGSn) Bit n selects WKPn pin input sensing.
Section 3 Exception Handling Interrupts IRQ4, IRQ3, IRQ1 and IRQ0 Interrupts IRQ4, IRQ3, IRQ1, and IRQ0 are requested by input signals to pins IRQ4, IRQ3, IRQ1, and IRQ0. These interrupts are detected by either rising edge sensing or falling edge sensing, depending on the settings of bits IEG4, IEG3, IEG1, and IEG0 in IEGR.
Section 3 Exception Handling 3.3.5 Interrupt Operations Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance. Priority decision logic Interrupt controller External or internal interrupts Interrupt request External interrupts or internal interrupt enable signals I CCR (CPU) Figure 3.2 Block Diagram of Interrupt Controller Interrupt operation is described as follows.
Section 3 Exception Handling • If the interrupt request is accepted, after processing of the current instruction is completed, both PC and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4. The PC value pushed onto the stack is the address of the first instruction to be executed upon return from interrupt handling. • The I bit of CCR is set to 1, masking further interrupts.
Section 3 Exception Handling Program execution state IRRI0 = 1 No Yes IEN0 = 1 No Yes IRRI1 = 1 No Yes IEN1 = 1 Yes No IRREC2 = 1 No Yes IENEC2 = 1 No Yes IRRDT = 1 No Yes IENDT = 1 Yes No I=0 Yes PC contents saved CCR contents saved I←1 Branch to interrupt handling routine [Legend] PC: Program counter CCR: Condition code register I bit of CCR I: Figure 3.3 Flow up to Interrupt Acceptance Rev. 8.00 Mar.
Section 3 Exception Handling SP − 4 SP (R7) CCR SP − 3 SP + 1 CCR* SP − 2 SP + 2 PCH SP − 1 SP + 3 PCL SP (R7) SP + 4 Even address Stack area Prior to start of interrupt exception handling PC and CCR saved to stack After completion of interrupt exception handling [Legend] PCH: Upper 8 bits of program counter (PC) Lower 8 bits of program counter (PC) PCL: CCR: Condition code register Stack pointer SP: Notes: 1.
Rev. 8.00 Mar. 09, 2010 Page 96 of 658 REJ09B0042-0800 Internal data bus (16 bits) Internal write signal Internal read signal Internal address bus φ Interrupt request signal Figure 3.5 Interrupt Sequence (4) Instruction prefetch (3) Internal processing (5) (1) Stack access (6) (7) (9) Vector fetch (8) (10) (9) Prefetch instruction of Internal interrupt-handling routine processing (1) Instruction prefetch address (Instruction is not executed.
Section 3 Exception Handling 3.3.6 Interrupt Response Time Table 3.4 shows the number of wait states after an interrupt request flag is set until the first instruction of the interrupt handler is executed. Table 3.4 Interrupt Wait States Item States Total Waiting time for completion of executing instruction* 1 to 13 15 to 27 Saving of PC and CCR to stack 4 Vector fetch 2 Instruction fetch 4 Internal processing 4 Note: * Not including EEPMOV instruction. Rev. 8.00 Mar.
Section 3 Exception Handling 3.4 Application Notes 3.4.1 Notes on Stack Area Use When word data is accessed in the LSI, the least significant bit of the address is regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7) should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W @SP+, Rn) to save or restore register values. Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
Section 3 Exception Handling 3.4.2 Notes on Rewriting Port Mode Registers When a port mode register is rewritten to switch the functions of external interrupt pins and when the value of ECPWME in AEGSR is rewritten to switch between selection/non-selection of IRQAEC, the following points should be observed.
Section 3 Exception Handling Interrupt Request Flags Set to 1 IWPR IWPF7 Conditions When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low and WEGR bit WKEGS7 = 0. When PMR5 bit WKP7 is changed from 1 to 0 while pin WKP7 is low and WEGR bit WKEGS7 = 1. IWPF6 When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low and WEGR bit WKEGS6 = 0. When PMR5 bit WKP6 is changed from 1 to 0 while pin WKP6 is low and WEGR bit WKEGS6 = 1.
Section 3 Exception Handling executed immediately after the port mode register (or AEGSR) access without executing an intervening instruction, the flag will not be cleared. An alternative method is to avoid the setting of interrupt request flags when pin functions are switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur. However, the procedure in Figure 3.7 is recommended because IECPWM is an internal signal and determining its value is complicated.
Section 3 Exception Handling • Example of a malfunction When flags are cleared with multiple instructions, other flags might be cleared during execution of the instructions, even though they are currently set, and this will cause a malfunction. Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1 (bit 1 of IRR1). MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time AND.B #B'11111101,R1L ..... Here, IRRI0 = 1 MOV.B R1L,@IRR1:8 .........
Section 4 Clock Pulse Generators Section 4 Clock Pulse Generators 4.1 Overview Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a system clock pulse generator and a subclock pulse generator. The system clock pulse generator consists of a system clock oscillator and system clock dividers. The subclock pulse generator consists of a subclock oscillator circuit and a subclock divider.
Section 4 Clock Pulse Generators Internal reset signal (other than watchdog timer or low-voltage detect circuit reset) C IRQAEC OSC1 OSC2 D Latch Q System clock oscillator On-chip oscillator φOSC (fOSC) φOSC/2 System clock divider (1/2) System clock divider ROSC φOSC/16 φOSC/32 φOSC/64 φOSC/128 φ Prescaler S (13 bits) φ/2 to φ/8192 System clock pulse generator φW φW/2 X1 X2 Subclock oscillator φW (fW) Subclock divider (1/2, 1/4, 1/8) φW/4 φW/8 Subclock pulse generator φSUB φW/2 φW/4
Section 4 Clock Pulse Generators 4.1.3 Register Descriptions Table 4.1 lists the registers that control the clock pulse generators. The registers listed in table 4.1 are only implemented in the H8/38124 Group. Table 4.
Section 4 Clock Pulse Generators Bit 2—IRQAEC Flag (IRQAECF) This bit indicates the IRQAEC pin input level set during resets. Bit 2 IRQAECF Description 0 IRQAEC pin set to GND during resets 1 IRQAEC pin set to VCC during resets Bit 1—OSC Flag (OSCF) This bit indicates the oscillator operating with the system clock pulse generator.
Section 4 Clock Pulse Generators C1 R f = 1 MΩ ±20% OSC1 Rf OSC2 C2 Frequency Crystal oscillator C1, C2 Recommendation value 4.19 MHz NDK 12 pF ±20% Note: Circuit constants should be determined in consultation with the resonator manufacturer. Figure 4.3(1) Typical Connection to Crystal Oscillator (H8/38024, H8/38024R Group) C1 R f = 1 MΩ ±20% OSC1 Rf C2 OSC2 Frequency Crystal oscillator 4.
Section 4 Clock Pulse Generators Table 4.2 Crystal Oscillator Parameters Frequency (MHz) 4 4.193 RS max (Ω) 100 100 C0 max (pF) 16 16 Connecting a Ceramic Oscillator Figure 4.5(1) shows a typical method of connecting a ceramic oscillator to the H8/38024 or H8/38024R Group, and figure 4.5(2) shows a typical method of connecting a crystal oscillator to the H8/38024S and H8/38124 Group. OSC 2 R f = 1 MΩ ±20% C1 OSC 1 Rf Frequency Ceramic oscillator C1, C2 Recommendation value 4.
Section 4 Clock Pulse Generators Notes on Board Design When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention to the following points. Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely affected by induction currents. (See figure 4.6.) The board should be designed so that the oscillator and load capacitors are located as close as possible to pins OSC1 and OSC2.
Section 4 Clock Pulse Generators External Clock Input Method Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.7 shows a typical connection. OSC1 External clock input OSC2 Open Figure 4.7 External Clock Input (Example) Frequency Oscillator Clock (φOSC) Duty cycle 45% to 55% On-Chip Oscillator Selection Method (H8/38124 Group Only) The on-chip oscillator is selected by setting the IRQAEC pin input level during resets.* Table 4.
Section 4 Clock Pulse Generators 4.3 Subclock Generator Connecting a 32.768 kHz/38.4 kHz Crystal Oscillator Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz/38.4 kHz crystal oscillator, as shown in figure 4.8. Follow the same precautions as noted under 3. notes on board design for the system clock in section 4.2. Note that only operation at 32.768 kHz is guaranteed on the H8/38124 Group. C1 X1 X2 C2 C1 = C 2 = 15 pF (typ.) Frequency Crystal oscillator 38.
Section 4 Clock Pulse Generators Pin Connection when Not Using Subclock When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in figure 4.10. X1 GND X2 Open Figure 4.10 Pin Connection when not Using Subclock External Clock Input Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4.11. Note that no external clock should be input to the H8/38124 Group. X1 X2 External clock input Open Figure 4.
Section 4 Clock Pulse Generators Frequency Subclock (φw) Duty 45% to 55% Method for Disabling Subclock Oscillator (H8/38124 Group Only) The subclock oscillator can be disabled by programs by setting the SUBSTP bit in the OSCCR register to 1. The register setting to disable the subclock oscillator should be made in the active mode.
Section 4 Clock Pulse Generators Prescaler W (PSW) Prescaler W is a 5-bit counter using a 32.768 kHz/38.4 kHz signal divided by 4 (φW/4) as its input clock. Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state. Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues functioning so long as clock signals are supplied to pins X1 and X2. Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Section 4 Clock Pulse Generators 4.5 Note on Oscillators Oscillator characteristics are closely related to board design and should be carefully evaluated by the user in mask ROM and ZTAT versions, referring to the examples shown in this section. Oscillator circuit constants will differ depending on the oscillator element, stray capacitance in its interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the oscillator element manufacturer.
Section 4 Clock Pulse Generators Modification point OSC1 OSC1 C1 C1 Rf Rf OSC2 OSC2 C2 C2 Negative resistance, addition of −R (1) Negative Resistance Measuring Circuit (2) Oscillator Circuit Modification Suggestion 1 Modification point Modification point C3 OSC1 C1 OSC1 C1 Rf C2 Rf OSC2 OSC2 (3) Oscillator Circuit Modification Suggestion 2 C2 (4) Oscillator Circuit Modification Suggestion 3 Figure 4.13 Negative Resistance Measurement and Circuit Modification Suggestions 4.5.
Section 4 Clock Pulse Generators 1. Oscillation stabilization time (trc) The time from the point at which the system clock oscillator oscillation waveform starts to change when an interrupt is generated, until the amplitude of the oscillation waveform increases and the oscillation frequency stabilizes. 2. Wait time The time required for the CPU and peripheral functions to begin operating after the oscillation waveform frequency and system clock have stabilized.
Section 4 Clock Pulse Generators amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is, the oscillation stabilization time—is required.
Section 4 Clock Pulse Generators For example, if erroneous operation occurs with a wait time setting of 16 states, check the operation with a wait time setting of 1,024* states or more. If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES pin low for a longer period. Note: * This figure applies to the H8/38024, H8/38024S, and H8/38024R Groups. The number of states on the H8/38124 Group is 8,192 or more. 4.5.
Section 4 Clock Pulse Generators Rev. 8.00 Mar.
Section 5 Power-Down Modes Section 5 Power-Down Modes 5.1 Overview The LSI has nine modes of operation after a reset. These include eight power-down modes, in which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating modes. Table 5.
Section 5 Power-Down Modes Program execution state Reset state SLEEP instruction*a Active (high-speed) mode P EE n SL uctio r t s in *d Program halt state Program halt state a SLEEP instruction*f SL instr EEP uctio *d n *1 SLEEP instruction*e Watch mode *1 SLEEP instruction*i *e P EE tion SL ruc st in Subactive mode P * EE tion SL ruc st inin SL st E ru EP ct io n *b SLEEP instruction*b *3 Sleep (medium-speed) mode ins SLEE tru P cti on *j S ins LE tru EP ctio n *i Active (medium-spee
Section 5 Power-Down Modes Table 5.
Section 5 Power-Down Modes 11. On the H8/38124 Group, operates only when the on-chip oscillator is selected; otherwise stops and stands by. On the H8/38024, H8/38024S, and H8/38024R Group, stops and stands by. 5.1.1 System Control Registers The operation mode is selected using the system control registers described in table 5.3. Table 5.
Section 5 Power-Down Modes Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0) These bits designate the time the CPU and peripheral modules wait for stable clock operation after exiting from standby mode or watch mode to active mode due to an interrupt. The designation should be made according to the operating frequency so that the waiting time is at least equal to the oscillation stabilization time.
Section 5 Power-Down Modes Bit 3—Low Speed on Flag (LSON) This bit chooses the system clock (φ) or subclock (φSUB) as the CPU operating clock when watch mode is cleared. The resulting operation mode depends on the combination of other control bits and interrupt input. Bit 3 LSON Description 0 The CPU operates on the system clock (φ) 1 The CPU operates on the subclock (φSUB) (initial value) Bit 2—Reserved Bit 2 is reserved: it is always read as 1 and cannot be modified.
Section 5 Power-Down Modes Bit 4—Noise Elimination Sampling Frequency Select (NESEL) This bit selects the frequency at which the watch clock signal (φW) generated by the subclock pulse generator is sampled, in relation to the oscillator clock (φOSC) generated by the system clock pulse generator. When φOSC = 2 to 20 MHz, clear NESEL to 0.
Section 5 Power-Down Modes Bit 2 MSON Description 0 Operation in active (high-speed) mode 1 Operation in active (medium-speed) mode (initial value) Bits 1 and 0—Subactive Mode Clock Select (SA1, SA0) These bits select the CPU clock rate (φW/2, φW/4, or φW/8) in subactive mode. SA1 and SA0 cannot be modified in subactive mode. Bit 1 SA1 Bit 0 SA0 Description 0 0 φW /8 0 1 φW /4 1 * φW /2 (initial value) *: Don’t care 5.2 Sleep Mode 5.2.1 Transition to Sleep Mode 1.
Section 5 Power-Down Modes 5.2.2 Clearing Sleep Mode Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event counter, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, WKP7 to WKP0, SCI3, A/D converter), or by input at the RES pin. • Clearing by interrupt When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
Section 5 Power-Down Modes 5.3 Standby Mode 5.3.1 Transition to Standby Mode The system goes from active mode to standby mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in TMA is cleared to 0.
Section 5 Power-Down Modes • When a oscillator is used The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a wait time at least as long as the oscillation stabilization time. Table 5.4(1) Clock Frequency and Stabilization Time (H8/38024, H8/38024S, H8/38024R Group) (Unit: ms) STS2 STS1 STS0 Wait Time 5 MHz 2 MHz 0 0 0 8,192 states 1.638 4.1 1 16,384 states 3.277 8.2 1 0 1,024 states 0.205 0.512 1 2,048 states 0.410 1.024 0 4,096 states 0.
Section 5 Power-Down Modes • When the on-chip oscillator is used 8,192 states (STS2 = STS1 = STS0 = 0) is recommended if the on-chip oscillator is used on the H8/38124 Group. 5.3.4 Standby Mode Transition and Pin States When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed) mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is cleared to 0 in TMA, a transition is made to standby mode.
Section 5 Power-Down Modes 5.3.5 Notes on External Input Signal Changes before/after Standby Mode 1. When external input signal changes before/after standby mode or watch mode When an external input signal such as IRQ, WKP, or IRQAEC is input, both the high- and low-level widths of the signal must be at least two cycles of system clock φ or subclock φSUB (referred to together in this section as the internal clock).
Section 5 Power-Down Modes Operating mode Active (high-speed, medium-speed) mode or subactive mode tcyc tsubcyc tcyc tsubcyc Wait for Active (high-speed, Standby mode oscillation medium-speed) mode or watch mode to settle or subactive mode tcyc tsubcyc tcyc tsubcyc φ or φSUB External input signal Capture possible: case 1 Capture possible: case 2 Capture possible: case 3 Capture not possible Interrupt by different signal Figure 5.
Section 5 Power-Down Modes 5.4.2 Clearing Watch Mode Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ0, or WKP7 to WKP0) or by input at the RES pin. • Clearing by interrupt When watch mode is cleared by interrupt, the mode to which a transition is made depends on the settings of LSON in SYSCR1 and MSON in SYSCR2.
Section 5 Power-Down Modes 5.5 Subsleep Mode 5.5.1 Transition to Subsleep Mode The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D converter and PWM is in active state.
Section 5 Power-Down Modes 5.6 Subactive Mode 5.6.1 Transition to Subactive Mode Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode, subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous event counter, SCI3, IRQAEC, IRQ4, IRQ3, IRQ1, IRQ0, or WKP7 to WKP0 interrupt is requested.
Section 5 Power-Down Modes 5.7 Active (Medium-Speed) Mode 5.7.1 Transition to Active (Medium-Speed) Mode If the MSON bit in SYSCR2 is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed) mode results from IRQ0, IRQ1 or WKP7 to WKP0 interrupts in standby mode, timer A, timer F, timer G, IRQ0, or WKP7 to WKP0 interrupts in watch mode, or any interrupt in sleep mode.
Section 5 Power-Down Modes 5.8 Direct Transfer 5.8.1 Overview of Direct Transfer The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed) mode, and subactive mode. A direct transfer is a transition among these three modes without the stopping of program execution. A direct transfer can be made by executing a SLEEP instruction while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt exception handling starts.
Section 5 Power-Down Modes • Direct transfer from active (medium-speed) mode to subactive mode When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made to subactive mode via watch mode.
Section 5 Power-Down Modes 2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
Section 5 Power-Down Modes 4. Time for direct transition from subactive mode to active (medium-speed) mode A direct transition from subactive mode to active (medium-speed) mode is performed by executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set to 1 in TMA.
Section 5 Power-Down Modes 5.9 Module Standby Mode 5.9.1 Setting Module Standby Mode Module standby mode is set for individual peripheral functions. All the on-chip peripheral modules can be placed in module standby mode. When a module enters module standby mode, the system clock supply to the module is stopped and operation of the module halts. This state is identical to standby mode.
Section 5 Power-Down Modes Register Name Bit Name CKSTPR2 LDCKSTP PW1CKSTP WDCKSTP AECKSTP PW2CKSTP LVDCKSTP* Operation 1 LCD module standby mode is cleared 0 LCD is set to module standby mode 1 PWM1 module standby mode is cleared 0 PWM1 is set to module standby mode 1 Watchdog timer module standby mode is cleared 0 Watchdog timer is set to module standby mode 1 Asynchronous event counter module standby mode is cleared 0 Asynchronous event counter is set to module standby mode 1 PWM2 m
Section 6 ROM Section 6 ROM 6.1 Overview The H8/38024, H8/38024S, and H8/38124 have 32 Kbytes of on-chip mask ROM, the H8/38023, H8/38023S, and H8/38123 have 24 Kbytes, the H8/38022, H8/38022S, and H8/38122 have 16 Kbytes, the H8/38021, H8/38021S, and H8/38121 have 12 Kbytes, and the H8/38020, H8/38020S, and H8/38120 have 8 Kbytes. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed two-state access for both byte data and word data.
Section 6 ROM 6.2 H8/38024 PROM Mode 6.2.1 Setting to PROM Mode If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a microcontroller and allows the PROM to be programmed in the same way as the standard HN27C101 EPROM. However, page programming is not supported. Table 6.1 shows how to set the chip to PROM mode. Table 6.1 Setting to PROM Mode Pin Name Setting TEST High level PB0/AN0 Low level PB1/AN1 PB2/AN2 6.2.
Section 6 ROM H8/38024 EPROM socket FP-80A, TFP-80C FP-80B 12 14 RES Pin VPP 1 21 23 P60 EO0 13 22 24 P61 EO1 14 23 25 P62 EO2 15 24 26 P63 EO3 17 25 27 P64 EO4 18 26 28 P65 EO5 19 27 29 P66 EO6 20 28 30 P67 EO7 21 69 71 P40 EA0 12 70 72 P41 EA1 11 63 65 P32 EA2 10 64 66 P33 EA3 9 65 67 P34 EA4 8 66 68 P35 EA5 7 67 69 P36 EA6 6 68 70 P37 EA7 5 29 31 P70 EA8 27 72 74 P43 EA9 26 31 33 P72 EA10 23 32 34
Section 6 ROM Address in MCU mode Address in PROM mode H'0000 H'0000 On-chip PROM H'7FFF H'7FFF Uninstalled area* H'1FFFF Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore, when programming with a PROM programmer, be sure to specify addresses from H'0000 to H'7FFF. If programming is inadvertently performed from H'8000 onward, it may not be possible to continue PROM programming and verification.
Section 6 ROM 6.3 H8/38024 Programming The write, verify, and other modes are selected as shown in table 6.2 in H8/38024 PROM mode. Table 6.
Section 6 ROM Start Set write/verify mode VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V Address = 0 n=0 n+1 →n No Yes n < 25 Write time t PW = 0.2 ms ± 5% No Address + 1 → address Verify Yes Write time t OPW = 0.2n ms Last address? No Yes Set read mode VCC = 5.0 V ± 0.25 V, VPP = VCC No Error Read all addresses? Yes End Figure 6.4 High-Speed, High-Reliability Programming Flowchart Rev. 8.00 Mar.
Section 6 ROM Tables 6.3 and 6.4 give the electrical characteristics in programming mode. Table 6.3 DC Characteristics Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Typ Max Unit Test Condition Input high-level voltage EO7 to EO0, EA16 to EA0, OE, CE, PGM VIH 2.4 — VCC + 0.3 V Input lowlevel voltage EO7 to EO0, EA16 to EA0, OE, CE, PGM VIL –0.3 — 0.8 V Output high-level voltage EO7 to EO0 VOH 2.
Section 6 ROM Table 6.4 AC Characteristics Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C Item Symbol Min Typ Max Unit Test Condition Address setup time tAS 2 — — µs Figure 6.5* OE setup time tOES 2 — — µs Data setup time tDS 2 — — µs Address hold time tAH 0 — — µs Data hold time 2 — — µs Data output disable time tDH 2 tDF* — — 130 ns VPP setup time tVPS 2 — — µs Programming pulse width tPW 0.19 0.20 0.
Section 6 ROM Figure 6.5 shows a PROM write/verify timing diagram. Write Verify Address tAS Data tAH Input data tDS VPP tDH tDF VPP VCC VCC Output data tVPS VCC+1 VCC tVCS CE tCES PGM tPW OE tOES tOE tOPW* Note: * tOPW is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart. Figure 6.5 PROM Write/Verify Timing Rev. 8.00 Mar.
Section 6 ROM 6.3.2 Programming Precautions • Use the specified programming voltage and timing. The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can permanently damage the chip. Be especially careful with respect to PROM programmer overshoot. Setting the PROM programmer to Renesas specifications for the HN27C101 will result in correct VPP of 12.5 V. • Make sure the index marks on the PROM programmer socket, socket adapter, and chip are properly aligned.
Section 6 ROM 6.4 Reliability of Programmed Data A highly effective way to improve data retention characteristics is to bake the programmed chips at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM memory cells prone to early failure. Figure 6.6 shows the recommended screening procedure. Program chip and verify programmed data Bake chip for 24 to 48 hours at 125°C to 150°C with power off Read and check program Install Figure 6.
Section 6 ROM 6.5 Flash Memory Overview 6.5.1 Features The features of the 32-Kbyte or 16-Kbyte flash memory built into the flash memory versions are summarized below. • Programming/erase methods ⎯ The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units. On the HD64F38024, HD64F38024R, and HD64F38124 the flash memory is configured as follows: 1 Kbyte × 4 blocks, 28 Kbytes × 1 block.
Section 6 ROM Block Diagram Internal address bus Internal data bus (16 bits) FLMCR1 Module bus 6.5.2 FLMCR2 Bus interface/controller EBR Operating mode TES pin P95 pin P34 pin FLPWCR FENR Flash memory [Legend] FLMCR1: FLMCR2: EBR: FLPWCR: FENR: Flash memory control register 1 Flash memory control register 2 Erase block register Flash memory power control register Flash memory enable register Figure 6.7 Block Diagram of Flash Memory Rev. 8.00 Mar.
Section 6 ROM 6.5.3 Block Configuration Figure 6.8 shows the block configuration of the flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. In versions with 32 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4 blocks and 28 Kbytes × 1 block. In versions with 16 Kbytes of flash memory, the flash memory is divided into 1 Kbyte × 4 blocks and 12 Kbytes × 1 block. Erasing is performed in these units.
Section 6 ROM Erase unit H'0000 H'0001 H'0002 H'0080 H'0081 H'0082 H'00FF H'0380 H'0381 H'0382 H'03FF H'0400 H'0401 H'0402 H'0480 H'0481 H'0482 H'04FF H'0780 H'0781 H'0782 H'07FF H'0800 H'0801 H'0802 H'0880 H'0881 H'0882 H'08FF H'0B80 H'0B81 H'0B82 H'0BFF H'0C00 H'0C01 H'0C02 H'0C80 H'0C81 H'0C82 H'0F80 H'0F81 H'0F82 H'1000 H'1001 H'1002 H'1080 H'1081 H'1082 H'10FF H'3F80 H'3F81 H'3F82 H'3FFF Programming unit: 128 bytes H'007F 1 Kbyte Erase unit Pro
Section 6 ROM 6.5.4 Register Configuration Table 6.5 lists the register configuration to control the flash memory when the built in flash memory is effective. Table 6.
Section 6 ROM Bit 6—Software Write Enable (SWE) This bit is to set enabling/disabling of programming/enabling of flash memory (set when bits 5 to 0 and the EBR register are to be set). Bit 6 SWE Description 0 Programming/erasing is disabled. Other FLMCR1 register bits and all EBR bits cannot be set. (initial value) 1 Flash memory programming/erasing is enabled. Bit 5—Erase Setup (ESU) This bit is to prepare for changing to erase mode.
Section 6 ROM Bit 3 EV Description 0 Erase-verify mode is cancelled 1 The flash memory changes to erase-verify mode (initial value) Bit 2—Program-Verify (PV) This bit is to set changing to or cancelling program-verify mode (do not set SWE, ESU, PSU, EV, E, and P bits at the same time).
Section 6 ROM 6.6.2 Flash Memory Control Register 2 (FLMCR2) Bit 7 6 5 4 3 2 1 0 FLER — — — — — — — Initial value 0 0 0 0 0 0 0 0 Read/Write R — — — — — — — FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a read-only register, and should not be written to.
Section 6 ROM 6.6.3 Erase Block Register (EBR) Bit 7 6 5 4 3 2 1 0 — — — EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write — — — R/W R/W R/W R/W R/W EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be erased.
Section 6 ROM Bit 7—Power-down Disable (PDWND) This bit selects the power-down mode of the flash memory when a transition to the subactive mode is made. Bit 7 PDWND Description 0 When this bit is 0 and a transition is made to the subactive mode, the flash memory enters the power-down mode. (initial value) 1 When this bit is 1, the flash memory remains in the normal mode even after a transition is made to the subactive mode. Bits 6 to 0—Reserved These bits are always read as 0 and cannot be modified.
Section 6 ROM 6.7 On-Board Programming Modes There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed with a PROM programmer. On-board programming/erasing can also be performed in user program mode.
Section 6 ROM 3. When the boot program is initiated, the chip measures the low-level period of asynchronous SCI communication data (H'00) transmitted continuously from the host. The chip then calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be pulled up on the board if necessary.
Section 6 ROM Table 6.8 Boot Mode Operation Item Host Operation LSI Operation Processing Contents Processing Contents Branches to boot program at reset-start. Bit rate adjustment Continuously transmits data H'00 at specified bit rate. Flash memory erase Transmits data H'55 when data H'00 is received and no error occurs. · Measures low-level period of receive data H'00. · Calculates bit rate and sets it in BRR of SCI3. · Transmits data H'00 to the host to indicate that the adjustment has ended.
Section 6 ROM 6.7.2 Programming/Erasing in User Program Mode The term user mode refers to the status when a user program is being executed. On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data.
Section 6 ROM 6.7.3 Notes on On-Board Programming 1. You must use the system clock oscillator when programming or erasing flash memory on the H8/38124 Group. The on-chip oscillator should not be used for programming or erasing flash memory. See section 4.2, On-Chip Oscillator Selection Method, for information on switching between the system clock oscillator and the on-chip oscillator. 2. On the H8/38124 Group the watchdog timer operates after a reset is canceled.
Section 6 ROM reprogramming data computation according to table 6.10, and additional programming data computation according to table 6.11. 4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or additional-programming data area to the flash memory. The program address and 128-byte data are latched in the flash memory. The lower 8 bits of the start address in the flash memory destination area must be H'00 or H'80.
Section 6 ROM Write pulse application subroutine Apply Write Pulse START Set SWE bit in FLMCR1 WDT enable Wait 1 μs Set PSU bit in FLMCR1 Store 128-byte program data in program data area and reprogram data area Wait 50 μs n=1 Set P bit in FLMCR1 m=0 Wait (Wait time = programming time) Write 128-byte data in RAM reprogram data area consecutively to flash memory Clear P bit in FLMCR1 Apply Write pulse Wait 5 μs Set PV bit in FLMCR1 Clear PSU bit in FLMCR1 Wait 4 μs Wait 5 μs Set block start addre
Section 6 ROM Table 6.10 Reprogram Data Computation Table Program Data Verify Data Reprogram Data Comments 0 0 1 Programming completed 0 1 0 Reprogram bit 1 0 1 — 1 1 1 Remains in erased state Table 6.
Section 6 ROM 6.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be followed. 1. Prewriting (setting erase block data to all 0s) is not necessary. 2. Erasing is performed in block units. Make only a single-bit specification in the erase block register (EBR). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
Section 6 ROM Erase start SWE bit ← 1 Wait 1 μs n←1 Set EBR Enable WDT ESU bit ← 1 Wait 100 μs E bit ← 1 Wait 10 ms E bit ← 0 Wait 10 μs ESU bit ← 0 Wait 10 μs Disable WDT EV bit ← 1 Wait 20 μs Set block start address as verify address H'FF dummy write to verify address Wait 2 μs n←n+1 Read verify data No Verify data = all 1s ? Increment address Yes No Last address of block ? Yes No EV bit ← 0 EV bit ← 0 Wait 4 μs Wait 4μs All erase block erased ? n ≤100 ? Yes No Yes SWE bit ← 0 SWE bit ← 0
Section 6 ROM 6.9 Program/Erase Protection There are three kinds of flash memory program/erase protection; hardware protection, software protection, and error protection. 6.9.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode, or standby mode.
Section 6 ROM 6.9.3 Error Protection In error protection, an error is detected when CPU runaway occurs during flash memory programming/erasing, or operation is not performed in accordance with the program/erase algorithm, and the program/erase operation is aborted. Aborting the program/erase operation prevents damage to the flash memory due to overprogramming or overerasing.
Section 6 ROM 6.10.2 Programmer Mode Commands The following commands are supported in programmer mode. • Memory Read Mode • Auto-Program Mode • Auto-Erase Mode • Status Read Mode Status polling is used for auto-programming, auto-erasing, and status read modes. In status read mode, detailed internal information is output after the execution of auto-programming or autoerasing. Table 6.13 shows the sequence of each command.
Section 6 ROM HD64F38024, HD64F38024R Pin No.
Section 6 ROM HD64F38124, HD64F38122 Pin No.
Section 6 ROM 6.10.3 Memory Read Mode 1. After completion of auto-program/auto-erase/status read operations, a transition is made to the command wait state. When reading memory contents, a transition to memory read mode must first be made with a command write, after which the memory contents are read. Once memory read mode has been entered, consecutive reads can be performed. 2. In memory read mode, command writes can be performed in the same way as in the command wait state. 3.
Section 6 ROM Table 6.15 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Command write cycle tnxtc 20 — µs Figure 6.
Section 6 ROM Table 6.16 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Access time tacc — 20 µs Figure 6.15 CE output delay time tce — 150 ns Figure 6.16 OE output delay time toe — 150 ns Output disable delay time tdf — 100 ns Data output hold time toh 5 — ns A15−A0 Address stable Address stable CE OE WE tacc tacc toh toh I/O7−I/O0 Figure 6.
Section 6 ROM 6.10.4 Auto-Program Mode 1. When reprogramming previously programmed addresses, perform auto-erasing before autoprogramming. 2. Perform auto-programming once only on the same address block. It is not possible to program an address block that has already been programmed. 3. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out by executing 128 consecutive byte transfers. A 128-byte data transfer is necessary even when programming fewer than 128 bytes.
Section 6 ROM Table 6.17 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Command write cycle tnxtc 20 — µs Figure 6.
Section 6 ROM 6.10.5 Auto-Erase Mode 1. Auto-erase mode supports only entire memory erasing. 2. Do not perform a command write during auto-erasing. 3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin). 4. Status polling I/O6 and I/O7 pin information is retained until the next command write.
Section 6 ROM A15−A0 tces tceh tnxtc tnxtc CE OE tf twep tr tests tspa WE tds terase tdh I/O7 Erase end decision signal I/O6 Erase normal end decision signal I/O5−I/O0 H'20 H'20 H'00 Figure 6.18 Auto-Erase Mode Timing Waveforms 6.10.6 Status Read Mode 1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. 2.
Section 6 ROM Table 6.19 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Notes Read time after command write tnxtc 20 — µs Figure 6.
Section 6 ROM Table 6.20 Status Read Mode Return Codes Pin Name Initial Value Indications I/O7 0 1: Abnormal end 0: Normal end I/O6 0 1: Command error I/O5 0 1: Programming error 0: Otherwise 0: Otherwise I/O4 0 1: Erasing error 0: Otherwise I/O3 0 ⎯ I/O2 0 ⎯ I/O1 0 1: Over counting of writing or erasing 0: Otherwise I/O0 0 1: Effective address error 0: Otherwise 6.10.7 Status Polling 1.
Section 6 ROM 6.10.8 Programmer Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the programmer mode setup period. After the programmer mode setup time, a transition is made to memory read mode. Table 6.
Section 6 ROM 6.11 Power-Down States for Flash Memory In user mode, the flash memory will operate in either of the following states: • Normal operating mode The flash memory can be read and written to at high speed. • Power-down operating mode The power supply circuit of the flash memory is partly halted and can be read under low power consumption. • Standby mode All flash memory circuits are halted. Table 6.23 shows the correspondence between the operating modes of this LSI and the flash memory.
Section 6 ROM Rev. 8.00 Mar.
Section 7 RAM Section 7 RAM 7.1 Overview The H8/38024, H8/38023, H8/38022, H8/38124, H8/38123, H8/38122, H8/38024S, H8/38023S, and H8/38022S have 1 Kbyte of high-speed static RAM on-chip, and the H8/38021, H8/38020, H8/38121, H8/38120, H8/38021S, and H8/38020S have 512 bytes. The RAM is connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data and word data. 7.1.1 Block Diagram Figure 7.1 shows a block diagram of the on-chip RAM.
Section 7 RAM Rev. 8.00 Mar.
Section 8 I/O Ports Section 8 I/O Ports 8.1 Overview The LSI is provided with five 8-bit I/O ports, two 4-bit I/O ports, one 3-bit I/O port, one 8-bit input-only port, one 1-bit input-only port, and one 6-bit output-only port. Table 8.1 indicates the functions of each port. Each port has of a port control register (PCR) that controls input and output, and a port data register (PDR) for storing output data. Input or output can be assigned to individual bits. See section 2.9.
Section 8 I/O Ports Other Functions Function Switching Registers P43/IRQ0 External interrupt 0 PMR2 P42/TXD32 P41/RXD32 P40/SCK32 SCI3 data output (TXD32), data input (RXD32), clock input/output (SCK32) SCR3 SMR3 SPCR P57 to P50/ WKP7 to WKP0/ SEG8 to SEG1 Wakeup input (WKP7 to WKP0), segment output (SEG8 to SEG1) PMR5 LPCR P67 to P60/ SEG16 to SEG9 Segment output (SEG16 to SEG9) LPCR 8-bit I/O port P77 to P70/ SEG24 to SEG17 Segment output (SEG24 to SEG17) LPCR • 8-bit I/O port P87 to
Section 8 I/O Ports 8.2 Port 1 8.2.1 Overview Port 1 is a 4-bit I/O port. Figure 8.1 shows its pin configuration. P17/IRQ3/TMIF P16* Port 1 P14/IRQ4/ADTRG P13/TMIG Note: * Pin 16 and the associated function are not implemented on the H8/38124 Group. Figure 8.1 Port 1 Pin Configuration 8.2.2 Register Configuration and Description Table 8.2 shows the port 1 register configuration. Table 8.2 Port 1 Registers Name Abbr.
Section 8 I/O Ports Port Data Register 1 (PDR1) Bit 7 6 5 4 3 2 1 0 P17 P16* — P14 P13 — — — Initial value 0 0 — 0 0 — — — Read/Write R/W R/W — R/W R/W — — — PDR1 is an 8-bit register that stores data for port 1 pins P17, P16*, P14, and P13. If port 1 is read while PCR1 bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is read while PCR1 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports Port Pull-Up Control Register 1 (PUCR1) Bit 7 6 PUCR17 PUCR16* 5 — 4 3 PUCR14 PUCR13 2 1 0 — — — Initial value 0 0 — 0 0 — — — Read/Write R/W R/W W R/W R/W W W W PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17, P16*, P14, and P13 is on or off. When a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Section 8 I/O Ports Bit 4—P14/IRQ4/ADTRG Pin Function Switch (IRQ4) This bit selects whether pin P14/IRQ4/ADTRG is used as P14 or as IRQ4/ADTRG. Bit 4 IRQ4 Description 0 Functions as P14 I/O pin 1 Functions as IRQ4/ADTRG input pin (initial value) Note: For details of ADTRG pin setting, see section 12.3.2, Start of A/D Conversion by External Trigger Input. Bit 3—P13/TMIG Pin Function Switch (TMIG) This bit selects whether pin P13/TMIG is used as P13 or as TMIG.
Section 8 I/O Ports This section only deals with the bits related to timer G and the watchdog timer. For the functions of the bits, see the descriptions of port 3 (POF1) and port 4 (IRQ0). Bit 2—Watchdog Timer Source Clock (WDCKS) This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R Group and for the H8/38124 Group are different.
Section 8 I/O Ports 8.2.3 Pin Functions Table 8.3 shows the port 1 pin functions. Table 8.3 Port 1 Pin Functions Pin Pin Functions and Selection Method P17/IRQ3/TMIF The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF, and bit PCR17 in PCR1.
Section 8 I/O Ports 8.2.4 Pin States Table 8.4 shows the port 1 pin states in each operating mode. Table 8.4 Port 1 Pin States Pins Reset Sleep Subsleep Standby P17/IRQ3/TMIF HighRetains Retains 1 P16* impedance previous previous state P14/IRQ4/ADTRG state P13/TMIG Watch Subactive Active HighRetains Functional Functional 2 impedance* previous state Notes: 1. Pin 16 and the associated function are not implemented on the H8/38124 Group. 2.
Section 8 I/O Ports 8.3 Port 3 8.3.1 Overview Port 3 is an 8-bit I/O port, configured as shown in figure 8.2. P3 7 /AEVL P3 6 /AEVH P3 5 P3 4 Port 3 P3 3 P3 2 /TMOFH P3 1 /TMOFL P3 0 /UD Figure 8.2 Port 3 Pin Configuration 8.3.2 Register Configuration and Description Table 8.5 shows the port 3 register configuration. Table 8.5 Port 3 Registers Name Abbr.
Section 8 I/O Ports Port Data Register 3 (PDR3) Bit 7 6 5 4 3 2 1 0 P3 7 P36 P35 P34 P3 3 P32 P31 P30 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3 bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is read while PCR3 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports Port Pull-Up Control Register 3 (PUCR3) Bit 7 6 5 4 3 2 1 0 PUCR37 PUCR36 PUCR3 5 PUCR34 PUCR3 3 PUCR3 2 PUCR31 PUCR30 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PUCR3 controls whether the MOS pull-up of each of the port 3 pins P37 to P30 is on or off. When a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Section 8 I/O Ports Port Mode Register 3 (PMR3) Bit 7 6 5 4 3 2 1 0 AEVL AEVH ⎯ ⎯ ⎯ TMOFH TMOFL UD Initial value 0 0 ⎯ ⎯ ⎯ 0 0 0 Read/Write R/W R/W W W W R/W R/W R/W PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins. Bit 7—P37/AEVL Pin Function Switch (AEVL) This bit selects whether pin P37/AEVL is used as P37 or as AEVL.
Section 8 I/O Ports Bit 1—P31/TMOFL Pin Function Switch (TMOFL) This bit selects whether pin P31/TMOFL is used as P31 or as TMOFL. Bit 1 TMOFL Description 0 Functions as P31 I/O pin 1 Functions as TMOFL output pin (initial value) Bit 0—P30/UD Pin Function Switch (UD) This bit selects whether pin P30/UD is used as P30 or as UD. Bit 0 UD Description 0 Functions as P30 I/O pin 1 Functions as UD input pin Rev. 8.00 Mar.
Section 8 I/O Ports 8.3.3 Pin Functions Table 8.6 shows the port 3 pin functions. Table 8.6 Port 3 Pin Functions Pin Pin Functions and Selection Method P37/AEVL The pin function depends on bit AEVL in PMR3 and bit PCR37 in PCR3. AEVL P36/AEVH 0 PCR37 0 1 * Pin function P37 input pin P37 output pin AEVL input pin The pin function depends on bit AEVH in PMR3 and bit PCR36 in PCR3.
Section 8 I/O Ports 8.3.4 Pin States Table 8.7 shows the port 3 pin states in each operating mode. Table 8.7 Port 3 Pin States Pins Reset Sleep Subsleep Standby P37/AEVL P36/AEVH P35 P34 P33 P32/TMOFH P31/TMOFL P30/UD Highimpedance Retains Retains previous previous state state Watch Subactive Active Retains Functional Functional Highimpedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.3.
Section 8 I/O Ports 8.4 Port 4 8.4.1 Overview Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.3. P4 3 /IRQ0 P4 2 /TXD32 Port 4 P4 1 /RXD32 P4 0 /SCK32 Figure 8.3 Port 4 Pin Configuration 8.4.2 Register Configuration and Description Table 8.8 shows the port 4 register configuration. Table 8.8 Port 4 Registers Name Abbr.
Section 8 I/O Ports Port Control Register 4 (PCR4) Bit 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ PCR42 PCR4 1 PCR4 0 Initial value 1 1 1 1 1 0 0 0 Read/Write ⎯ ⎯ ⎯ ⎯ ⎯ W W W PCR4 is an 8-bit register for controlling whether each of port 4 pins P42 to P40 functions as an input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Section 8 I/O Ports 8.4.3 Pin Functions Table 8.9 shows the port 4 pin functions. Table 8.9 Port 4 Pin Functions Pin Pin Functions and Selection Method P43/IRQ0 The pin function depends on bit IRQ0 in PMR2. P42/TXD32 P41/RXD32 IRQ0 0 1 Pin function P43 input pin IRQ0 input pin The pin function depends on bit TE in SCR3, bit SPC32 in SPCR, and bit PCR42 in PCR4.
Section 8 I/O Ports 8.4.4 Pin States Table 8.10 shows the port 4 pin states in each operating mode. Table 8.10 Port 4 Pin States Pins Reset Sleep Subsleep Standby P43/IRQ0 P42/TXD32 P41/RXD32 P40/SCK32 HighRetains Retains impedance previous previous state state Rev. 8.00 Mar.
Section 8 I/O Ports 8.5 Port 5 8.5.1 Overview Port 5 is an 8-bit I/O port, configured as shown in figure 8.4. P57/WKP7/SEG8 P56/WKP6/SEG7 P55/WKP5/SEG6 P54/WKP4/SEG5 Port 5 P53/WKP3/SEG4 P52/WKP2/SEG3 P51/WKP1/SEG2 P50/WKP0/SEG1 Figure 8.4 Port 5 Pin Configuration 8.5.2 Register Configuration and Description Table 8.11 shows the port 5 register configuration. Table 8.11 Port 5 Registers Name Abbr.
Section 8 I/O Ports Port Data Register 5 (PDR5) Bit 7 6 5 4 3 2 1 0 P57 P56 P55 P54 P53 P52 P51 P50 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5 bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is read while PCR5 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports Port Pull-Up Control Register 5 (PUCR5) Bit 7 6 5 4 3 2 0 1 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PUCR5 controls whether the MOS pull-up of each of port 5 pins P57 to P50 is on or off. When a PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Section 8 I/O Ports 8.5.3 Pin Functions Table 8.12 shows the port 5 pin functions. Table 8.12 Port 5 Pin Functions Pin Pin Functions and Selection Method P57/WKP7/ SEG8 to The pin function depends on bits WKP7 to WKP0 in PMR5, bits PCR57 to PCR50 in PCR5, and bits SGS3 to SGS0 in LPCR.
Section 8 I/O Ports 8.5.4 Pin States Table 8.13 shows the port 5 pin states in each operating mode. Table 8.13 Port 5 Pin States Pins Reset Sleep Subsleep Standby P57/WKP7/ SEG8 to P50/ WKP0/SEG1 HighRetains Retains impedance previous previous state state Watch Subactive Active Retains Functional Functional Highimpedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. In the HD64F38024 the previous pin state is retained. 8.5.
Section 8 I/O Ports 8.6 Port 6 8.6.1 Overview Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.5. P67/SEG16 P66/SEG15 P65/SEG14 P64/SEG13 Port 6 P63/SEG12 P62/SEG11 P61/SEG10 P60/SEG9 Figure 8.5 Port 6 Pin Configuration 8.6.2 Register Configuration and Description Table 8.14 shows the port 6 register configuration. Table 8.14 Port 6 Registers Name Abbr.
Section 8 I/O Ports Port Data Register 6 (PDR6) Bit 7 6 5 4 3 2 1 0 P6 7 P66 P65 P64 P6 3 P62 P61 P6 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60. If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports Port Pull-Up Control Register 6 (PUCR6) Bit 7 6 5 4 3 2 0 1 PUCR67 PUCR66 PUCR6 5 PUCR64 PUCR6 3 PUCR6 2 PUCR61 PUCR60 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PUCR6 controls whether the MOS pull-up of each of the port 6 pins P67 to P60 is on or off. When a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Section 8 I/O Ports 8.6.4 Pin States Table 8.16 shows the port 6 pin states in each operating mode. Table 8.16 Port 6 Pin States Pin Reset Sleep Subsleep Standby P67/SEG16 to P60/SEG9 HighRetains Retains impedance previous previous state state Watch Subactive Active Retains Functional Functional Highimpedance* previous state Note: * A high-level signal is output when the MOS pull-up is in the on state. 8.6.
Section 8 I/O Ports 8.7 Port 7 8.7.1 Overview Port 7 is an 8-bit I/O port, configured as shown in figure 8.6. P77/SEG24 P76/SEG23 P75/SEG22 P74/SEG21 Port 7 P73/SEG20 P72/SEG19 P71/SEG18 P70/SEG17 Figure 8.6 Port 7 Pin Configuration 8.7.2 Register Configuration and Description Table 8.17 shows the port 7 register configuration. Table 8.17 Port 7 Registers Name Abbr. R/W Initial Value Address Port data register 7 PDR7 R/W H'00 H'FFDA Port control register 7 PCR7 W H'00 H'FFEA Rev.
Section 8 I/O Ports Port Data Register 7 (PDR7) Bit 7 6 5 4 3 2 1 0 P7 7 P7 6 P75 P7 4 P73 P72 P71 P70 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7 bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is read while PCR7 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports 8.7.3 Pin Functions Table 8.18 shows the port 7 pin functions. Table 8.18 Port 7 Pin Functions Pin Pin Functions and Selection Method P77/SEG24 to P70/SEG17 The pin function depends on bits PCR77 to PCR70 in PCR7 and bits SGS3 to SGS0 in LPCR.
Section 8 I/O Ports 8.8 Port 8 8.8.1 Overview Port 8 is an 8-bit I/O port configured as shown in figure 8.7. P87/SEG32 P86/SEG31 P85/SEG30 P84/SEG29 Port 8 P83/SEG28 P82/SEG27 P81/SEG26 P80/SEG25 Figure 8.7 Port 8 Pin Configuration 8.8.2 Register Configuration and Description Table 8.20 shows the port 8 register configuration. Table 8.20 Port 8 Registers Name Abbr. R/W Initial Value Address Port data register 8 PDR8 R/W H'00 H'FFDB Port control register 8 PCR8 W H'00 H'FFEB Rev. 8.
Section 8 I/O Ports Port Data Register 8 (PDR8) Bit 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P8 0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8 bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is read while PCR8 bits are cleared to 0, the pin states are read.
Section 8 I/O Ports 8.8.3 Pin Functions Table 8.21 shows the port 8 pin functions. Table 8.21 Port 8 Pin Functions Pin Pin Functions and Selection Method P87/SEG32 to P80/SEG25 The pin function depends on bits PCR87 to PCR80 in PCR8 and bits SGS3 to SGS0 in LPCR.
Section 8 I/O Ports 8.9 Port 9 8.9.1 Overview Port 9 is a 6-bit output port, configured as shown in figure 8.8. P95 P94 Port 9 P93/Vref* P92 P91/PWM2 P90/PWM1 Note: * The Vref pin is implemented on the H8/38124 Group only. Figure 8.8 Port 9 Pin Configuration Rev. 8.00 Mar.
Section 8 I/O Ports 8.9.2 Register Configuration and Description Table 8.23 shows the port 9 register configuration. Table 8.23 Port 9 Registers Name Abbr.
Section 8 I/O Ports Bit 3— P92 to P90 Step-Up Circuit Control (PIOFF) Bit 3 turns the P92 to P90 step-up circuit on and off. This bit is reserved in the H8/38024S Group and H8/38124 Group. Bit 3 PIOFF Description 0 Large-current port step-up circuit is turned on 1 Large-current port step-up circuit is turned off (initial value) Note: In the H8/38024 ZTAT version and mask ROM version, and the HD64F38024R, the following precautions should be followed when accessing the PIOFF bit.
Section 8 I/O Ports from 1 to 0 only when the PIOFF bit is cleared to 0. Also, if a large current flow is required, the PIOFF bit should be set to 1 and all the port data bits set to 1. Then clear PIOFF to 0 and, after allowing 30 clock cycles to permit stabilization of the voltage boost circuit, clear the port data bits to 0. If time is not provided to allow the voltage boost circuit to stabilize, it will not be possible to produce a large current flow.
Section 8 I/O Ports 8.9.3 Pin Functions Table 8.24 shows the port 9 pin functions. Table 8.24 Port 9 Pin Functions Pin Pin Functions and Selection Method P93/Vref* P91/PWMn+1 to P90/PWMn+1 VREFSEL 0 1 Pin function P93 output pin Vref input pin PMR9n 0 1 Pin function P9n output pin PWMn+1 output pin (n = 1 or 0) Note: * The Vref pin is the input pin for the LVD’s external reference voltage. It is implemented on the H8/38124 Group only. 8.9.4 Pin States Table 8.
Section 8 I/O Ports 8.10 Port A 8.10.1 Overview Port A is a 4-bit I/O port, configured as shown in figure 8.9. PA3/COM4 PA2/COM3 Port A PA1/COM2 PA0/COM1 Figure 8.9 Port A Pin Configuration 8.10.2 Register Configuration and Description Table 8.26 shows the port A register configuration. Table 8.26 Port A Registers Name Abbr.
Section 8 I/O Ports Port Control Register A (PCRA) Bit 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ PCRA 2 PCRA 1 Initial value 1 1 1 1 0 0 0 0 Read/Write ⎯ ⎯ ⎯ ⎯ W W W W PCRA 3 PCRA 0 PCRA controls whether each of port A pins PA3 to PA0 functions as an input pin or output pin. Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0 makes the pin an input pin.
Section 8 I/O Ports 8.10.3 Pin Functions Table 8.27 shows the port A pin functions. Table 8.27 Port A Pin Functions Pin Pin Functions and Selection Method PA3/COM4 The pin function depends on bit PCRA3 in PCRA and bits SGS3 to SGS0. PA2/COM3 PA1/COM2 PA0/COM1 SGS3 to SGS0 0000 0000 Not 0000 PCRA3 0 1 * Pin function PA3 input pin PA3 output pin COM4 output pin The pin function depends on bit PCRA2 in PCRA and bits SGS3 to SGS0.
Section 8 I/O Ports 8.10.4 Pin States Table 8.28 shows the port A pin states in each operating mode. Table 8.28 Port A Pin States Pins Reset Sleep Subsleep Standby PA3/COM4 PA2/COM3 PA1/COM2 PA0/COM1 HighRetains Retains impedance previous previous state state Rev. 8.00 Mar.
Section 8 I/O Ports 8.11 Port B 8.11.1 Overview Port B is an 8-bit input-only port, configured as shown in figure 8.10. PB7/AN7 PB6/AN6 PB5/AN5 PB4/AN4 Port B PB3/AN3/IRQ1/TMIC PB2/AN2 PB1/AN1/extU* PB0/AN0/extD* Note: * The extU and extD pins are implemented on the H8/38124 Group only. Figure 8.10 Port B Pin Configuration 8.11.2 Register Configuration and Description Table 8.29 shows the port B register configuration. Table 8.29 Port B Register Name Abbr.
Section 8 I/O Ports Port Data Register B (PDRB) Bit Read/Write 7 6 5 4 3 2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB 0 R R R R R R R R Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input voltage.
Section 8 I/O Ports 8.11.3 Pin Functions Table 8.30 shows the port B pin functions. Table 8.30 Port B Pin Functions Pin Pin Functions and Selection Method PB7/AN7 The pin function depends on bits CH3 to CH0 in AMR. PB6/AN6 PB5/AN5 PB4/AN4 PB3/AN3/IRQ1/ TMIC CH3 to CH0 Not 1011 1011 Pin function PB7 input pin AN7 input pin The pin function depends on bits CH3 to CH0 in AMR.
Section 8 I/O Ports Pin Pin Functions and Selection Method PB1/AN1/extU Switching is accomplished by combining CH3 to CH0 in AMR and VINTUSEL in LVDCR as shown below. Note that VINTUSEL is implemented on the H8/38124 Group only. VINTUSEL 0 1 CH3 to CH0 Not B'0101 B'0101 * Pin function PB1 input pin AN1 input pin extU input pin Note: The extU pin is implemented on the H8/38124 Group only.
Section 8 I/O Ports 8.12.2 Register Configuration and Descriptions Table 8.31 shows the registers used by the input/output data inversion function. Table 8.31 Register Configuration Name Abbr.
Section 8 I/O Ports Bit 3—TXD32 Pin Output Data Inversion Switch Bit 3 specifies whether or not TXD32 pin output data is to be inverted. Bit 3 SCINV3 Description 0 TXD32 output data is not inverted 1 TXD32 output data is inverted (initial value) Bit 2—RXD32 Pin Input Data Inversion Switch Bit 2 specifies whether or not RXD32 pin input data is to be inverted.
Section 8 I/O Ports 8.13 Application Note 8.13.1 The Management of the Un-Use Terminal If an I/O pin not used by the user system is floating, pull it up or down. • If an unused pin is an input pin, handle it in one of the following ways: ⎯ Pull it up to VCC with an on-chip pull-up MOS. ⎯ Pull it up to VCC with an external resistor of approximately 100 kΩ. ⎯ Pull it down to VSS with an external resistor of approximately 100 kΩ. ⎯ For a pin also used by the A/D converter, pull it up to AVCC.
Section 8 I/O Ports Rev. 8.00 Mar.
Section 9 Timers Section 9 Timers 9.1 Overview This LSI provides six timers: timers A, C, F, G, and a watchdog timer, and an asynchronous event counter. The functions of these timers are outlined in table 9.1. Table 9.
Section 9 Timers Name Functions Asynchro- • nous event • counter 16-bit counter Also usable as two independent 8-bit counters • Counts events asynchronous to φ and φw • Can count asynchronous events (rising/falling/both edges) independ-ently of the MCU's internal clock Internal Clock φ/2 to φ/8 (3 choices) Event Input Pin Waveform Output Pin AEVL AEVH IRQAEC — Remarks Note: * The watchdog timer functions differently on the H8/38024, H8/38024S, H8/38024R Group and H8/38124 Group.
Section 9 Timers Block Diagram Figure 9.1 shows a block diagram of timer A. φW TMA PSW 1/4 Internal data bus φW /4 φW/128 φ +256* +128* +64* φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32, φ/8 +8* TCA PSS IRRTA [Legend] TMA: TCA: IRRTA: PSW: PSS: Timer mode register A Timer counter A Timer A overflow interrupt request flag Prescaler W Prescaler S Note: * Can be selected only when the prescaler W output (φW /128) is used as the TCA input clock. Figure 9.1 Block Diagram of Timer A Rev.
Section 9 Timers Register Configuration Table 9.2 shows the register configuration of timer A. Table 9.2 Timer A Registers Name Abbr. R/W Initial Value Address Timer mode register A TMA R/W — H'FFB0 Timer counter A TCA R H'00 H'FFB1 Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA 9.2.
Section 9 Timers Bits 3 to 0—Internal Clock Select (TMA3 to TMA0) Bits 3 to 0 select the clock input to TCA. The selection is made as follows. Description Bit 3 TMA3 Bit 2 TMA2 Bit 1 TMA1 Bit 0 TMA0 Prescaler and Divider Ratio or Overflow Period 0 0 0 0 PSS, φ/8192 1 PSS, φ/4096 0 PSS, φ/2048 1 PSS, φ/512 0 PSS, φ/256 1 PSS, φ/128 0 PSS, φ/32 1 PSS, φ/8 0 0 PSW, 1 s 1 PSW, 0.5 s base 1 0 PSW, 0.25 s (when using 1 PSW, 0.03125 s 32.
Section 9 Timers Timer Counter A (TCA) Bit 7 6 5 4 3 2 1 0 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A (TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive mode.
Section 9 Timers 9.2.3 Timer Operation Interval Timer Operation When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit interval timer. Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in TMA; any of eight internal clock signals output by prescaler S can be selected.
Section 9 Timers 9.2.4 Timer A Operation States Table 9.3 summarizes the timer A operation states. Table 9.
Section 9 Timers 9.3 Timer C 9.3.1 Overview Timer C is an 8-bit timer that increments or decrements each time a clock pulse is input. This timer has two operation modes, interval and auto reload. Features Features of timer C are given below. • Choice of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/64, φ/16, φ/4, φW/4) or an external clock (can be used to count external events). • An interrupt is requested when the counter overflows.
Section 9 Timers Block Diagram Figure 9.2 shows a block diagram of timer C. Internal data bus TMC UD TCC φ PSS TMIC TLC φW /4 IRRTC [Legend] TMC: Timer mode register C TCC: Timer counter C Timer load register C TLC: IRRTC: Timer C overflow interrupt request flag PSS: Prescaler S Figure 9.2 Block Diagram of Timer C Pin Configuration Table 9.4 shows the timer C pin configuration. Table 9.4 Pin Configuration Name Abbr.
Section 9 Timers Register Configuration Table 9.5 shows the register configuration of timer C. Table 9.5 Timer C Registers Name Abbr. R/W Initial Value Address Timer mode register C TMC R/W H'18 H'FFB4 Timer counter C TCC R H'00 H'FFB5 Timer load register C TLC W H'00 H'FFB5 Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA 9.3.
Section 9 Timers Bits 6 and 5—Counter Up/Down Control (TMC6, TMC5) Selects whether TCC up/down control is performed by hardware using UD pin input, or whether TCC functions as an up-counter or a down-counter.
Section 9 Timers Timer Counter C (TCC) Bit 7 6 5 4 3 2 1 0 TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R TCC is an 8-bit read-only up/down-counter, which is incremented or decremented by internal clock or external event input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode register C (TMC). TCC values can be read by the CPU at any time.
Section 9 Timers Clock Stop Register 1 (CKSTPR1) Bit: 7 6 ⎯ ⎯ 5 4 3 2 1 0 S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Initial value: 1 1 1 1 1 1 1 1 Read/Write: ⎯ ⎯ R/W R/W R/W R/W R/W R/W CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer C is described here. For details of the other bits, see the sections on the relevant modules.
Section 9 Timers During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC), the same value is set in TCC. Note: For details on interrupts, see section 3.3, Interrupts. Auto-Reload Timer Operation Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a reload value is set in TLC, the same value is loaded into TCC, becoming the value from which TCC starts its count.
Section 9 Timers 9.3.4 Timer C Operation States Table 9.6 summarizes the timer C operation states. Table 9.
Section 9 Timers 9.4 Timer F 9.4.1 Overview Timer F is a 16-bit timer with a built-in output compare function. As well as counting external events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc., using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH and timer FL). Features Features of timer F are given below.
Section 9 Timers Block Diagram Figure 9.3 shows a block diagram of timer F.
Section 9 Timers Pin Configuration Table 9.7 shows the timer F pin configuration. Table 9.7 Pin Configuration Name Abbr. I/O Function Timer F event input TMIF Input Event input pin for input to TCFL Timer FH output TMOFH Output Timer FH toggle output pin Timer FL output TMOFL Output Timer FL toggle output pin Register Configuration Table 9.8 shows the register configuration of timer F. Table 9.8 Timer F Registers Name Abbr.
Section 9 Timers 9.4.2 Register Descriptions 16-bit Timer Counter (TCF) 8-bit Timer Counter (TCFH) 8-bit Timer Counter (TCFL) TCF Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCFH TCFL TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters TCFH and TCFL.
Section 9 Timers 16-bit Output Compare Register (OCRF) 8-bit Output Compare Register (OCRFH) 8-bit Output Compare Register (OCRFL) OCRF Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W OCRFH OCRFL OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL.
Section 9 Timers Timer Control Register F (TCRF) Bit: 7 6 5 4 3 2 1 0 TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value: 0 0 0 0 0 0 0 0 Read/Write: W W W W W W W W TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the input clock from among four internal clock sources or external event input, and sets the output level of the TMOFH and TMOFL pins. TCRF is initialized to H'00 upon reset.
Section 9 Timers Bit 3—Toggle Output Level L (TOLL) Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is written. Bit 3 TOLL Description 0 Low level 1 High level (initial value) Bits 2 to 0—Clock Select L (CKSL2 to CKSL0) Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event input.
Section 9 Timers Timer Control/Status Register F (TCSRF) Bit: 7 6 5 4 3 2 1 0 OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value: 0 0 0 0 0 0 0 0 Read/Write: R/(W)* R/(W)* R/W R/W R/(W)* R/(W)* R/W R/W Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing. TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting, and compare match flag setting, and controls enabling of overflow interrupt requests.
Section 9 Timers Bit 5—Timer Overflow Interrupt Enable H (OVIEH) Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows. Bit 5 OVIEH Description 0 TCFH overflow interrupt request is disabled 1 TCFH overflow interrupt request is enabled (initial value) Bit 4—Counter Clear H (CCLRH) In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match. In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match.
Section 9 Timers Bit 2—Compare Match Flag L (CMFL) Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and cleared by software. It cannot be set by software.
Section 9 Timers Clock Stop Register 1 (CKSTPR1) 7 6 ⎯ ⎯ Initial value: 1 1 1 1 1 1 1 1 Read/Write: ⎯ ⎯ R/W R/W R/W R/W R/W R/W Bit: 5 4 3 2 1 0 S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to timer F is described here. For details of the other bits, see the sections on the relevant modules.
Section 9 Timers Figure 9.4 shows an example in which H'AA55 is written to TCF. Write to upper byte CPU (H'AA) Module data bus Bus interface TEMP (H'AA) TCFH ( ) TCFL ( ) Write to lower byte CPU (H'55) Module data bus Bus interface TEMP (H'AA) TCFH (H'AA) TCFL (H'55) Figure 9.4 Write Access to TCF (CPU → TCF) Rev. 8.00 Mar.
Section 9 Timers Read Access In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the lower-byte data in TEMP is transferred to the CPU. In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU. Figure 9.
Section 9 Timers 9.4.4 Operation Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is constantly compared with the value set in output compare register F, and the counter can be cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can also function as two independent 8-bit timers. Timer F Operation Timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each of these modes is described below.
Section 9 Timers TCF Increment Timing TCF is incremented by clock input (internal clock or external event input). a. Internal clock operation Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock sources (φ/32, φ/16, φ/4, or φw/4) created by dividing the system clock (φ or φw). b. External event operation External event input is selected by clearing CKSL2 to 0 in TCRF. TCF can increment on either the rising or falling edge of external event input.
Section 9 Timers TCF Clear Timing TCF can be cleared by a compare match with OCRF. Timer Overflow Flag (OVF) Set Timing OVF is set to 1 when TCF overflows from H'FFFF to H'0000. Compare Match Flag Set Timing The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match. The compare match signal is generated in the last state during which the values match (when TCF is updated from the matching value to a new value).
Section 9 Timers 9.4.5 Application Notes The following types of contention and operation can occur when timer F is used. 16-bit Timer Mode In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal is generated. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write.
Section 9 Timers b. TCFL, OCRFL In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF write by a MOV instruction and generation of the compare match signal occur simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write. If an OCRFL write and compare match signal generation occur simultaneously, the compare match signal is invalid. However, if the written data and the counter value match, a compare match signal will be generated at that point.
Section 9 Timers The term of validity of “Interrupt factor generation signal” = 1 cycle of φw + waiting time for completion of executing instruction + interrupt time synchronized with φ = 1/φw + ST × (1/φ) + (2/φ) (second).....(1) ST: Executing number of execution states Method 1 is recommended to operate for time efficiency. Method 1 1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0). 2.
Section 9 Timers Interrupt request flag clear Interrupt request flag clear (2) Program process Interrupt Interrupt Normal φW Interrupt factor generation signal (Internal signal, nega-active) Overflow signal, Compare match signal (Internal signal, nega-active) Interrupt request flag (IRRTFH, IRRTFL) (1) Figure 9.
Section 9 Timers 9.5 Timer G 9.5.1 Overview Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of pulses input from the input capture input pin (input capture input signal). High-frequency component noise in the input capture input signal can be eliminated by a noise canceler, enabling accurate measurement of the input capture input signal duty cycle. If input capture input is not set, timer G functions as an 8-bit interval timer.
Section 9 Timers Block Diagram Figure 9.8 shows a block diagram of timer G. φ PSS Level detector φW/4 ICRGF TMIG Noise canceler Edge detector NCS Internal data bus TMG TCG ICRGR IRRTG [Legend] TMG: TCG: ICRGF: ICRGR: IRRTG: NCS: PSS: Timer mode register G Timer counter G Input capture register GF Input capture register GR Timer G interrupt request flag Noise canceler select Prescaler S Figure 9.8 Block Diagram of Timer G Pin Configuration Table 9.10 shows the timer G pin configuration.
Section 9 Timers Register Configuration Table 9.11 shows the register configuration of timer G. Table 9.11 Timer G Registers Name Abbr. R/W Initial Value Address Timer control register G TMG R/W H'00 H'FFBC Timer counter G TCG — H'00 — Input capture register GF ICRGF R H'00 H'FFBD Input capture register GR ICRGR R H'00 H'FFBE Clock stop register 1 CKSTPR1 R/W H'FF H'FFFA 9.5.
Section 9 Timers Input Capture Register GF (ICRGF) Bit: 7 6 5 4 3 2 1 0 ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value: 0 0 0 0 0 0 0 0 Read/Write: R R R R R R R R ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time, IRRTG in IRR2 is set to 1, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
Section 9 Timers Timer Mode Register G (TMG) Bit: Initial value: Read/Write: 7 6 5 4 3 2 1 0 OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 0 R/(W)* 0 R/(W)* 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
Section 9 Timers Bit 5—Timer Overflow Interrupt Enable (OVIE) Bit 5 selects enabling or disabling of interrupt generation when TCG overflows. Bit 5 OVIE Description 0 TCG overflow interrupt request is disabled 1 TCG overflow interrupt request is enabled (initial value) Bit 4—Input Capture Interrupt Edge Select (IIEGS) Bit 4 selects the input capture input signal edge that generates an interrupt request.
Section 9 Timers Bits 1 and 0—Clock Select (CKS1, CKS0) Bits 1 and 0 select the clock input to TCG from among four internal clock sources.
Section 9 Timers 9.5.3 Noise Canceler The noise canceler consists of a digital low-pass filter that eliminates high-frequency component noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in PMR2. Figure 9.9 shows a block diagram of the noise canceler. Sampling clock C Input capture input signal C D Q D Latch Q Latch C D C Q Latch D C Q Latch D Q Latch Match detector Noise canceler output Δt Sampling clock Δt: Set by CKS1 and CKS0 Figure 9.
Section 9 Timers In this example, high-level input of less than five times the width of the sampling clock at the input capture input pin is eliminated as noise. Input capture input signal Sampling clock Noise canceler output Eliminated as noise Figure 9.10 Noise Canceler Timing (Example) Rev. 8.00 Mar.
Section 9 Timers 9.5.4 Operation Timer G is an 8-bit timer with built-in input capture and interval functions. Timer G Functions Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval timer function. The operation of these two functions is described below. a. Input capture timer operation When the TMIG bit in port mode register 1 (PMR1) is set to 1, timer G functions as an input capture timer*.
Section 9 Timers b. Interval timer operation When the TMIG bit in PMR1 is cleared to 0, timer G functions as an interval timer. Following a reset, TCG starts counting on the φ/64 internal clock. The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG increments on the selected clock, and when it overflows from H'FF to H'00, the OVFL bit in TMG is set to 1.
Section 9 Timers b. With noise cancellation function When noise cancellation is performed on the input capture input, the passage of the input capture signal through the noise canceler results in a delay of five sampling clock cycles from the input capture input signal edge. Figure 9.12 shows the timing in this case. Input capture input signal Sampling clock Noise canceler output Input capture signal R Figure 9.
Section 9 Timers TCG Clear Timing TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input signal. Figure 9.14 shows the timing for clearing by both edges. Input capture input signal Input capture signal F Input capture signal R TCG N H'00 N H'00 Figure 9.14 TCG Clear Timing Rev. 8.00 Mar.
Section 9 Timers Timer G Operation Modes Timer G operation modes are shown in table 9.12. Table 9.
Section 9 Timers 9.5.5 Application Notes Internal Clock Switching and TCG Operation Depending on the timing, TCG may be incremented by a switch between different internal clock sources. Table 9.13 shows the relation between internal clock switchover timing (by write to bits CKS1 and CKS0) and TCG operation. When TCG is internally clocked, an increment pulse is generated on detection of the falling edge of an internal clock signal, which is divided from the system clock (φ) or subclock (φw).
Section 9 Timers No. Clock Levels Before and After Modifying Bits CKS1 and CKS0 TCG Operation 3 Goes from high level to low level Clock before switching Clock after switching * Count clock TCG N N+1 N+2 Write to CKS1 and CKS0 4 Goes from high level to high level Clock before switching Clock after switching Count clock TCG N N+1 N+2 Write to CKS1 and CKS0 Note: * The switchover is seen as a falling edge, and TCG is incremented.
Section 9 Timers Table 9.
Section 9 Timers When the pin function is switched and an edge is generated in the input capture input signal, if this edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use. Figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag clearing.
Section 9 Timers 9.5.6 Timer G Application Example Using timer G, it is possible to measure the high and low widths of the input capture input signal as absolute values. For this purpose, CCLR1 and CCLR0 in TMG should both be set to 1. Figure 9.16 shows an example of the operation in this case. Input capture input signal H'FF Input capture register GF Input capture register GR H'00 TCG Counter cleared Figure 9.16 Timer G Application Example Rev. 8.00 Mar.
Section 9 Timers 9.6 Watchdog Timer 9.6.1 Overview The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset the chip internally. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R Group and for the H8/38124 Group are different. Features Features of the watchdog timer are given below.
Section 9 Timers Block Diagram Figures 9.17(1) and 9.17(2) show a block diagram of the watchdog timer. φ PSS φ/8192 TCW [Legend] TCSRW: Timer control/status register W Timer counter W TCW: Prescaler S PSS: Internal data bus TCSRW φW/32 Reset signal Figure 9.17(1) Block Diagram of Watchdog Timer (H8/38024, H8/38024S, H8/38024R Group) Rev. 8.00 Mar.
Section 9 Timers Watchdog on-chip oscillator φ Internal data bus TMW TCSRW PSS TCW φW/32 Interrupt/reset controller [Legend] TCSRW: TCW: TMW: PSS: Internal reset signal or interrupt request signal Timer control/status register W Timer counter W Timer mode register W Prescaler S Figure 9.17(2) Block Diagram of Watchdog Timer (H8/38124 Group) Register Configuration Table 9.16 shows the register configuration of the watchdog timer. Table 9.16 Watchdog Timer Registers Name Abbr.
Section 9 Timers 9.6.2 Register Descriptions Timer Control/Status Register W (TCSRW) Bit Initial value Read/Write 7 6 5 4 3 2 1 0 B6WI TCWE B4WI TCSRWE B2WI WDON B0WI WRST 1 0 1 0 1 0/1*2 1 0 R (R/W)*1 R (R/W)*1 R (R/W)*1 R (R/W)*1 Notes: 1. Write is enabled only under certain conditions, which are given in the descriptions of the individual bits. 2. Initial value is 0 on H8/38024, H8/38024S, and H8/38024R Group; initial value is 1 on H8/38124 Group.
Section 9 Timers Bit 5—Bit 4 Write Disable (B4WI) Bit 5 controls the writing of data to bit 4 in TCSRW. Bit 5 B4WI Description 0 Bit 4 is write-enabled 1 Bit 4 is write-protected (initial value) This bit is always read as 1. Data written to this bit is not stored. Bit 4—Timer Control/Status Register W Write Enable (TCSRWE) Bit 4 controls the writing of data to bits 2 and 0 in TCSRW.
Section 9 Timers Bit 2 WDON Description 0 Watchdog timer operation is disabled (initial value)* Clearing conditions: Reset, or when TCSRWE is set to 1 and 0 is written to B2WI and WDON. Note that a reset clears WDON to 0 on the H8/38024, H8/38024S, and H8/38024R Group, but sets WDON to 1 on the H8/38124 Group. Note: * Initial value is 0 on H8/38024, H8/38024S, and H8/38024R Group; initial value is 1 on H8/38124 Group.
Section 9 Timers Timer Counter W (TCW) Bit 7 6 5 4 3 2 1 0 TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W For the H8/38024, H8/38024S, and H8/38024R groups, the clock source is φ/8,192 or φw/32. For the H8/38124 group, the clock source is selected based on the timer mode register (TMW) setting if WDCKS is 0 and is φw/32 if WDCKS is 1.
Section 9 Timers Bit 3 CKS3 Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Description 1 0 0 0 Internal clock: φ/64 count 1 Internal clock: φ/128 count 1 0 Internal clock: φ/256 count 1 Internal clock: φ/512 count 0 Internal clock: φ/1024 count 1 Internal clock: φ/2048 count 0 Internal clock: φ/4096 count 1 Internal clock: φ/8192 count X Watchdog on-chip oscillator 1 0 1 0 X X (initial value) Note: X: Don't care Clock Stop Register 2 (CKSTPR2) Bit 7 6 5 LVDCKSTD* ⎯ ⎯ 4 3 2 1 0
Section 9 Timers Port Mode Register 2 (PMR2) Bit 7 6 5 4 3 2 1 0 — — POF1 — — WDCKS NCS IRQ0 Initial value 1 1 0 1 1 0 0 0 Read/Write — — R/W — — R/W R/W R/W PMR2 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 2. Only the bit relating to the watchdog timer is described here. For details of the other bits, see section 8, I/O Ports. Bit 2—Watchdog Timer Source Clock Select (WDCKS) This bit selects the watchdog timer source clock.
Section 9 Timers 9.6.3 Timer Operation The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input. The input clock is selected by the WDCKS in port mode register 2 (PMR2): on the H8/38024, H8/38024S, and H8/38024R Group, φ/8192 is selected when WDCKS is cleared to 0, and φw/32 when set to 1. On the H8/38124 Group, if WDCKS is cleared to 0 the clock selection is specified by the setting of timer mode register W (TMW), and if WDCKS is set to 1 the φw/32 clock source is selected.
Section 9 Timers 9.6.4 Watchdog Timer Operation States Table 9.17(1) and table 9.17(2) summarize the watchdog timer operation states for the H8/38024, H8/38024S, and H8/38024R Group, and for the H8/38124 Group, respectively. Table 9.
Section 9 Timers 9.7 Asynchronous Event Counter (AEC) 9.7.1 Overview The asynchronous event counter is incremented by external event clock or internal clock input. Features Features of the asynchronous event counter are given below. • Can count asynchronous events Can count external events input asynchronously without regard to the operation of base clocks φ and φSUB. The counter has a 16-bit configuration, enabling it to count up to 65536 (216) events.
Section 9 Timers Block Diagram Figure 9.19 shows a block diagram of the asynchronous event counter.
Section 9 Timers Pin Configuration Table 9.18 shows the asynchronous event counter pin configuration. Table 9.18 Pin Configuration Name Abbr. I/O Function Asynchronous event input H AEVH Input Event input pin for input to event counter H Asynchronous event input L AEVL Input Event input pin for input to event counter L Event input enable interrupt input IRQAEC Input Input pin for interrupt enabling event input Register Configuration Table 9.
Section 9 Timers 9.7.2 Register Configurations Event Counter PWM Compare Register H (ECPWCRH) Bit 7 6 5 4 3 2 1 0 ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWCRH should not be modified.
Section 9 Timers Event Counter PWM Data Register H (ECPWDRH) Bit 7 6 5 4 3 2 1 0 ECPWDRH7 ECPWDRH6 ECPWDRH5 ECPWDRH4 ECPWDRH3 ECPWDRH2 ECPWDRH1 ECPWDRH0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Note: When ECPWME in AEGSR is 1, event counter PWM is operating and therefore ECPWDRH should not be modified. When changing the data, event counter PWM must be halted by clearing ECPWME to 0 in AEGSR before modifying ECPWDRH.
Section 9 Timers Bits 7 and 6—AEC Edge Select H Bits 7 and 6 select rising, falling, or both edge sensing for the AEVH pin. Bit 7 AHEGS1 Bit 6 AHEGS0 Description 0 0 Falling edge on AEVH pin is sensed 1 Rising edge on AEVH pin is sensed 0 Both edges on AEVH pin are sensed 1 Use prohibited 1 (initial value) Bits 5 and 4—AEC Edge Select L Bits 5 and 4 select rising, falling, or both edge sensing for the AEVL pin.
Section 9 Timers Bit 1—Event Counter PWM Enable Bit 1 controls enabling/disabling of event counter PWM and selection/deselection of IRQAEC. Bit 1 ECPWME Description 0 AEC PWM halted, IRQAEC selected 1 AEC PWM operation enabled, IRQAEC deselected (initial value) Bit 0—Reserved Bit 0 is a readable/writable reserved bit. It is initialized to 0 by a reset. Note: Do not set this bit to 1.
Section 9 Timers Bits 5 and 4—AEC Clock Select L (ACKL1, ACKL0) Bits 5 and 4 select the clock used by ECL. Bit 5 ACKL1 Bit 4 ACKL0 Description 0 0 AEVL pin input 1 φ/2 0 φ/4 1 φ/8 1 (initial value) Bits 3 to 1—Event Counter PWM Clock Select (PWCK2, PWCK1, PWCK0) Bits 3 to 1 select the event counter PWM clock.
Section 9 Timers Event Counter Control/Status Register (ECCSR) Bit 7 6 5 4 3 2 1 0 OVH OVL ⎯ CH2 CUEH CUEL CRCH CRCL Initial Value 0 0 0 0 0 0 0 0 Read/Write R/W* R/W* R/W R/W R/W R/W R/W R/W Note: * Bits 7 and 6 can only be written with 0, for flag clearing. ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting, and halting of the count-up function. ECCSR is initialized to H'00 upon reset.
Section 9 Timers Bit 6 OVL Description 0 ECL has not overflowed Clearing condition: After reading OVL = 1, cleared by writing 0 to OVL 1 ECL has overflowed Setting condition: Set when ECL overflows from H'FF to H'00 (initial value) Bit 5—Reserved Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset. Bit 4—Channel Select (CH2) Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two independent 8-bit event counter channels.
Section 9 Timers Bit 2—Count-up Enable L (CUEL) Bit 2 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled and increments the counter. When 0 is written to this bit, event clock input is disabled and the ECL value is held. Bit 2 CUEL Description 0 ECL event clock input is disabled ECL value is held 1 ECL event clock input is enabled (initial value) Bit 1—Counter Reset Control H (CRCH) Bit 1 controls resetting of ECH.
Section 9 Timers ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL. The external asynchronous event AEVH pin, φ/2, φ/4, φ/8, or the overflow signal from lower 8-bit counter ECL can be selected as the input clock source. ECH can be cleared to H'00 by software, and is also initialized to H'00 upon reset.
Section 9 Timers 9.7.3 Operation 16-bit Event Counter Operation When bit CH2 is cleared to 0 in ECCSR, ECH and ECL operate as a 16-bit event counter. Any of four input clock sources—φ/2, φ/4, φ/8, or AEVL pin input—can be selected by means of bits ACKL1 and ACKL0 in ECCR. When AEVL pin input is selected, input sensing is selected with bits ALEGS1 and ALEGS0. The input clock is enabled only when IRQAEC is high or IECPWM is high.
Section 9 Timers 8-bit Event Counter Operation When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters. φ/2, φ/4, φ/8, or AEVH pin input can be selected as the input clock source for ECH by means of bits ACKH1 and ACKH0 in ECCR, and φ/2, φ/4, φ/8, or AEVL pin input can be selected as the input clock source for ECL by means of bits ACKL1 and ACKL0 in ECCR.
Section 9 Timers IRQAEC Operation When ECPWME in AEGSR is 0, the ECH and ECL input clocks are enabled only when IRQAEC is high. When IRQAEC is low, the input clocks are not input to the counters, and so ECH and ECL do not count. ECH and ECL count operations can therefore be controlled from outside by controlling IRQAEC. In this case, ECH and ECL cannot be controlled individually. IRQAEC can also operate as an interrupt source.
Section 9 Timers Figure 9.22 and table 9.20 show examples of event counter PWM operation. toff = T × (Ndr +1) Ton : Toff : Tcm : T: Ndr : Clock input enabled time Clock input disabled time One conversion period ECPWM input clock cycle Value of ECPWDRH and ECPWDRL Fixed low when Ndr = H'FFFF Ncm : Value of ECPWCRH and ECPWCRL ton tcm = T × (Ncm +1) Figure 9.22 Event Counter Operation Waveform Note: Ndr and Ncm above must be set so that Ndr < Ncm.
Section 9 Timers Clock Input Enable/Disable Function Operation The clock input to the event counter can be controlled by the IRQAEC pin when ECPWME in AEGSR is 0, and by event counter PWM output IECPWM when ECPWME in AEGSR is 1. As this function forcibly terminates the clock input by each signal, a maximum error of one count will occur depending the IRQAEC or IECPWM timing. Figure 9.23 shows an example of the operation of this function.
Section 9 Timers 9.7.4 Asynchronous Event Counter Operation Modes Asynchronous event counter operation modes are shown in table 9.21. Table 9.
Section 9 Timers Mode Maximum AEVH/AEVL Pin Input Clock Frequency Active (high-speed), sleep (high-speed) 16 MHz Active (medium-speed), sleep (medium-speed) (φ/16) 2 • fOSC (φ/32) fOSC (φ/64) 1/2 • fOSC fOSC = 1 MHz to 4 MHz (φ/128) 1/4 • fOSC Watch, subactive, subsleep, standby (φw/2) 1000 kHz (φw/4) 500 kHz (φw/8) 250 kHz φw = 32.768 kHz or 38.4 kHz* Note: * Does not apply to H8/38124 Group. 3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.
Section 9 Timers Rev. 8.00 Mar.
Section 10 Serial Communication Interface Section 10 Serial Communication Interface 10.1 Overview The H8/38024 Group is provided with one serial communication interface, SCI3. Serial communication interface 3 (SCI3) can carry out serial data communication in either asynchronous or synchronous mode. 10.1.1 Features Features of SCI3 are listed below.
Section 10 Serial Communication Interface • Full-duplex communication Separate transmission and reception units are provided, enabling transmission and reception to be carried out simultaneously. The transmission and reception units are both double-buffered, allowing continuous transmission and reception.
Section 10 Serial Communication Interface 10.1.2 Block Diagram Figure 10.1 shows a block diagram of SCI3.
Section 10 Serial Communication Interface 10.1.3 Pin Configuration Table 10.1 shows the SCI3 pin configuration. Table 10.1 Pin Configuration Name Abbr. I/O Function SCI3 clock SCK32 I/O SCI3 clock input/output SCI3 receive data input RXD32 Input SCI3 receive data input SCI3 transmit data output TXD32 Output SCI3 transmit data output 10.1.4 Register Configuration Table 10.2 shows the SCI3 register configuration. Table 10.2 Registers Name Abbr.
Section 10 Serial Communication Interface 10.2 Register Descriptions 10.2.1 Receive Shift Register (RSR) Bit 7 6 5 4 3 2 1 0 Read/Write ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ RSR is a register used to receive serial data. Serial data input to RSR from the RXD32 pin is set in the order in which it is received, starting from the LSB (bit 0), and converted to parallel data. When one byte of data is received, it is transferred to RDR automatically. RSR cannot be read or written directly by the CPU. 10.2.
Section 10 Serial Communication Interface 10.2.3 Transmit Shift Register (TSR) Bit 7 6 5 4 3 2 1 0 Read/Write ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR, and serial data transmission is carried out by sending the data to the TXD32 pin in order, starting from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is transferred to TDR, and transmission started, automatically.
Section 10 Serial Communication Interface 10.2.5 Serial Mode Register (SMR) Bit 7 6 5 4 3 2 1 0 COM CHR PE PM STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for the baud rate generator. SMR can be read or written by the CPU at any time. SMR is initialized to H'00 upon reset, and in standby, module standby, or watch mode.
Section 10 Serial Communication Interface Bit 5—Parity Enable (PE) Bit 5 selects whether a parity bit is to be added during transmission and checked during reception in asynchronous mode. In synchronous mode parity bit addition and checking is not performed, irrespective of the bit 5 setting. Bit 5 PE 0 1 Description 2 Parity bit addition and checking disabled* 1/ 2 Parity bit addition and checking enabled* * (initial value) Notes: 1.
Section 10 Serial Communication Interface Bit 3—Stop Bit Length (STOP) Bit 3 selects 1 bit or 2 bits as the stop bit length in asynchronous mode. The STOP bit setting is only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 1 stop bit* 2 2 stop bits* (initial value) Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character. 2.
Section 10 Serial Communication Interface Bits 1 and 0—Clock Select 1, 0 (CKS1, CKS0) Bits 1 and 0 choose φ/64, φ/16, φw/2, or φ as the clock source for the baud rate generator. For the relation between the clock source, bit rate register setting, and baud rate, see section 10.2.8, Bit rate register (BRR). Bit 1 CKS1 Bit 0 CKS0 Description 0 0 φ clock 0 1 φ w/2 clock /φ w clock 1 0 φ/16 clock 1 1 φ/64 clock (initial value) *1 *2 Notes: 1.
Section 10 Serial Communication Interface Bit 7 TIE Description 0 Transmit data empty interrupt request (TXI) disabled 1 Transmit data empty interrupt request (TXI) enabled (initial value) Bit 6—Receive Interrupt Enable (RIE) Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR) to the receive data register (RDR), and bit RDRF in the serial status registe
Section 10 Serial Communication Interface Bit 4—Receive Enable (RE) Bit 4 selects enabling or disabling of the start of receive operation. Bit 4 RE 0 1 Description 1 Receive operation disabled* (RXD32 pin is I/O port) 2 Receive operation enabled* (RXD32 pin is receive data pin) (initial value) Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is cleared to 0, and retain their previous state. 2.
Section 10 Serial Communication Interface Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0) Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK32 pin. The combination of CKE1 and CKE0 determines whether the SCK32 pin functions as an I/O port, a clock output pin, or a clock input pin. The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous mode.
Section 10 Serial Communication Interface 10.2.7 Serial Status Register (SSR) Bit 7 6 5 4 3 2 1 0 TDRE RDRF OER FER PER TEND MPBR MPBT Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only a write of 0 for flag clearing is possible. SSR is an 8-bit register containing status flags that indicate the operational status of SCI3.
Section 10 Serial Communication Interface Bit 6—Receive Data Register Full (RDRF) Bit 6 indicates that received data is stored in RDR.
Section 10 Serial Communication Interface Bit 4—Framing Error (FER) Bit 4 indicates that a framing error has occurred during reception in asynchronous mode.
Section 10 Serial Communication Interface Bit 2—Transmit End (TEND) Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent. Bit 2 is a read-only bit and cannot be modified.
Section 10 Serial Communication Interface 10.2.8 Bit Rate Register (BRR) Bit 7 6 5 4 3 2 1 0 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR). BRR can be read or written by the CPU at any time.
Section 10 Serial Communication Interface Table 10.3 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2) φ 5 MHz 8 MHz 10 MHz Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 3 21 0.88 3 35 –1.36 3 43 0.88 150 3 15 1.73 3 25 0.16 3 32 –1.36 200 3 11 1.73 3 19 –2.34 3 23 1.73 250 3 9 –2.34 3 15 –2.34 3 19 –2.34 300 3 7 1.73 3 12 0.16 3 15 1.73 600 3 3 1.73 2 25 0.16 3 7 1.73 1200 3 1 1.73 2 12 0.
Section 10 Serial Communication Interface Table 10.4 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 φ 0 0 0 φw/2 /φw 0 1 2 φ/16 1 0 3 φ/64 1 1 *1 *2 Notes: 1. φ w/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. φ w clock in subactive mode and subsleep mode In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only. Table 10.5 shows the maximum bit rate for each frequency. The values shown are for active (high-speed) mode.
Section 10 Serial Communication Interface Table 10.6 shows examples of BRR settings in synchronous mode. The values shown are for active (high-speed) mode. Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1) φ 1 MHz 19.2 kHz 2 MHz Bit Rate (bit/s) n N Error n N Error n N Error 200 0 23 0 — — — — — — 250 — — — — — — 2 124 0 300 2 0 0 — — — — — — 500 — — — — — — 1K 0 249 0 — — — 2.
Section 10 Serial Communication Interface Table 10.6 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2) φ 8 MHz 5 MHz 10 MHz Bit Rate (bit/s) n N Error n N Error n N Error 200 — — — — — — 0 12499 0 250 — — — 3 124 0 2 624 0 300 — — — — — — 0 8332 0 500 — — — 2 249 0 0 4999 0 1K — — — 2 124 0 0 2499 0 2.
Section 10 Serial Communication Interface Table 10.7 Relation between n and Clock SMR Setting n Clock CKS1 CKS0 0 φ 0 0 0 φw/2 /φw 0 1 2 φ/16 1 0 3 φ/64 1 1 *1 *2 Notes: 1. φw/2 clock in active (medium-speed/high-speed) mode and sleep mode 2. φw clock in subactive mode and subsleep mode In subactive or subsleep mode, SCI3 can be operated when CPU clock is φw/2 only. Rev. 8.00 Mar.
Section 10 Serial Communication Interface 10.2.9 Clock stop register 1 (CKSTPR1) Bit 7 6 5 4 3 2 1 0 ⎯ ⎯ Initial value 1 1 1 1 1 1 1 1 Read/Write ⎯ ⎯ R/W R/W R/W R/W R/W R/W S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the sections on the relevant modules.
Section 10 Serial Communication Interface Bit 5—P42/TXD32 Pin Function Switch (SPC32) This bit selects whether pin P42/TXD32 is used as P42 or as TXD32. Bit 5 SPC32 Description 0 Functions as P42 I/O pin 1 Functions as TXD32 output pin* (initial value) Note: * Set the TE bit in SCR3 after setting this bit to 1. Bit 4—Reserved Bit 4 is reserved; only 0 can be written to this bit. Bit 3—TXD32 Pin Output Data Inversion Switch Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Section 10 Serial Communication Interface 10.3 Operation 10.3.1 Overview SCI3 can perform serial communication in two modes: asynchronous mode in which synchronization is provided character by character, and synchronous mode in which synchronization is provided by clock pulses. The serial mode register (SMR) is used to select asynchronous or synchronous mode and the data transfer format, as shown in table 10.8.
Section 10 Serial Communication Interface Table 10.
Section 10 Serial Communication Interface Interrupts and Continuous Transmission/Reception SCI3 can carry out continuous reception using RXI and continuous transmission using TXI. These interrupts are shown in table 10.10. Table 10.
Section 10 Serial Communication Interface RDR RDR RSR (reception in progress) RXD32 pin RSR↑ (reception completed, transfer) RXD32 pin RDRF ← 1 (RXI request when RIE = 1) RDRF = 0 Figure 10.2(a) RDRF Setting and RXI Interrupt TDR (next transmit data) TDR TSR (transmission in progress) ↓ TSR (transmission completed, transfer) TXD32 pin TXD32 pin TDRE ← 1 (TXI request when TIE = 1) TDRE = 0 Figure 10.
Section 10 Serial Communication Interface 10.3.2 Operation in Asynchronous Mode In asynchronous mode, serial communication is performed with synchronization provided character by character. A start bit indicating the start of communication and one or two stop bits indicating the end of communication are added to each character before it is sent. SCI3 has separate transmission and reception units, allowing full-duplex communication.
Section 10 Serial Communication Interface Table 10.11 shows the 16 data transfer formats that can be set in asynchronous mode. The format is selected by the settings in the serial mode register (SMR). Table 10.
Section 10 Serial Communication Interface Clock Either an internal clock generated by the baud rate generator or an external clock input at the SCK32 pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.9 for details on clock source selection. When an external clock is input at the SCK32 pin, the clock frequency should be 16 times the bit rate.
Section 10 Serial Communication Interface Figure 10.5 shows an example of a flowchart for initializing SCI3. Start Clear bits TE and RE to 0 in SCR3 Set bits CKE1 and CKE0 [1] Set data transfer format in SMR [2] Set value in BRR [3] Wait Has 1-bit period elapsed? No [2] Set the data transfer format in the serial mode register (SMR). [3] Write the value corresponding to the transfer rate in BRR. This operation is not necessary when an external clock is selected.
Section 10 Serial Communication Interface • Transmitting Figure 10.6 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3. Start Sets bit SPC32 to 1 in SPCR Read bit TDRE in SSR [1] No TDRE = 1? Yes Write transmit data to TDR [2] Continue data transmission? Yes [1] Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR).
Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. Serial data is transmitted from the TXD32 pin using the relevant data transfer format in table 10.11. When the stop bit is sent, SCI3 checks bit TDRE.
Section 10 Serial Communication Interface • Receiving Figure 10.8 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bits OER, PER, FER in SSR [1] Read bits OER, PER, and FER in the serial status register (SSR) to determine if there is an error. If a receive error has occurred, execute receive error processing. [1] Yes OER + PER + FER = 1? [2] Read SSR and check that bit RDRF is set to 1.
Section 10 Serial Communication Interface Start receive error processing [4] Overrun error processing OER = 1? Yes No FER = 1? Break? Yes No No PER = 1? Yes [4] If a receive error has occurred, read bits OER, PER, and FER in SSR to identify the error, and after carrying out the necessary error processing, ensure that bits OER, PER, and FER are all cleared to 0. Yes Reception cannot be resumed if any of these bits is set to 1.
Section 10 Serial Communication Interface SCI3 operates as follows when receiving data. SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal synchronization and begins reception. Reception is carried out in accordance with the relevant data transfer format in table 10.11. The received data is first placed in RSR in LSB-to-MSB order, and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.
Section 10 Serial Communication Interface Figure 10.9 shows an example of the operation when receiving in asynchronous mode. Start bit Serial data 1 0 Receive data D0 D1 D7 Parity Stop Start bit bit bit 0/1 1 0 1 frame Receive data D0 D1 Parity Stop bit bit D7 0/1 0 Mark state (idle state) 1 1 frame RDRF FER RXI request LSI operation User processing RDRF cleared to 0 RDR data read 0 start bit detected ERI request in response to framing error Framing error processing Figure 10.
Section 10 Serial Communication Interface Data Transfer Format The general data transfer format in asynchronous communication is shown in figure 10.10. * * Serial clock LSB Serial data Bit 0 MSB Bit 1 Bit 2 Don't care Bit 3 Bit 4 Bit 5 Bit 6 8 bits Bit 7 Don't care One transfer data unit (character or frame) Note: * High level except in continuous transmission/reception Figure 10.
Section 10 Serial Communication Interface Data Transfer Operations • SCI3 initialization Data transfer on SCI3 first of all requires that SCI3 be initialized as described in section 10.3.2, SCI3 initialization, and shown in figure 10.5. • Transmitting Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be followed for data transmission after initializing SCI3.
Section 10 Serial Communication Interface SCI3 operates as follows when transmitting data. SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If bit TIE in SCR3 is set to 1 at this time, a TXI request is made. When clock output mode is selected, SCI3 outputs 8 serial clock pulses.
Section 10 Serial Communication Interface • Receiving Figure 10.13 shows an example of a flowchart for data reception. This procedure should be followed for data reception after initializing SCI3. Start Read bit OER in SSR [1] [1] Read bit OER in the serial status register (SSR) to determine if there is an error. If an overrun error has occurred, execute overrun error processing. Yes OER = 1? [2] Read SSR and check that bit RDRF is set to 1. If it is, read the receive data in RDR.
Section 10 Serial Communication Interface SCI3 operates as follows when receiving data. SCI3 performs internal synchronization and begins reception in synchronization with the serial clock input or output. The received data is placed in RSR in LSB-to-MSB order. After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from RSR to RDR.
Section 10 Serial Communication Interface • Simultaneous transmit/receive Figure 10.15 shows an example of a flowchart for a simultaneous transmit/receive operation. This procedure should be followed for simultaneous transmission/reception after initializing SCI3. Start Sets bit SPC32 to 1 in SPCR Read bit TDRE in SSR [1] Read the serial status register (SSR) and check that bit TDRE is set to 1, then write transmit data to the transmit data register (TDR).
Section 10 Serial Communication Interface Notes: 1. When switching from transmission to simultaneous transmission/reception, check that SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set bits TE and RE to 1 simultaneously. 2.
Section 10 Serial Communication Interface 10.4 Interrupts SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and three receive error interrupts (overrun error, framing error, and parity error). These interrupts have the same vector address. The various interrupt requests are shown in table 10.13. Table 10.13 SCI3 Interrupt Requests Interrupt Abbr.
Section 10 Serial Communication Interface 10.5 Application Notes The following points should be noted when using SCI3. 1. Relation between writes to TDR and bit TDRE Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to 0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Section 10 Serial Communication Interface 3. Break detection and processing When a framing error is detected, a break can be detected by reading the value of the RXD32 pin directly. In a break, the input from the RXD32 pin becomes all 0s, with the result that bit FER is set and bit PER may also be set. SCI3 continues the receive operation even after receiving a break. Note, therefore, that even though bit FER is cleared to 0 it will be set to 1 again. 4.
Section 10 Serial Communication Interface 16 clock pulses 8 clock pulses 0 7 15 0 7 15 0 Internal basic clock Receive data (RXD32) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 10.16 Receive Data Sampling Timing in Asynchronous Mode Consequently, the receive margin in asynchronous mode can be expressed as shown in equation (1). M ={(0.5 – where 1 D – 0.5 )– – (L – 0.5) F} × 100 [%] 2N N .....
Section 10 Serial Communication Interface 7. Relation between RDR reads and bit RDRF In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this indicates that an overrun error has occurred. When the contents of RDR are read, bit RDRF is cleared to 0 automatically.
Section 10 Serial Communication Interface 8. Transmit and receive operations when making a state transition Make sure that transmit and receive operations have completely finished before carrying out state transition processing. 9.
Section 11 10-Bit PWM Section 11 10-Bit PWM 11.1 Overview The H8/38024 Group is provided with two on-chip 10-bit PWMs (pulse width modulators), designated PWM1 and PWM2, with identical functions. The PWMs can be used as D/A converters by connecting a low-pass filter. In this section the suffix m (m = 1 or 2) is used with register names, etc., as in PWDRLm, which denotes the PWDRL registers for each PWM. 11.1.1 Features Features of the 10-bit PWMs are as follows.
Section 11 10-Bit PWM 11.1.2 Block Diagram Figure 11.1(1) shows a block diagram of the 10-bit PWM of the H8/38024 Group, H8/38024FZTAT Group, and H8/38024S Group. Figure 11.1(2) shows a block diagram of the 10-bit PWM of the H8/38124 Group. PWDRLm φ/2 φ/4 φ/8 φ Internal data bus PWDRUm PWM waveform generator PWCRm PWMm [Legend] PWDRLm: PWM data register L PWDRUm: PWM data register U PWCRm: PWM control register m = 1 or 2 Figure 11.
Section 11 10-Bit PWM PWDRUm φ/2 φ/4 φ/8 φ PWM waveform generator Internal data bus PWDRLm PWCRm IECPWM PWMm (IECPWM) [Legend] PWCRm: PWDRLm: PWDRUm: PWMm: IECPWM: m = 1 or 2 PWM control register PWM data register L PWM data register U PWM output pin Event counter PWM (PWM incorporating AEC) Figure 11.1(2) Figure 11.1(1) Block Diagram of the 10-bit PWM (H8/38124 Group: 1-Channel Configuration) 11.1.3 Pin Configuration Table 11.1 shows the output pin assigned to the 10-bit PWM. Table 11.
Section 11 10-Bit PWM 11.1.4 Register Configuration Table 11.2 shows the register configuration of the 10-bit PWM. Table 11.2 Register Configuration Name Abbr.
Section 11 10-Bit PWM Bits 7 to 2—Reserved/Bits 7 to 3—Reserved* Bits 7 to 2 are reserved; they are always read as 1, and cannot be modified. Note: * Implemented on H8/38124 Group only. Bit 2—Output Format Select (PWCRm2)* This bit selects the format of the output from the PWMm output pin. This bit is write-only. Reading it always returns 1. Bit 2 PWCRm2 Description 0 Pulse-division PWM 1 Event counter PWM (initial value) Note: * Implemented on H8/38124 Group only.
Section 11 10-Bit PWM 11.2.
Section 11 10-Bit PWM 11.2.3 Clock Stop Register 2 (CKSTPR2) 7 6 5 LVDCKSTP* — — Initial value 1 1 1 1 1 1 1 1 Read/Write R/W — — R/W R/W R/W R/W R/W Bit 4 3 2 1 0 PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group. CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the PWM is described here.
Section 11 10-Bit PWM 11.3 Operation 11.3.1 Operation When using the 10-bit PWM, set the registers in the following sequence. 1. Set PWM1 or PWM2 in PMR9 to 1 for the PWM channel to be used, so that pin P90/PWM1 or P91/PWM2 is designated as the PWM output pin, or both are designated as PWM output pins. 2.
Section 11 10-Bit PWM 1 conversion period tf2 tf3 tf1 tH1 tH2 tH3 tf4 tH4 TH = tH1 + tH2 + tH3 + tH4 tf1 = tf2 = tf3 = tf4 Figure 11.2 PWM Output Waveform 11.3.2 PWM Operation Modes PWM operation modes are shown in table 11.3. Table 11.
Section 11 10-Bit PWM Rev. 8.00 Mar.
Section 12 A/D Converter Section 12 A/D Converter 12.1 Overview This LSI includes on-chip a resistance-ladder-based successive-approximation analog-to-digital converter, and can convert up to 8 channels of analog input. 12.1.1 Features The A/D converter has the following features. • 10-bit resolution • Eight input channels • Conversion time: approx. 12.4 µs per channel (at 5-MHz operation)/6.
Section 12 A/D Converter 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the A/D converter. ADTRG AMR AN0 AN1 AN2 AN3 ADSR Multiplexer Internal data bus AN4 AN5 AN6 AVCC AN7 + Comparator − AVCC Reference voltage Control logic AVSS AVSS ADRRH ADRRL [Legend] AMR: A/D mode register ADSR: A/D start register ADRR: A/D result register IRRAD: A/D conversion end interrupt request flag Figure 12.1 Block Diagram of the A/D Converter Rev. 8.00 Mar.
Section 12 A/D Converter 12.1.3 Pin Configuration Table 12.1 shows the A/D converter pin configuration. Table 12.1 Pin Configuration Name Abbr.
Section 12 A/D Converter 12.2 Register Descriptions 12.2.
Section 12 A/D Converter Bit 7—Clock Select (CKS) Bit 7 sets the A/D conversion speed. Conversion Time Bit 7 CKS Conversion Period φ = 1 MHz φ = 5 MHz φ = 10 MHz* 0 62/φ (initial value) 62 µs 1 31/φ 31 µs 12.4 µs 1 —* 6.2 µs 1 —* 2 Notes: 1. With the H8/38024, H8/38024S, and H8/38024F-ZTAT operation cannot be guaranteed if the conversion time is less than 12.4 µs. Make sure to select a setting that gives a conversion time of 12.4 µs or more.
Section 12 A/D Converter Bits 3 to 0—Channel Select (CH3 to CH0) Bits 3 to 0 select the analog input channel. The channel selection should be made while bit ADSF is cleared to 0. Bit 3 CH3 Bit 2 CH2 Bit 1 CH1 Bit 0 CH0 Analog Input Channel 0 0 * * No channel selected 0 1 0 0 AN0 0 1 0 1 AN1 0 1 1 0 AN2 0 1 1 1 AN3 1 0 0 0 AN4 1 0 0 1 AN5 1 0 1 0 AN6 1 0 1 1 AN7 1 1 * * Setting prohibited (initial value) *: Don’t care 12.2.
Section 12 A/D Converter Bit 7—A/D Start Flag (ADSF) Bit 7 controls and indicates the start and end of A/D conversion. Bit 7 ADSF Description 0 Read: Indicates the completion of A/D conversion (initial value) Write: Stops A/D conversion 1 Read: Indicates A/D conversion in progress Write: Starts A/D conversion Bits 6 to 0—Reserved Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified. 12.2.
Section 12 A/D Converter 12.3 Operation 12.3.1 A/D Conversion Operation The A/D converter operates by successive approximations, and yields its conversion result as 10bit data. A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete. The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1.
Section 12 A/D Converter 12.3.3 A/D Converter Operation Modes A/D converter operation modes are shown in table 12.3. Table 12.
Section 12 A/D Converter If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 through 6 take place. A/D conversion result (2) Note: * ( ) indicates instruction execution by software. Read conversion result Read conversion result A/D conversion result (1) ADRRH ADRRL Idle Channel 1 (AN1) operation state ADSF IENAD Interrupt (IRRAD) A/D conversion starts Set* Set* A/D conversion (1) Idle Set* A/D conversion (2) Idle Figures 12.4 and 12.
Section 12 A/D Converter Start Set A/D conversion speed and input channel Disable A/D conversion end interrupt Start A/D conversion Read ADSR No ADSF = 0? Yes Read ADRRH/ADRRL data Yes Perform A/D conversion? No End Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Polling by Software) Rev. 8.00 Mar.
Section 12 A/D Converter Start Set A/D conversion speed and input channel Enable A/D conversion end interrupt Start A/D conversion A/D conversion end interrupt? No Yes Clear bit IRRAD to 0 in IRR2 Read ADRRH/ADRRL data Yes Perform A/D conversion? No End Figure 12.5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used) Rev. 8.00 Mar.
Section 12 A/D Converter 12.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below. • Resolution The number of A/D converter digital output codes • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 12.6). • Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value 0000000000 to 0000000001 (see figure 12.7).
Section 12 A/D Converter Digital output Ideal A/D conversion characteristic 111 110 101 100 011 010 Quantization error 001 000 1 8 2 8 3 8 4 8 5 8 7 FS 8 Analog input voltage 6 8 Figure 12.6 A/D Conversion Accuracy Definitions (1) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic Offset error FS Analog input voltage Figure 12.7 A/D Conversion Accuracy Definitions (2) Rev. 8.00 Mar.
Section 12 A/D Converter 12.7 Application Notes 12.7.1 Permissible Signal Source Impedance This LSI’s analog input is designed such that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 kΩ or less.
Section 12 A/D Converter 12.7.3 Additional Usage Notes • Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D start register (ADSR) is cleared to 0. • Changing the digital input signal at an adjacent pin during A/D conversion may adversely affect conversion accuracy. • When A/D conversion is started after clearing module standby mode, wait for 10 φ clock cycles before starting.
Section 13 LCD Controller/Driver Section 13 LCD Controller/Driver 13.1 Overview This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit, enabling it to directly drive an LCD panel. 13.1.1 Features Features of the LCD controller/driver are given below.
Section 13 LCD Controller/Driver 13.1.2 Block Diagram Figures 13.1(1) and 13.1(2) show a block diagram of the LCD controller/driver. LCD drive power supply VCC V1 V2 V3 VSS φ/256 to φ/2 Common data latch φW Common driver COM1 COM4 Internal data bus SEG32 LPCR LCR LCR2 32-bit shift register Display timing generator Segment driver LCD RAM (16 bytes) SEG1 SEGn [Legend] LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2 Figure 13.
Section 13 LCD Controller/Driver VCC V1 LCD drive power supply V2 V3 VSS φ/256 to φ/2 Common data latch Internal data bus φw Common driver COM1 COM4 SEG32 LPCR LCR LCR2 32-bit shift register Display timing generator Segment driver LCD RAM (16 bytes) SEG1 SEGn [Legend] LPCR: LCD port control register LCR: LCD control register LCR2: LCD control register 2 Figure 13.1(2) Block Diagram of H8/38124 Group LCD Controller/Driver Rev. 8.00 Mar.
Section 13 LCD Controller/Driver 13.1.3 Pin Configuration Table 13.1 shows the LCD controller/driver pin configuration. Table 13.1 Pin Configuration Name Abbr.
Section 13 LCD Controller/Driver 13.2 Register Descriptions 13.2.1 LCD Port Control Register (LPCR) Bit 7 6 5 4 3 2 1 0 DTS1 DTS0 CMX ⎯ SGS3 SGS2 SGS1 SGS0 Initial value 0 0 0 ⎯ 0 0 0 0 Read/Write R/W R/W R/W W R/W R/W R/W R/W LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions.
Section 13 LCD Controller/Driver Bits 3 to 0—Segment Driver Select 3 to 0 (SGS3 to SGS0) Bits 3 to 0 select the segment drivers to be used.
Section 13 LCD Controller/Driver 13.2.2 LCD Control Register (LCR) Bit 7 6 5 4 3 2 1 0 ⎯ PSW ACT DISP CKS3 CKS2 CKS1 CKS0 Initial value 1 0 0 0 0 0 0 0 Read/Write ⎯ R/W R/W R/W R/W R/W R/W R/W LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and display data control, and selects the frame frequency. LCR is initialized to H'80 upon reset. Bit 7—Reserved Bit 7 is reserved; it is always read as 1 and cannot be modified.
Section 13 LCD Controller/Driver Bit 4—Display Data Control (DISP) Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless of the LCD RAM contents. Bit 4 DISP Description 0 Blank data is displayed 1 LCD RAM data is display (initial value) Bits 3 to 0—Frame Frequency Select 3 to 0 (CKS3 to CKS0) Bits 3 to 0 select the operating clock and the frame frequency.
Section 13 LCD Controller/Driver 13.2.3 LCD Control Register 2 (LCR2) Bit 7 6 5 4 3 2 1 0 LCDAB — — — CDS3* CDS2* CDS1* CDS0* Initial value 0 1 1 — 0 0 0 0 Read/Write R/W — — R/W R/W R/W R/W R/W Note: * Applies to the H8/38124 Group only. On the H8/38024, H8/38024S, and H8/38024F-ZTAT Group, these bits are reserved like bit 4. LCR2 is an 8-bit read/write register which controls switching between the A waveform and B waveform and removal of split-resistance.
Section 13 LCD Controller/Driver Bits 3 to 0—Removal of Split-Resistance Control These bits control whether the split-resistance is removed or connected. Note that on products other than the H8/38124 Group, these bits are reserved like bit 4. Bit 3 CDS3 Bit 2 CDS2 Bit 1 CDS1 Bit 0 CDS0 0 0 0 0 1 1 Description (initial value) Split-resistance connected 0 1 1 0 0 1 0 1 1 0 0 1 Split-resistance removed 0 Split-resistance connected 1 1 0 0 0 1 1 1 1 0 1 Rev. 8.00 Mar.
Section 13 LCD Controller/Driver 13.2.4 Clock Stop Register 2 (CKSTPR2) Bit 7 6 5 LVDCKSTP* ⎯ ⎯ Initial value 1 1 1 1 1 1 1 1 Read/Write R/W ⎯ ⎯ R/W R/W R/W R/W R/W 4 3 2 1 0 PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP Note: * Bits 6 and 5 are also reserved on products other than the H8/38124 Group. CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral modules. Only the bit relating to the LCD controller/driver is described here.
Section 13 LCD Controller/Driver 13.3 Operation 13.3.1 Settings up to LCD Display To perform LCD display, the hardware and software related items described below must first be determined. Hardware Settings a. Using 1/2 duty When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 13.2. VCC V1 V2 V3 VSS Figure 13.2 Handling of LCD Drive Power Supply when Using 1/2 Duty b.
Section 13 LCD Controller/Driver Software Settings a. Duty selection Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits DTS1 and DTS0. b. Segment selection The segment drivers to be used can be selected with bits SGS3 to SGS0. c. Frame frequency selection The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency should be selected in accordance with the LCD panel specification.
Section 13 LCD Controller/Driver 13.3.2 Relationship between LCD RAM and Display The relationship between the LCD RAM and the display segments differs according to the duty cycle. LCD RAM maps for the different duty cycles are shown in figures 13.3 to 13.6. After setting the registers required for display, data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM, and display is started automatically when turned on.
Section 13 LCD Controller/Driver Bit 7 Bit 6 Bit 5 Bit 4 H'F740 SEG2 SEG2 H'F74F SEG32 COM3 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 SEG1 SEG1 SEG1 SEG32 SEG32 SEG31 SEG31 SEG31 COM2 COM1 COM3 COM2 COM1 Space not used for display Figure 13.4 LCD RAM Map (1/3 Duty) Rev. 8.00 Mar.
Section 13 LCD Controller/Driver H'F740 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 Display space SEG32 SEG32 SEG31 SEG31 SEG30 SEG30 SEG29 SEG29 H'F747 Space not used for display H'F74F COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 Figure 13.
Section 13 LCD Controller/Driver 1 frame 1 frame M M Data Data V1 V2 V3 VSS COM1 V1 V2 V3 VSS V1 V2 V3 VSS COM2 COM3 V1 V2 V3 VSS V1 V2 V3 VSS COM4 SEGn V1 V2 V3 VSS COM1 V1 V2 V3 VSS V1 V2 V3 VSS COM2 COM3 V1 V2 V3 VSS SEGn (a) Waveform with 1/4 duty (b) Waveform with 1/3 duty 1 frame 1 frame M M Data Data V1 COM1 V1 V2, V3 VSS COM1 COM2 V1 V2, V3 VSS SEGn SEGn V1 V2, V3 VSS (c) Waveform with 1/2 duty VSS V1 VSS (d) Waveform with static output M: LCD alternation signa
Section 13 LCD Controller/Driver 1 frame 1 frame 1 frame 1 frame 1 frame M M Data Data V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS COM1 COM2 COM3 COM4 V1 V2 V3 VSS SEGn 1 frame 1 frame 1 frame 1 frame V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS COM1 COM2 COM3 V1 V2 V3 VSS SEGn (a) Waveform with 1/4 duty 1 frame 1 frame (b) Waveform with 1/3 duty 1 frame 1 frame 1 frame 1 frame 1 frame M M Data Data V1 COM1 V1 V2, V3 VSS COM1 COM2 V1 V2, V3 VSS SEGn SEGn V1 V2,
Section 13 LCD Controller/Driver Table 13.3 Output Levels Data 0 0 1 1 M 0 1 0 1 Common output V1 VSS V1 VSS Segment output V1 VSS VSS V1 Common output V2, V3 V2, V3 V1 VSS Segment output V1 VSS VSS V1 Static 1/2 duty 1/3 duty 1/4 duty Common output V3 V2 V1 VSS Segment output V2 V3 VSS V1 Common output V3 V2 V1 VSS Segment output V2 V3 VSS V1 M: LCD alternation signal 13.3.
Section 13 LCD Controller/Driver Table 13.4 Power-Down Modes and Display Operation Reset Active Sleep Watch Subactive Subsleep Module Standby Standby φ Runs Runs Runs Stops Stops Stops Stops Stops*4 φw Runs Runs Runs Runs Runs Runs Stops*1 Stops*4 Stops Stops Stops Stops Stops*2 Stops Stops*2 Stops Mode Clock Display ACT = 0 operation ACT = 1 Stops Functions Functions Functions Stops *3 Functions Stops *3 Functions *3 Notes: 1.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) 14.1 Overview This LSI can include a power-on reset circuit and low-voltage detection circuit. The low-voltage detection circuit consists of two circuits: LVDI (interrupt by low voltage detect) and LVDR (reset by low voltage detect) circuits.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Two pairs of detection levels for reset generation voltage are available: when only the LVDR circuit is used, or when the LVDI and LVDR circuits are both used. In addition, power supply rise/drop detection voltages and a detection voltage reference voltage may be input from an external source, allowing the detection level to be set freely by the user. 14.1.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) 14.1.3 Pin Description The pins of the power-on reset circuit and low-voltage detection circuit are listed in table 14.1. Table 14.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) LVDCR is an 8-bit read/write register. It is used to control whether or not the low-voltage detection circuit is used, settings for external input of power supply rise and drop detection voltages, the LVDR detection level setting, enabling or disabling of resets triggered by the lowvoltage detection reset circuit (LVDR), and enabling or disabling of interrupts triggered by power supply voltage drops or rises.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Bit 3—LVDR Detection Level Select (LVDSEL) This bit is used to select the LVDR detection level. Select 2.3 V (typical) reset if voltage rise and drop detection interrupts are to be used. For reset detection only, Select 3.3 V (typical) reset. Bit 3 LVDSEL Description 0 Reset detection voltage 2.3 V (typ.) 1 Reset detection voltage 3.3 V (typ.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Table 14.3 shows the relationship between LVDCR settings and function selections. Refer to table 14.3 when making settings to LVDCR. Table 14.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Bits 6 to 4—Reserved These bits are read/write enabled reserved bits. Bit 3—Reference Voltage External Input Select (VREFSEL) This bit is used to select the reference voltage. Bit 3 VREFSEL Description 0 The on-chip circuit is used to generate the reference voltage 1 The reference voltage is input to the Vref pin from an external source (initial value) Bit 2—Reserved This bit is reserved.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) 14.2.3 Low-Voltage Detection Counter (LVDCNT) Bit 7 6 5 4 3 2 1 0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R LVDCNT is a read-only 8-bit up-counter. Counting begins when 1 is written to LVDE.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) 14.3 14.3.1 Operation Power-On Reset Circuit Figure 14.2 shows the timing of the operation of the power-on reset circuit. As the power-supply voltage rises, the capacitor which is externally connected to the RES pin is gradually charged via the on-chip pull-up resistor (typ. 100 kΩ). Since the state of the RES pin is transmitted within the chip, the prescaler S and the entire chip are in their reset states.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) tPWON Vcc Vpor Vss RES Vss PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 14.2 Operational Timing of Power-On Reset Circuit 14.3.2 Low-Voltage Detection Circuit LVDR (Reset by Low Voltage Detect) Circuit: Figure 14.3 shows the timing of the LVDR function. The LVDR enters the module-standby state after a power-on reset is canceled.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) VCC Vreset VLVDRmin VSS LVDRES PSS-reset signal OVF Internal reset signal 131,072 cycles PSS counter starts Reset released Figure 14.3 Operational Timing of LVDR Circuit LVDI (Interrupt by Low Voltage Detect) Circuit: Figure 14.4 shows the timing of LVDI functions. The LVDI enters the module-standby state after a power-on reset is canceled.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) When the power-supply voltage does not fall below Vreset1 (typ. = 2.3 V) voltage but rises above Vint (U) (typ. = 4.0 V) voltage, the LVDI sets the LVDINT signal to 1. If the LVDUE bit is 1 at this time, the LVDUF bit in LVDSR is set to 1 and an IRQ0 interrupt request is simultaneously generated. If the power supply voltage (Vcc) falls below Vreset1 (typ. = 2.3 V) voltage, the LVDR function is performed.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) External power supply voltage extD input voltage extU input voltage (1) (2) Vexd (3) (4) Vreset1 VSS LVDINTD LVDDF LVDINTU LVDUF IRQ0 interrupt generated IRQ0 interrupt generated Figure 14.5 Operational Timing of Low-Voltage Detection Interrupt Circuit (Using Pins Vref, extD, and extU) Rev. 8.00 Mar.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Figure 14.6 shows a usage example for the LVD function employing pins Vref, extD, and extU. LVDCR On-chip ladder resistor R1 R2 D1 External power supply voltage R1 = 517 kΩ U1 D2 U2 + − LVDRES + − LVDINT Interrupt controller extD R2 = 33 kΩ LVDSR Interrupt request extU R3 = 450 kΩ Vref External reference voltage 1.3 V On-chip reference voltage generator Setting conditions: • Vref = 1.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Resistance Value Calculation Table Ex. No Vref (V) R (kΩ) Vreset1 Vint(D) Vint(U) R1 (kΩ) R2 (kΩ) R3 (kΩ) 1 1.30 1000 2.5 2.7 2.9 517 33 450 2 1.41 1000 2.7 2.9 3 514 16 470 3 1.57 1000 3 3.2 3.5 511 42 447 4 2.09 1000 4 4.5 4.7 536 20 444 4.
Section 14 Power-On Reset and Low-Voltage Detection Circuits (H8/38124 Group Only) Operation and Cancellation Setting Procedure Using LVDR and LVDI: Settings should be made as indicated below in order to ensure proper operation of the low voltage detection circuit or to cancel operation. Figure 14.7 shows the setting timing for low voltage detection circuit operation and cancellation. 1. To turn on the low voltage detection circuit, first set the LVDE bit in LVDCR to 1. 2.
Section 15 Power Supply Circuit (H8/38124 Group Only) Section 15 Power Supply Circuit (H8/38124 Group Only) This LSI incorporates an internal power supply step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant level of approximately 3.0 V, independently of the voltage of the power supply connected to the external VCC pin. As a result, the current consumed when an external power supply is used at 3.
Section 15 Power Supply Circuit (H8/38124 Group Only) 15.2 When Not Using Internal Power Supply Step-Down Circuit When the internal power supply step-down circuit is not used, connect the external power supply to the CVCC pin and VCC pin, as shown in figure 15.2. The external power supply is then input directly to the internal power supply. The permissible range for the power supply voltage is 2.7 V to 3.6 V. Operation cannot be guaranteed if a voltage outside this range (less than 3.0 V or more than 3.
Section 16 Electrical Characteristics Section 16 Electrical Characteristics 16.1 H8/38024 Group ZTAT Version and Mask ROM Version Absolute Maximum Ratings Table 16.1 lists the absolute maximum ratings. Table 16.1 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +7.0 V * Analog power supply voltage AVCC –0.3 to +7.0 V Programming voltage VPP –0.3 to +13.0 V Input voltage Ports other than Port B and IRQAEC Vin –0.3 to VCC +0.3 V Port B AVin –0.
Section 16 Electrical Characteristics 16.2 H8/38024 Group ZTAT Version and Mask ROM Version Electrical Characteristics 16.2.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range 38.4 fW (kHz) fosc (MHz) 16.0 10.0 32.768 4.0 2.0 1.8 2.7 4.5 5.5 VCC (V) 1.8 3.0 5.5 4.5 VCC (V) • Active (high-speed) mode • All operating • Sleep (high-speed) mode Note: 2.
Section 16 Electrical Characteristics Power Supply Voltage and Operating Frequency Range 8.0 5.0 16.384 2.0 1.0 (0.5) 9.6 1.8 2.7 4.5 5.5 VCC (V) • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz. φSUB (kHz) φ (MHz) 19.2 8.192 4.8 4.096 1.8 3.6 5.
Section 16 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Operating Range 1000 φ (kHz) φ (MHz) 5.0 1.0 625 500 (0.5) 1.8 2.7 4.5 5.5 AVCC (V) 1.8 2.7 • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode Note: 3. When AVCC = 1.8 V to 2.7 V, the operating range is limited to φ = 1.0 MHz when using an oscillator, and is φ = 0.5 MHz to 1.0 MHz when using an external clock. Rev. 8.00 Mar.
Section 16 Electrical Characteristics 16.2.2 DC Characteristics Table 16.2 lists the DC characteristics of the H8/38024. Table 16.2 DC Characteristics VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including subactive mode) unless otherwise indicated. Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Input high voltage VIH RES, 0.8 VCC WKP0 to WKP7, 0.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Input low voltage VIL –0.3 — 0.2 VCC V –0.3 — 0.1 VCC –0.3 — 0.3 VCC –0.3 — 0.2 VCC OSC1 –0.3 — 0.2 VCC –0.3 — 0.1 VCC X1 –0.3 — 0.1 VCC V VCC = 1.8 V to 5.5 V P13, P14, P16, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PB0 to PB7 –0.3 — 0.3 VCC V VCC = 4.0 V to 5.5 V –0.3 — 0.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Output low voltage VOL P13, P14, P16, P17, P40 to P42 — Typ Max Unit Test Condition — 0.6 V VCC = 4.0 V to 5.5 V IOL = 1.6 mA — — 0.5 IOL = 0.4 mA P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 — — 0.5 IOL = 0.4 mA P30 to P37 — — 1.5 VCC = 4.0 V to 5.5 V IOL = 10 mA — — 0.6 VCC = 4.0 V to 5.5 V IOL = 1.6 mA — — 0.5 IOL = 0.4 mA — — 0.5 VCC = 2.2 to 5.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Pull-up MOS current –Ip 50.0 — 300.0 µA — 35.0 — All input pins except power supply, RES, P43, PB0 to PB7 — — 15.0 IRQAEC — — 30.0 RES — — 80.0 *2 — — 15.0 *1 — — 50.0 *2 — — 15.0 *1 PB0 to PB7 — — 15.0 IOPE1 VCC — 7.0 10.0 mA Active (high-speed) *3 *4 mode VCC = 5 V, fOSC = 10 MHz IOPE2 VCC — 2.2 3.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Watch mode current dissipation IWATCH 3.8 6.0 µA *2 *3 *4 2.8 6.0 VCC — *1 *3 *4 Standby mode current dissipation ISTBY VCC — 1.0 5.0 µA RAM data retaining voltage VRAM VCC 1.5 — — V Allowable output low current (per pin) IOL Output pins except port 3 and 9 — — 2.0 mA Port 3 — — 10.0 Output pins except port 9 — — 0.5 P90 to P92 — — 25.0 — — 15.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Allowable ∑ – IOH output high current (total) All output pins Typ Max Unit Test Condition — — 15.0 mA — — 10.0 Notes VCC = 4.0 V to 5.5 V Except the above Notes: Connect the TEST pin to VSS. 1. Applies to the Mask ROM products. 2. Applies to the HD64738024. 3. Pin states during current measurement.
Section 16 Electrical Characteristics 16.2.3 AC Characteristics Table 16.3 lists the control signal timing, and tables 16.4 lists the serial interface timing of the H8/38024. Table 16.3 Control Signal Timing VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including subactive mode) unless otherwise indicated.
Section 16 Electrical Characteristics Item External clock high width External clock low width External clock rise time External clock fall time Pin RES low width Min Typ Max Unit Test Condition tCPH 25 — — ns VCC = 4.5 V to 5.5 V Figure 16.2 40 — — tCPL tCPr tCPf tREL Input pin high width tIH Input pin low width Values Applicable Symbol Pins tIL OSC1 Reference Figure VCC = 2.7 V to 5.5 V 100 — — X1 — 15.26 or 13.02 — µs Except the above OSC1 25 — — ns VCC = 4.
Section 16 Electrical Characteristics Item Applicable Symbol Pins UD pin minimum transition width tUDH tUDL UD Values Min Typ Max Unit 4 — — tcyc tsubcyc Test Condition Reference Figure Figure 16.7 Notes: 1. Selected with SA1 and SA0 of system control register 2 (SYSCR2). 2. The figure in parentheses applies when an external clock is used. 3. After powering on, hold VCC at 2.2 V to 5.5 V until the chip's oscillation settling time has elapsed. Table 16.
Section 16 Electrical Characteristics 16.2.4 A/D Converter Characteristics Table 16.5 shows the A/D converter characteristics of the H8/38024. Table 16.5 A/D Converter Characteristics VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) unless otherwise indicated. Item Applicable Symbol Pins Values Min Typ Max Unit Analog power AVCC supply voltage AVCC 1.8 — 5.
Section 16 Electrical Characteristics Item Absolute accuracy Conversion time Applicable Symbol Pins Values Min Typ Max Unit Test Condition — — ±3.0 LSB AVCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V — — ±6.0 AVCC = 2.0 V to 5.5 V VCC = 2.0 V to 5.5 V — — ±8.0 Except the above 12.4 — 124 62 — 124 µs Reference Figure *4 AVCC = 2.7 V to 5.5 V VCC = 2.7 V to 5.5 V Except the above Notes: 1. Set AVCC = VCC when the A/D converter is not used. 2.
Section 16 Electrical Characteristics 16.2.5 LCD Characteristics Table 16.6 shows the LCD characteristics. Table 16.6 LCD Characteristics VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications), Ta = +75°C (Die) (including subactive mode) unless otherwise specified.
Section 16 Electrical Characteristics 16.3 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Absolute Maximum Ratings Table 16.7 lists the absolute maximum ratings. Table 16.7 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +4.3 V *1 Analog power supply voltage AVCC –0.3 to +4.3 V Input voltage Ports other than Port B and IRQAEC Vin –0.3 to VCC +0.3 V Port B AVin –0.3 to AVCC +0.3 V IRQAEC HVin –0.3 to +7.
Section 16 Electrical Characteristics 16.4 H8/38024 Group F-ZTAT Version and H8/38024R Group F-ZTAT Version Electrical Characteristics 16.4.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range fW (kHz) fosc (MHz) 38.4 10.0 32.768 2.0 2.7 3.
Section 16 Electrical Characteristics Power Supply Voltage and Operating Frequency Range 19.2 16.384 1.0 (0.5) 9.6 2.7 3.6 VCC (V) • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz. φSUB (kHz) φ (MHz) 5.0 8.192 4.8 4.096 2.7 3.
Section 16 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Operating Range φ (kHz) φ (MHz) 5.0 1.0 625 500 (0.5) 2.7 3.6 AVCC (V) 2.7 • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode Rev. 8.00 Mar. 09, 2010 Page 468 of 658 REJ09B0042-0800 3.
Section 16 Electrical Characteristics 16.4.2 DC Characteristics Table 16.8 lists the DC characteristics of the HD64F38024 and HD64F38024R. Table 16.8 DC Characteristics VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Input high voltage VIH RES, 0.9 VCC WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK32 — VCC + 0.3 V IRQ1 0.9 VCC — AVCC + 0.3 V RXD32, UD 0.8 VCC — VCC + 0.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Input low voltage VIL Output high VOH voltage Typ Max Unit Test Condition RES, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, P95*5, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK32 –0.3 — 0.1 VCC V RXD32, UD –0.3 — 0.2 VCC V OSC1 –0.3 — 0.1 VCC V X1 –0.3 — 0.1 VCC V P13, P14, P16, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PB0 to PB7 –0.3 — 0.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Output low voltage VOL Input/output | IIL | leakage current Pull-up MOS current –Ip Input CIN capacitance Typ Max Unit Test Condition Notes P13, P14, P16, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 — — 0.5 V IOL = 0.4 mA P90 to P92 — — 0.5 V IOL = 25 mA *1 IOL = 10 mA *2 P93 to P95 — — 0.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Active mode current dissipation IOPE1 — 1.2 — mA Active (high-speed) *3 *4 mode VCC = 3 V, Max. fOSC = 2 MHz guideline = 1.1 × typ. — 1.8 — mA Active (high-speed) *3 *4 mode VCC = 3 V, Max. fOSC = 4 MHz guideline = 1.1 × typ. — 4.0 6.0 mA Active (high-speed) *3 *4 mode VCC = 3 V, fOSC = 10 MHz — 0.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Sleep mode ISLEEP current dissipation VCC — Typ Max Unit Test Condition Notes 1.0 — mA *3 *4 VCC= 3 V, fOSC= 2 MHz Max. guideline = 1.1 × typ. — 1.5 — mA VCC= 3 V, fOSC= 4 MHz *3 *4 Max. guideline = 1.1 × typ. Subactive mode current dissipation Subsleep mode current dissipation ISUB ISUBSP VCC VCC — 3.2 4.8 mA VCC= 3 V, fOSC= 10 MHz *3 *4 — 10 — µA VCC = 2.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Watch mode current dissipation IWATCH 2.0 — µA *3 *4 Standby mode current dissipation ISTBY VCC VCC — — 2.6 — µA VCC = 2.7 V, Ta = 25°C 32 kHz crystal resonator LCD not used — 2.0 6.0 µA VCC = 2.7 V, 32 kHz External Clock LCD not used — 2.6 6.0 µA VCC = 2.7 V, 32 kHz crystal resonator LCD not used — 0.3 — µA VCC = 3.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Allowable –IOH output high current (per pin) All output pins — — 0.2 mA ∑ – IOH Allowable output high current (total) All output pins — — 10.0 mA Notes Notes: Connect the TEST pin to VSS. 1. Applied when the PIOFF bit in the port mode register 9 is 0. 2. Applied when the PIOFF bit in the port mode register 9 is 1. 3. Pin states during current measurement.
Section 16 Electrical Characteristics 16.4.3 AC Characteristics Table 16.9 lists the control signal timing, and tables 16.10 lists the serial interface timing of the H8/38024F. Table 16.9 Control Signal Timing VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V Values Applicable Symbol Pins Min Typ Max Unit System clock oscillation frequency fOSC OSC1, OSC2 2.0 — 10.
Section 16 Electrical Characteristics Values Applicable Symbol Pins Min Typ Max Unit External clock high width tCPH OSC1 40 — — ns X1 — 15.26 or 13.02 — µs External clock low width tCPL OSC1 40 — — ns X1 — 15.26 or 13.02 — µs External clock rise time tCPr OSC1 — — 10 ns X1 — — 55.0 ns External clock fall time tCPf OSC1 — — 10 ns X1 — — 55.
Section 16 Electrical Characteristics Table 16.10 Serial Interface (SCI3) Timing VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V Values Item Input clock cycle Asynchronous Symbol Min Typ Max Unit tscyc 4 — — 6 — — tcyc or t Synchronous Test Conditions Reference Figure Figure 16.5 subcyc Input clock pulse width tSCKW 0.4 — 0.6 tscyc Figure 16.5 Transmit data delay time (synchronous) tTXD — — 1 tcyc or tsubcyc Figure 16.
Section 16 Electrical Characteristics 16.4.4 A/D Converter Characteristics Table 16.11 shows the A/D converter characteristics of the H8/38024F. Table 16.11 A/D Converter Characteristics VCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V Item Applicable Symbol Pins Values Min Typ Max Unit Analog power AVCC supply voltage AVCC 2.7 — 3.6 V Analog input voltage AN0 to AN7 – 0.3 — AVCC + 0.3 V AVCC — — 1.
Section 16 Electrical Characteristics 16.4.5 LCD Characteristics Table 16.12 shows the LCD characteristics. Table 16.12 LCD Characteristics VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V Item Applicable Symbol Pins Min Values Test Typ Max Unit Conditions Segment driver drop voltage VDS SEG1 to SEG32 — — 0.6 V Common driver drop voltage VDC COM1 to COM4 — — 0.3 V 0.5 3.0 9.0 MΩ 1.5 3.0 7.0 2.2 — 3.
Section 16 Electrical Characteristics 16.4.6 Flash Memory Characteristics Table 16.13 lists the flash memory characteristics. Table 16.13 Flash Memory Characteristics AVCC = 2.7 V to 3.6 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 3.6 V (operating voltage range in reading), VCC = 3.0 V to 3.
Section 16 Electrical Characteristics Notes: 1. 2. Make the time settings in accordance with the program/erase algorithms. The programming time for 128 bytes. (Indicates the total time for which the P bit in flash memory control register 1 (FLMCR1) is set. The program-verify time is not included.) 3. The time required to erase one block. (Indicates the time for which the E bit in flash memory control register 1 (FLMCR1) is set. The erase-verify time is not included.) 4.
Section 16 Electrical Characteristics 16.5 H8/38024S Group Mask ROM Version Absolute Maximum Ratings Table 16.15 lists the absolute maximum ratings. Table 16.15 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +4.3 V *1 Analog power supply voltage AVCC –0.3 to +4.3 V Input voltage Ports other than Port B Vin –0.3 to VCC +0.3 V Port B AVin –0.3 to AVCC +0.3 V Port 9 pin voltage VP9 –0.3 to VCC +0.
Section 16 Electrical Characteristics 16.6 H8/38024S Group Mask ROM Version Electrical Characteristics 16.6.1 Power Supply Voltage and Operating Range The power supply voltage and operating range are indicated by the shaded region in the figures. Power Supply Voltage and Oscillator Frequency Range fW (kHz) fosc (MHz) 38.4 10.0 32.768 4.0 2.0 1.8 2.7 3.
Section 16 Electrical Characteristics Power Supply Voltage and Operating Frequency Range 5.0 16.384 2.0 1.0 (0.5) 9.6 1.8 2.7 3.6 VCC (V) • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) Note: 1. The figure in parentheses is the minimum operating frequency when an external clock is input. When using an oscillator, the minimum operating frequency (φ) is 1 MHz. φSUB (kHz) φ (MHz) 19.2 8.192 4.8 4.096 1.8 2.7 3.
Section 16 Electrical Characteristics Analog power Supply Voltage and A/D Converter Operating Range φ (kHz) φ (MHz) 5.0 1.0 625 500 (0.5) 1.8 2.7 3.6 AVCC (V) 1.8 2.7 • Active (high-speed) mode • Active (medium-speed) mode • Sleep (high-speed) mode • Sleep (medium-speed) mode Rev. 8.00 Mar. 09, 2010 Page 486 of 658 REJ09B0042-0800 3.
Section 16 Electrical Characteristics 16.6.2 DC Characteristics Table 16.16 lists the DC characteristics of the H8/38024S. Table 16.16 DC Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Input high voltage VIH RES, 0.9 VCC WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK32 — VCC + 0.3 V IRQ1 0.9 VCC — AVCC + 0.3 V RXD32, UD 0.8 VCC — VCC + 0.3 V OSC1 0.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Input low voltage VIL Output high VOH voltage Typ Max Unit Test Condition RES, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK32 –0.3 — 0.1 VCC V RXD32, UD –0.3 — 0.2 VCC V OSC1 –0.3 — 0.1 VCC V X1 –0.3 — 0.1 VCC V P13, P14, P16, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PB0 to PB7 –0.3 — 0.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Output low voltage VOL Input/output | IIL | leakage current Pull-up MOS current –Ip Input CIN capacitance Typ Max Unit Test Condition P13, P14, P16, P17, P30 to P37, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 — — 0.5 V IOL = 0.4 mA P90 to P95 — — 0.5 V IOL = 10 mA VCC = 2.2 V to 3.6 V — — 0.5 V IOL = 8 mA VCC = 1.8 V to 3.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Active mode current dissipation IOPE1 — 0.2 — mA Active (high-speed) *1 *2 mode VCC = 1.8 V, Max. fOSC = 1 MHz guideline = 1.1 × typ. — 0.6 — mA Active (high-speed) *1 *2 mode VCC = 3 V, Max. fOSC = 2 MHz guideline = 1.1 × typ. — 1.2 — mA Active (high-speed) mode VCC = 3 V, fOSC = 4 MHz IOPE2 VCC VCC Notes *1 *2 Max. guideline = 1.1 × typ. — 3.1 6.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Active mode current dissipation IOPE2 0.2 — mA *1 *2 Sleep mode ISLEEP current dissipation VCC VCC — Active (mediumspeed) mode VCC = 3 V, fOSC = 4 MHz φosc/128 Max. guideline = 1.1 × typ. — 0.6 1.8 mA Active (mediumspeed) mode VCC = 3 V, fOSC = 10 MHz φosc/128 *1 *2 — 0.08 — mA VCC= 1.8 V, fOSC= 1 MHz *1 *2 Max. guideline = 1.1 × typ. — 0.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Subactive mode current dissipation ISUB 6.2 — µA *1 *2 Subsleep mode current dissipation Watch mode current dissipation ISUBSP IWATCH VCC VCC VCC — VCC = 1.8 V, LCD on 32 kHz External Clock (φSUB=φw/2) — 5.7 — µA VCC = 1.8 V, LCD on 32 kHz crystal resonator (φSUB=φw/2) — 4.4 — µA VCC = 2.7 V, LCD on 32 kHz crystal resonator (φSUB=φw/8) — 10 40 µA VCC = 2.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Watch mode current dissipation IWATCH 2.3 — µA VCC = 2.7 V, Ta = 25°C 32 kHz crystal resonator LCD not used *1 *2 *1 *2 Standby mode current dissipation ISTBY VCC VCC — — 2.0 6.0 µA VCC = 2.7 V, 32 kHz External Clock LCD not used — 2.3 6.0 µA VCC = 2.7 V, 32 kHz crystal resonator LCD not used — 0.1 — µA VCC = 1.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Allowable ∑ – IOH output high current (total) All output pins — Typ Max Unit Test Condition — 10.0 mA Notes Notes: Connect the TEST pin to VSS. 1. Pin states during current measurement.
Section 16 Electrical Characteristics 16.6.3 AC Characteristics Table 16.17 lists the control signal timing, and tables 16.10 lists the serial interface timing of the H8/38024S. Table 16.17 Control Signal Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V Values Applicable Symbol Pins Min Typ Max Unit Test Condition System clock oscillation frequency fOSC OSC1, OSC2 2.0 — 10.0 MHz VCC = 2.7 V to 3.6 V 2.0 — 4.
Section 16 Electrical Characteristics Item Oscillation stabilization time Min Typ Max Unit Test Condition trc — 20 45 µs Ceramic oscillator Figure 16.10 VCC = 2.2 V to 3.6 V — 80 — µs Ceramic oscillator Except the above — 0.8 2 ms Crystal oscillator VCC = 2.7 V to 3.6 V — 1.2 3 ms Crystal oscillator VCC = 2.2 V to 3.6 V — — 50 ms Except the above — — 2 s VCC = 2.2 V to 3.6 V — 4 — s Except the above OSC1 40 — — ns VCC = 2.7 V to 3.6 V Figure 16.
Section 16 Electrical Characteristics Item Applicable Symbol Pins Input pin high width tIH Input pin low width UD pin minimum transition width tIL tUDH tUDL Values Min Typ Max Unit 2 IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIC, TMIF, TMIG, ADTRG — — tcyc tsubcyc AEVL, AEVH — — tosc 2 IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIC, TMIF, TMIG, ADTRG — — tcyc tsubcyc AEVL, AEVH 0.5 — — tosc UD 4 — — tcyc tsubcyc 0.5 Test Condition Reference Figure Figure 16.
Section 16 Electrical Characteristics Table 16.18 Serial Interface (SCI3) Timing VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V Values Item Input clock cycle Asynchronous Symbol Min Typ Max Unit tscyc 4 — — 6 — — tcyc or t Synchronous Test Conditions Reference Figure Figure 16.5 subcyc Input clock pulse width tSCKW 0.4 — 0.6 tscyc Figure 16.5 Transmit data delay time (synchronous) tTXD — — 1 tcyc or tsubcyc Figure 16.
Section 16 Electrical Characteristics 16.6.4 A/D Converter Characteristics Table 16.19 shows the A/D converter characteristics of the H8/38024S. Table 16.19 A/D Converter Characteristics VCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V Item Applicable Symbol Pins Values Min Typ Max Unit Analog power AVCC supply voltage AVCC 1.8 — 3.6 V Analog input voltage AN0 to AN7 – 0.3 — AVCC + 0.3 V AVCC — — 1.
Section 16 Electrical Characteristics 3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes while the A/D converter is idle. 4. Conversion time: 62 μs. 16.6.5 LCD Characteristics Table 16.20 shows the LCD characteristics. Table 16.20 LCD Characteristics VCC = 1.8 V to 3.6 V, AVCC = 1.8 V to 3.6 V, VSS = AVSS = 0.0 V Item Applicable Symbol Pins Min Values Test Typ Max Unit Conditions Reference Figure Segment driver drop voltage VDS SEG1 to SEG32 — — 0.
Section 16 Electrical Characteristics 16.7 Absolute Maximum Ratings of H8/38124 Group F-ZTAT Version and Mask ROM Version Table 16.21 lists the absolute maximum ratings. Table 16.21 Absolute Maximum Ratings Item Symbol Value Unit Note Power supply voltage VCC –0.3 to +7.0 V *1 CVCC –0.3 to +4.3 V Analog power supply voltage AVCC –0.3 to +7.0 V Input voltage Other than port B Vin –0.3 to VCC +0.3 V Port B AVin –0.3 to AVCC +0.
Section 16 Electrical Characteristics 16.8 Electrical Characteristics of H8/38124 Group F-ZTAT Version and Mask ROM Version 16.8.1 Power Supply Voltage and Operating Ranges Power Supply Voltage and Oscillation Frequency Range (System Clock Oscillator Selected) fosc (MHz) fW (kHz) 20.0 32.768 2.0 2.7 5.5 VCC (V) 2.7 • Active (high-speed) mode • Sleep (high-speed) mode 5.
Section 16 Electrical Characteristics Power Supply Voltage and Operating Frequency Range (System Clock Oscillator Selected) 10.0 φ (MHz) 16.384 2.7 5.5 VCC (V) • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) φSUB (kHz) 1.0 8.192 4.096 2.7 5.5 VCC (V) • Subactive mode • Subsleep mode (except CPU) • Watch mode (except CPU) φ (kHz) 1250 15.625 2.7 5.5 VCC (V) • Active (medium-speed) mode • Sleep (medium-speed) mode (except A/D converter) Rev. 8.00 Mar.
Section 16 Electrical Characteristics Power Supply Voltage and Operating Frequency Range (On-Chip Oscillator Selected) φSUB (kHz) φ (MHz) 16.384 1.0 0.35 2.7 5.5 VCC (V) φ (kHz) • Active (high-speed) mode • Sleep (high-speed) mode (except CPU) 125 6.25 2.7 5.5 VCC (V) • Active (medium-speed) mode • Sleep (medium-speed) mode (except A/D converter) Rev. 8.00 Mar. 09, 2010 Page 504 of 658 REJ09B0042-0800 8.192 4.096 2.7 • Subactive mode • Subsleep mode (except CPU) • Watch mode (except CPU) 5.
Section 16 Electrical Characteristics Analog Power Supply Voltage and A/D Converter Operating Range (System Clock Oscillator Selected) φ (kHz) φ (MHz) 10.0 1000 500 1.0 2.7 2.7 5.5 AVCC (V) 5.5 AVCC (V) • Active (medium-speed) mode • Sleep (medium-speed) mode • Active (high-speed) mode • Sleep (high-speed) mode Analog Power Supply Voltage and A/D Converter Operating Range (On-Chip Oscillator Selected) φ (kHz) φ (MHz) 1.0 125 6.25 0.35 2.7 5.
Section 16 Electrical Characteristics 16.8.2 DC Characteristics Table 16.22 lists the DC characteristics. Table 16.22 DC Characteristics VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Values Item Symbol Input high VIH voltage Applicable Pins Max Unit Test Condition RES, VCC × 0.8 — WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, VCC × 0.9 — TMIC, TMIF, TMIG, ADTRG, SCK32 VCC + 0.3 V VCC = 4.0 V to 5.5 V VCC + 0.3 Other than above IRQ1 VCC × 0.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Input low voltage VIL RES, WKP0 to WKP7, IRQ0, IRQ1, IRQ3, IRQ4, IRQAEC, P95*5, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK32 – 0.3 — VCC × 0.2 V VCC = 4.0 V to 5.5 V – 0.3 — VCC × 0.1 – 0.3 — VCC × 0.3 – 0.3 — VCC × 0.2 OSC1 – 0.3 — VCC × 0.2 – 0.3 — VCC × 0.1 P13, P14, P17, P30 to P37, P40 to P43, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3, PB0 to PB7 – 0.
Section 16 Electrical Characteristics Values Item Symbol Output low VOL voltage Applicable Pins Min Typ Max Unit Test Condition P13, P14, P17, P40 to P42, P50 to P57, P60 to P67, P70 to P77, P80 to P87, PA0 to PA3 — — 0.6 V VCC = 4.0 V to 5.5 V P30 to P37 Notes IOL = 1.6 mA — — 0.5 — — 1.0 IOL = 0.4 mA VCC = 4.0 V to 5.5 V IOL = 10 mA — — 0.6 VCC = 4.0 V to 5.5 V IOL = 1.6 mA P90 to P95 — — 0.5 — — 1.5 IOL = 0.4 mA VCC = 4.0 V to 5.5 V IOL = 15 mA — — 1.0 VCC = 4.
Section 16 Electrical Characteristics Values Item Symbol Applicable Pins Min Typ Max Unit Test Condition Input capacitance Cin All input pins except power supply pin — — 15.0 pF f = 1 MHz, VIN = 0.0 V, Ta = 25°C VCC — 0.6 — mA Active (high-speed) mode VCC = 2.7 V, fOSC = 2 MHz IOPE1 Active mode current consumption — 1.0 Notes *1 *3 *4 Approx. max. value = 1.1 × Typ. *2 *3 *4 — Approx. max. value = 1.1 × Typ. — 0.8 — Active (high-speed) mode VCC = 5 V, fOSC = 2 MHz — 1.
Section 16 Electrical Characteristics Values Item Symbol Active IOPE2 mode current consumption Applicable Pins Min Typ Max Unit Test Condition Notes VCC — 0.2 — mA Active (mediumspeed) mode VCC = 2.7 V, fOSC = 2 MHz, φOSC/128 *1 *3 *4 — 0.5 Approx. max. value = 1.1 × Typ. *2 *3 *4 — Approx. max. value = 1.1 × Typ. — — 0.4 0.8 — Active (mediumspeed) mode VCC = 5 V, fOSC = 2 MHz, φOSC/128 *1 *3 *4 Approx. max. value = 1.1 × Typ. *2 *3 *4 — Approx. max. value = 1.1 × Typ. — 0.
Section 16 Electrical Characteristics Values Item Symbol ISLEEP Sleep mode current consumption Applicable Pins Min Typ Max Unit Test Condition Notes VCC — 0.3 — mA VCC = 2.7 V, fOSC = 2 MHz *1 *3 *4 — 0.8 Approx. max. value = 1.1 × Typ. *2 *3 *4 — Approx. max. value = 1.1 × Typ. — — 0.5 0.9 — VCC = 5 V, fOSC = 2 MHz *1 *3 *4 Approx. max. value = 1.1 × Typ. *2 *3 *4 — Approx. max. value = 1.1 × Typ. — Subactive ISUB mode current consumption VCC 0.
Section 16 Electrical Characteristics Values Item Applicable Pins Min Typ Max Unit Test Condition Notes Subsleep ISUBSP mode current consumption Symbol VCC — 4.0 16 µA VCC = 2.7 V, LCD on, 32-kHz crystal resonator used (φSUB = φW/2) *3 *4 Watch IWATCH mode current consumption VCC — 1.4 — µA VCC = 2.7 V, Ta = 25°C, 32-kHz crystal resonator used, LCD not used *1 *3 *4 VCC = 2.7 V, 32-kHz crystal resonator used, LCD not used *3 *4 VCC = 2.
Section 16 Electrical Characteristics Item Symbol Allowable output low current (per pin) IOL Allowable output low current (total) ∑IOL Allowable output high –IOH current (per pin) Allowable output high ∑–IOH current (total) Applicable Pins Values Min Test Condition Typ Max Unit Output pins — except ports 3 and 9 — 2.0 mA Port 3 — — 10.0 Output pins except port 9 — — 0.5 Port 9 — — 15.0 VCC = 4.0 V to 5.5 V — — 5.
Section 16 Electrical Characteristics 3.
Section 16 Electrical Characteristics 16.8.3 AC Characteristics Table 16.23 lists the control signal timing and table 16.24 lists the serial interface timing. Table 16.23 Control Signal Timing VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Item Symbol Applicable Pins System clock oscillation frequency fOSC OSC clock (φOSC) cycle time tOSC System clock (φ) cycle time Values Typ Max Unit OSC1, OSC2 2.0 — 20.0 MHz 0.7 — 2.0 OSC1, OSC2 50.
Section 16 Electrical Characteristics Item Symbol Input pin high width tIH Input pin low width tIL UD pin minimum transition width tUDH Applicable Pins Values Min Typ Max Unit IRQ0, IRQ1, 2 IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIC, TMIF, TMIG, ADTRG — — tcyc tsubcyc AEVL, AEVH 0.5 — — tOSC IRQ0, IRQ1, 2 IRQ3, IRQ4, IRQAEC, WKP0 to WKP7, TMIC, TMIF, TMIG, ADTRG — — tcyc tsubcyc AEVL, AEVH 0.5 — — tOSC UD — — tcyc tsubcyc 4 tUDL Test Condition Reference Figure Figure 16.
Section 16 Electrical Characteristics 16.8.4 A/D Converter Characteristics Table 16.25 shows the A/D converter characteristics. Table 16.25 A/D Converter Characteristics VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Values Applicable Min Pins Typ Max Unit Analog power supply AVCC voltage AVCC 2.7 — 5.5 V Analog input voltage AN0 to AN7 – 0.3 — AVCC + 0.3 V AVCC — — 1.
Section 16 Electrical Characteristics 16.8.5 LCD Characteristics Table 16.26 shows the LCD characteristics. Table 16.26 LCD Characteristics VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Item Symbol Segment driver step-down voltage Common driver step-down voltage VDS VDC LCD power supply split-resistance RLCD Liquid crystal display voltage VLCD Applicable Pins Values Reference Figure Min Typ Max Unit Test Condition SEG1 to SEG32 — — 0.
Section 16 Electrical Characteristics 16.8.6 Flash Memory Characteristics Table 16.27 Flash Memory Characteristics Condition: AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 5.5 V (range of operating voltage when reading), VCC = 3.0 V to 5.
Section 16 Electrical Characteristics Values Symbol Min Typ Max Unit Wait time after SWE-bit setting*1 x 1 — — µs Wait time after ESU-bit setting*1 y 100 — — µs Wait time after E-bit setting*1*6 z 10 — 100 ms Wait time after E-bit clear*1 α 10 — — µs Wait time after ESU-bit clear*1 β 10 — — µs Wait time after EV-bit setting*1 γ 20 — — µs Wait time after dummy write*1 ε 2 — — µs Wait time after EV-bit clear*1 η 4 — — µs Wait time after SWE-bit clear*1 θ
Section 16 Electrical Characteristics 16.8.7 Power Supply Voltage Detection Circuit Characteristics Table 16.28 Power Supply Voltage Detection Circuit Characteristics (1) VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Rated Values Item Symbol Min Typ Max Unit LVDR operation drop voltage* VLVDRmin 1.0 — — V LVD stabilization time TLVDON 150 — — µs Standby mode current consumption ISTBY — — 100 µA Test Conditions LVDE = 1 VCC = 5.
Section 16 Electrical Characteristics Table 16.30 Power Supply Voltage Detection Circuit Characteristics (3) Using on-chip reference voltage and detect voltage external input (VREFSEL = 0, VINTDSEL and VINTUSEL = 1) Rated Values Item Symbol Min Typ Max Unit extD/extU interrupt detection level Vexd 0.80 1.20 1.60 V extD/extU pin input 2 voltage* VextD* 1 VextU* –0.3 — VCC + 0.3 or AVCC + 0.3, whichever is lower V VCC = 2.7 to 3.3 V –0.3 — 3.6 or AVCC + 0.
Section 16 Electrical Characteristics Table 16.31 Power Supply Voltage Detection Circuit Characteristics (4) Using external reference voltage and ladder resistor (VREFSEL = 1, VINTDSEL = VINTUSEL = 0) Rated Values Typ Max Test Unit Condition Vint(D)*1 3.08 * (Vref1 – 0.1) 3.08 * Vref1 3.08 * (Vref1 + 0.1) V LVDSEL = 0 Vref input voltage (Vint(D)) Vref1*2 — 1.68 V Vint(D) Power supply rise detection voltage Vint(U)*1 3.33 * (Vref2 – 0.1) 3.33 * Vref2 3.33 * (Vref2 + 0.
Section 16 Electrical Characteristics Table 16. 32 Power Supply Voltage Detection Circuit Characteristics (5) Using external reference voltage and detect voltage external input (VREFSEL = VINTDSEL = VINTUSEL = 1) Rated Values Item Symbol Min Typ Max Unit Test Condition Comparator detection accuracy Vcdl 0.1 — — V | VextU – Vref | extD/extU pin input voltage VextD* Vref pin input voltage | VextD – Vref | –0.3 — VCC + 0.3 or AVCC + 0.3, whichever is lower V VCC = 2.7 to 3.3 V –0.
Section 16 Electrical Characteristics 16.8.9 Watchdog Timer Characteristics Table 16.34 Watchdog Timer Characteristics AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified Item Symbol On-chip oscillator overflow time tOVF Applicable Pins Rated Values Min Typ Max Unit Note Test Condition 0.2 0.4 — s * VCC = 5 V Note: * When the on-chip oscillator is selected, the timer counts from 0 to 255, indicating the time remaining until an internal reset is generated. 16.8.
Section 16 Electrical Characteristics 16.9 Operation Timing Figures 16.2 to 16.7 show timing diagrams. t OSC , tw VIH OSC1 x1 VIL t CPH t CPL t CPr t CPf Figure 16.2 Clock Input Timing RES VIL tREL Figure 16.3 RES Low Width IRQ0, IRQ1, IRQ3, IRQ4, TMIC, TMIF, TMIG, ADTRG, WKP0 to WKP7, IRQAEC, AEVL, AEVH VIH VIL t IL t IH Figure 16.4 Input Timing Rev. 8.00 Mar.
Section 16 Electrical Characteristics t SCKW SCK 32 t scyc Figure 16.5 SCK3 Input Clock Timing t scyc VIH or VOH* SCK 32 VIL or VOL* t TXD VOH* VOL* TXD32 (transmit data) t RXS t RXH RXD32 (receive data) Note: * Output timing reference levels Output high VOH = 1/2Vcc + 0.2 V Output low VOL = 0.8 V Load conditions are shown in figure 16.8. Figure 16.6 SCI3 Synchronous Mode Input/Output Timing Rev. 8.00 Mar.
Section 16 Electrical Characteristics VIH VIL UD tUDL tUDH Figure 16.7 UD Pin Minimum Transition Width Timing 16.10 Output Load Circuit VCC 2.4 kΩ Output pin 30 pF 12 kΩ Figure 16.8 Output Load Condition Rev. 8.00 Mar.
Section 16 Electrical Characteristics 16.11 Resonator Equivalent Circuit LS RS CS OSC1 OSC2 CO Ceramic Resonator Parameters Crystal Resonator Parameters Frequency (MHz) Frequency (MHz) 4 4.193 10 RS (max) 100 Ω 100 Ω 30 Ω RS (max) CO (max) 16 pF 16 pF 16 pF CO (max) 2 4 10 18.3 Ω 6.8 Ω 4.6 Ω 36.94 pF 36.72 pF 32.31 pF Figure 16.
Section 16 Electrical Characteristics 16.12 Usage Note The ZTAT, F-ZTAT, and mask ROM versions satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on.
Appendix A CPU Instruction Set Appendix A CPU Instruction Set A.
Appendix A CPU Instruction Set Table A.1 lists the H8/300L CPU instruction set. Table A.1 Instruction Set ⎯ ⎯ 2 MOV.B @aa:8, Rd B @aa:8 → Rd8 2 ⎯ ⎯ MOV.B @aa:16, Rd B @aa:16 → Rd8 4 ⎯ ⎯ MOV.B Rs, @Rd B Rs8 → @Rd16 MOV.B Rs, @(d:16, Rd) B Rs8 → @(d:16, Rd16) MOV.B Rs, @−Rd B Rd16−1 → Rd16 Rs8 → @Rd16 ⎯ ⎯ 2 ⎯ ⎯ 4 ⎯ ⎯ 2 MOV.B Rs, @aa:8 B Rs8 → @aa:8 2 ⎯ ⎯ MOV.B Rs, @aa:16 B Rs8 → @aa:16 4 ⎯ ⎯ MOV.W #xx:16, Rd W #xx:16 → Rd MOV.W Rs, Rd W Rs16 → Rd16 MOV.
Appendix A CPU Instruction Set 2 No. of States Implied @@aa @(d:8, PC) @aa: 8/16 @−Rn/@Rn+ @(d:16, Rn) @Rn ⎯ (1) ⎯ 2 ↔ ↔ ↔ ↔ B Rd8+#xx:8 +C → Rd8 ⎯ 2 ↔ ↔ ↔ ↔ W Rd16+Rs16 → Rd16 ADDX.B #xx:8, Rd 2 ↔ ↔ ADD.W Rs, Rd ⎯ 2 2 ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ B Rd8+#xx:8 → Rd8 B Rd8+Rs8 → Rd8 Condition Code I H N Z V C ↔ ↔ ADD.B #xx:8, Rd ADD.
Appendix A CPU Instruction Set 0 ↔ 2 0 ↔ 2 0 ↔ 2 0 2 0 2 0 ⎯ 2 0 ⎯ 2 0 ⎯ 2 0 ⎯ 2 0 ⎯ 2 Implied XOR.B Rs, Rd B Rd8⊕Rs8 → Rd8 2 ⎯ ⎯ NOT.B Rd B Rd → Rd 2 ⎯ ⎯ SHAL.B Rd B 2 ⎯ ⎯ 2 ⎯ ⎯ 2 ⎯ ⎯ 2 ⎯ ⎯ 0 2 ⎯ ⎯ 2 ⎯ ⎯ C 0 b7 SHAR.B Rd B B C b0 C 0 b7 SHLR.B Rd B b0 0 C b7 ROTXL.B Rd B b0 C b7 ROTXR.B Rd b0 B b7 0 ⎯ 2 0 ⎯ 2 b0 b7 SHLL.B Rd No.
Appendix A CPU Instruction Set No. of States Implied @@aa @(d:8, PC) @aa: 8/16 @−Rn/@Rn+ ⎯ ⎯ 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 2 ↔ 2 0 2 0 2 b0 B C b7 ⎯ ⎯ ↔ ROTR.B Rd I H N Z V C 2 ↔ ↔ b7 Condition Code ↔ ↔ C @(d:16, Rn) Operation @Rn B Rn ROTL.
Appendix A CPU Instruction Set B (Rn8 of @aa:8) → Z B (#xx:3 of Rd8) → C BLD #xx:3, @Rd B (#xx:3 of @Rd16) → C BLD #xx:3, @aa:8 B (#xx:3 of @aa:8) → C BILD #xx:3, Rd B (#xx:3 of Rd8) → C BILD #xx:3, @Rd B (#xx:3 of @Rd16) → C BILD #xx:3, @aa:8 B (#xx:3 of @aa:8) → C BST #xx:3, Rd B C → (#xx:3 of Rd8) BST #xx:3, @Rd B C → (#xx:3 of @Rd16) BST #xx:3, @aa:8 B C → (#xx:3 of @aa:8) BIST #xx:3, Rd B C → (#xx:3 of Rd8) BIST #xx:3, @Rd B C → (#xx:3 of @Rd16) BIST #xx:3, @aa:8 B C → (#xx:3 of
Appendix A CPU Instruction Set B C⊕(#xx:3 of Rd8) → C B C⊕(#xx:3 of @Rd16) → C BXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) → C BIXOR #xx:3, Rd B C⊕(#xx:3 of Rd8) → C BIXOR #xx:3, @Rd B C⊕(#xx:3 of @Rd16) → C BIXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) → C I H N Z V C ⎯ ⎯ ⎯ ⎯ ⎯ 4 ⎯ ⎯ ⎯ ⎯ ⎯ 2 ⎯ ⎯ ⎯ ⎯ ⎯ 4 ⎯ ⎯ ⎯ ⎯ ⎯ 4 ⎯ ⎯ ⎯ ⎯ ⎯ 2 ⎯ ⎯ ⎯ ⎯ ⎯ 4 ⎯ ⎯ ⎯ ⎯ ⎯ 4 No.
Appendix A CPU Instruction Set Condition Code I H N Z V C No. of States Implied @@aa @(d:8, PC) @aa: 8/16 @−Rn/@Rn+ @(d:16, Rn) @Rn Rn Operation #xx: 8/16 Mnemonic Operand Size Addressing Mode/ Instruction Length (bytes) JSR @Rn ⎯ SP−2 → SP PC → @SP PC ← Rn16 JSR @aa:16 ⎯ SP−2 → SP PC → @SP PC ← aa:16 JSR @@aa:8 ⎯ SP−2 → SP PC → @SP PC ← @aa:8 RTS ⎯ PC ← @SP SP+2 → SP 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ 8 RTE ⎯ CCR ← @SP SP+2 → SP PC ← @SP SP+2 → SP 2 SLEEP ⎯ Transit to sleep mode.
Appendix A CPU Instruction Set A.2 Operation Code Map Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the instruction code (bits 15 to 8 of the first instruction word). Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0. Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1. Rev. 8.00 Mar.
Rev. 8.00 Mar. 09, 2010 Page 540 of 658 REJ09B0042-0800 OR XOR AND MOV C D E F Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
Appendix A CPU Instruction Set A.3 Number of Execution States The tables here can be used to calculate the number of states required for instruction execution. Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write, etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction.
Appendix A CPU Instruction Set Table A.4 Number of Cycles in Each Instruction Instruction Mnemonic Instruction Fetch I ADD ADD.B #xx:8, Rd 1 ADDS ADDX AND ADD.B Rs, Rd 1 ADD.W Rs, Rd 1 ADDS.W #1, Rd 1 ADDS.W #2, Rd 1 ADDX.B #xx:8, Rd 1 ADDX.B Rs, Rd 1 AND.B #xx:8, Rd 1 Stack Branch Addr. Read Operation K J Byte Data Access L AND.
Appendix A CPU Instruction Set Instruction BILD BIOR BIST BIXOR BLD BNOT BOR BSET Mnemonic Instruction Fetch I Byte Data Access L BILD #xx:3, Rd 1 BILD #xx:3, @Rd 2 1 BILD #xx:3, @aa:8 2 1 BIOR #xx:3, Rd 1 BIOR #xx:3, @Rd 2 1 BIOR #xx:3, @aa:8 2 1 BIST #xx:3, Rd 1 BIST #xx:3, @Rd 2 2 BIST #xx:3, @aa:8 2 2 BIXOR #xx:3, Rd 1 BIXOR #xx:3, @Rd 2 1 BIXOR #xx:3, @aa:8 2 1 BLD #xx:3, Rd 1 BLD #xx:3, @Rd 2 1 BLD #xx:3, @aa:8 2 1 BNOT #xx:3, Rd 1 BNOT #xx:3, @Rd
Appendix A CPU Instruction Set Stack Branch Addr. Read Operation K J Byte Data Access L Instruction Mnemonic Instruction Fetch I BTST BTST Rn, @aa:8 2 BXOR BXOR #xx:3, Rd 1 BXOR #xx:3, @Rd 2 1 BXOR #xx:3, @aa:8 2 1 CMP. B #xx:8, Rd 1 CMP CMP. B Rs, Rd 1 CMP.W Rs, Rd 1 DAA DAA.B Rd 1 DAS DAS.B Rd 1 DEC DEC.B Rd 1 DIVXU DIVXU.B Rs, Rd 1 EEPMOV EEPMOV 2 INC INC.
Appendix A CPU Instruction Set Stack Branch Addr. Read Operation K J Byte Data Access L Word Data Access M Instruction Mnemonic Instruction Fetch I MOV MOV.W Rs, @Rd 1 MOV.W Rs, @(d:16, Rd) 2 1 MOV.W Rs, @–Rd 1 1 MOV.W Rs, @aa:16 2 1 MULXU MULXU.B Rs, Rd 1 NEG NEG.B Rd 1 NOP NOP 1 NOT NOT.B Rd 1 OR OR.B #xx:8, Rd 1 OR.B Rs, Rd 1 Internal Operation N 1 2 12 ORC ORC #xx:8, CCR 1 ROTL ROTL.B Rd 1 ROTR ROTR.B Rd 1 ROTXL ROTXL.B Rd 1 ROTXR ROTXR.
Appendix B Internal I/O Registers Appendix B Internal I/O Registers B.1 Addresses Upper Address: H'F0 Bit Names Lower Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'20 FLMCR1 — SWE ESU PSU EV PV E P ROM H'21 FLMCR2 FLER — — — — — — — H'22 FLPWCR PDWND — — — — — — — H'23 EBR — — — EB4 EB3 EB2 EB1 EB0 FENR FLSHE — — — — — — — H'24 H'25 H'26 H'27 H'28 H'29 H'2A H'2B H'2C H'2D H'2E H'2F Rev. 8.00 Mar.
Appendix B Internal I/O Registers Upper Address: H'FF Lower Address Bit Names Register Name Bit 7 Bit 6 Bit 5 Bit 4 H'86 LVDCR LVDE — VINTDSEL H'87 LVDSR OVF — — Bit 3 Bit 2 Bit 1 Bit 0 Module Name VINTUSEL LVDSL LVDRE LVDDE LVDUE — VREFSEL — LVDDF LVDUF Low-voltage detect circuit* H'80 H'81 H'82 H'83 H'84 H'85 H'88 H'89 H'8A H'8B H'8C ECPWCRH ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Asynchronous H'8D ECPWCRL ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPW
Appendix B Internal I/O Registers Upper Address: H'FF Lower Address Bit Names Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'A8 SMR COM CHR PE PM STOP MP CKS1 CKS0 SCI3 H'A9 BRR BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 H'AA SCR3 TIE RIE TE RE — TEIE CKE1 CKE0 H'AB TDR TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 H'A0 H'A1 H'A2 H'A3 H'A4 H'A5 H'A6 H'A7 H'AC SSR TDRE RDRF OER FER PER TEND — — H''AD RDR RDR7 RDR6 RDR5 R
Appendix B Internal I/O Registers Upper Address: H'FF Bit Names Lower Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'C0 LPCR DTS1 DTS0 CMX — SGS3 SGS2 SGS1 SGS0 H'C1 LCR — PSW ACT DISP CKS3 CKS2 CKS1 CKS0 LCD controller/ driver H'C2 LCR2 LCDAB — — — CDS3* CDS2* CDS1* CDS0* H'C3 LVDCNT CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 Low-voltage detect circuit* H'C4 ADRRH ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 A/D co
Appendix B Internal I/O Registers Upper Address: H'FF Lower Address Register Name Bit Names Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name I/O port H'E0 PUCR1 PUCR17 PUCR16 — PUCR14 PUCR13 — — — H'E1 PUCR3 PUCR37 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30 H'E2 PUCR5 PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 H'E3 PUCR6 PUCR67 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60 H'E4 PCR1 PCR17 PCR16 — PCR14 PCR13 — — —
Appendix B Internal I/O Registers B.2 Functions Address to which the register is mapped. When displayed with two-digit number, this indicates the lower address, and the upper address is HFF. Register name Register acronym Timer F H'B6 TCRF⎯Timer Control Register F Name of on-chip supporting module Bit numbers Bit Initial bit values Dashes (⎯) indicate undefined bits.
Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 Bit H'F020 Flash Memory 7 6 5 4 3 2 1 0 ⎯ SWE ESU PSU EV PV E P Initial value 0 0 0 0 0 0 0 0 Read/Write ⎯ R/W R/W R/W R/W R/W R/W R/W Program 0 Program mode cleared (initial value) 1 Transition to program mode [Setting condition] When SWE = 1 and PSU = 1 Erase 0 Erase mode cleared (initial value) 1 Transition to erase mode [Setting condition] When SWE = 1 and ESU = 1 Program-Verify 0 Prog
Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 Bit H'F021 Flash Memory 7 6 5 4 3 2 1 0 FLER ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value 0 0 0 0 0 0 0 0 Read/Write R ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Flash memory error Note: A write to FLMCR2 is prohibited.
Appendix B Internal I/O Registers EBR—Erase Block Register Bit H'F023 Flash Memory 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ EB4 EB3 EB2 EB1 EB0 Initial value 0 0 0 0 0 0 0 0 Read/Write ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W Blocks 4 to 0 0 When a block of EB4 to EB0 is not selected (initial value) 1 When a block of EB4 to EB0 is selected Note: Set the bit of EBR to H'00 when erasing.
Appendix B Internal I/O Registers LVDCR—Low-Voltage Detection Control Register H'86 Note: This register is implemented on the H8/38124 Group only.
Appendix B Internal I/O Registers LVDSR—Low-Voltage Detection Status Register H'87 Note: This register is implemented on the H8/38124 Group only.
Appendix B Internal I/O Registers ECPWCRH—Event Counter PWM Compare Register H H'8C Bit 7 6 5 4 3 AEC 2 1 0 ECPWCRH7 ECPWCRH6 ECPWCRH5 ECPWCRH4 ECPWCRH3 ECPWCRH2 ECPWCRH1 ECPWCRH0 Initial value R/W 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Sets event counter PWM waveform conversion period ECPWCRL—Event Counter PWM Compare Register L Bit 7 6 5 4 H'8D 3 AEC 2 1 0 ECPWCRL7 ECPWCRL6 ECPWCRL5 ECPWCRL4 ECPWCRL3 ECPWCRL2 ECPWCRL1 ECPWCRL0 Initial value R/W 1 1 1 1 1
Appendix B Internal I/O Registers WEGR—Wakeup Edge Select Register Bit 7 6 5 H'90 4 3 System Control 2 1 0 WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W WKPn Edge Selected 0 WKPn pin falling edge detected 1 WKPn pin rising edge detected (n = 7 to 0) Rev. 8.00 Mar.
Appendix B Internal I/O Registers SPCR—Serial Port Control Register Bit H'91 7 6 5 4 3 SCI3 2 1 0 ⎯ ⎯ SPC32 ⎯ ⎯ ⎯ Initial value 1 1 0 ⎯ 0 0 ⎯ ⎯ Read/Write ⎯ ⎯ R/W W R/W R/W W W SCINV3 SCINV2 RXD32 Pin Input Data Inversion Switch 0 1 RXD32 input data is not inverted RXD32 input data is inverted TXD32 Pin Output Data Inversion Switch 0 1 TXD32 output data is not inverted TXD32 output data is inverted P42/TXD32 Pin Function Switch 0 1 Function as P42 I/O pin Function as
Appendix B Internal I/O Registers AEGSR—Input Pin Edge Select Register 5 6 7 Bit H'92 3 4 AHEGS1 AHEGS0 ALEGS1 ALEGS0 AIEGS1 AEC 2 1 AIEGS0 ECPWME 0 ⎯ Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Event Counter PWM Enable/Disable, IRQAEC Select/Deselect 0 1 AEC PWM halted, IRQAEC selected AEC PWM operation enabled, IRQAEC deselected IRQAEC Edge Select Bit 3 Bit 2 Description AIEGS1 AIEGS0 Falling edge on IRQAEC pin is sensed 0 0 Rising edge on IRQAE
Appendix B Internal I/O Registers ECCR—Event Counter Control Register Bit H'94 7 6 5 4 ACKH1 ACKH0 ACKL1 ACKL0 3 AEC 1 2 PWCK2 PWCK1 PWCK0 0 ⎯ Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Event Counter PWM Clock Select Bit 3 Bit 2 Bit 1 PWCK2 PWCK1 PWCK0 φ/2 0 0 0 φ/4 0 0 1 φ/8 0 1 0 φ/16 0 1 1 φ/32 1 * 0 φ/64 1 * 1 Description *: Don't care AEC Clock Select L Bit 5 Bit 4 Description ACKL1 ACKL0 AEVL pin input 0 0 φ/2 0 1 φ/4 1 0 φ/8 1 1 AEC Cl
Appendix B Internal I/O Registers ECCSR—Event Counter Control/Status Register Bit H'95 AEC 7 6 5 4 3 2 1 0 OVH OVL ⎯ CH2 CUEH CUEL CRCH CRCL Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Counter Reset Control L 0 ECL is reset 1 ECL reset is cleared and count-up function is enabled Counter Reset Control H 0 ECH is reset 1 ECH reset is cleared and count-up function is enabled Count-up Enable L 0 ECL event clock input is disabled.
Appendix B Internal I/O Registers ECH—Event Counter H Bit H'96 AEC 7 6 5 4 3 2 1 0 ECH7 ECH6 ECH5 ECH4 ECH3 ECH2 ECH1 ECH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count value Note: ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (EC).
Appendix B Internal I/O Registers SMR—Serial Mode Register Bit H'A8 SCI3 7 6 5 4 3 2 1 0 COM CHR PE PM STOP MP CKS1 CKS0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 0 φ clock 0 1 φw/2 clock 1 0 φ/16 clock 1 1 φ/64 clock 5 Bit Communication 0 5 bits communication disabled 1 5 bits communication enabled Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode 0 Even parity 1 Odd parity Parity Enable 0 Parity bit addition and check
Appendix B Internal I/O Registers BRR—Bit Rate Register Bit H'A9 SCI3 7 6 5 4 3 2 1 0 BRR7 BRR6 BRR5 BRR4 BRR3 BRR2 BRR1 BRR0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Serial transmit/receive bit rate Rev. 8.00 Mar.
Appendix B Internal I/O Registers SCR3—Serial Control Register 3 Bit H'AA SCI3 7 6 5 4 3 2 1 0 TIE RIE TE RE ⎯ TEIE CKE1 CKE0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable Bit 1 CKE1 0 Bit 0 CKE0 0 0 1 1 0 1 1 Communication Mode Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Asynchronous Synchronous Description Clock Source SCK32 Pin Function I/O port Internal clock Internal clock Serial clock
Appendix B Internal I/O Registers TDR—Transmit Data Register Bit H'AB SCI3 7 6 5 4 3 2 1 0 TDR7 TDR6 TDR5 TDR4 TDR3 TDR2 TDR1 TDR0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data for transfer to TSR Rev. 8.00 Mar.
Appendix B Internal I/O Registers SSR—Serial Status Register Bit H'AC SCI3 7 6 5 4 3 2 1 0 TDRE RDRF OER FER PER TEND ⎯ ⎯ Initial value 1 0 0 0 0 1 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Transmit End 0 Transmission in progress [Clearing conditions] · After reading TDRE = 1, cleared by writing 0 to TDRE · When data is written to TDR by an instruction 1 Transmission ended [Setting conditions] · When bit TE in serial control register3 (SCR3) is clear
Appendix B Internal I/O Registers RDR—Receive Data Register Bit H'AD SCI3 7 6 5 4 3 2 1 0 RDR7 RDR6 RDR5 RDR4 RDR3 RDR2 RDR1 RDR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Serial receiving data are stored TMA—Timer Mode Register A Bit H'B0 Timer A 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ TMA3 TMA2 TMA1 TMA0 Initial value ⎯ ⎯ ⎯ 1 0 0 0 0 Read/Write W W W ⎯ R/W R/W R/W R/W Internal Clock Select Prescaler and Divider Ratio TMA3 TMA2 TMA1
Appendix B Internal I/O Registers TCA—Timer Counter A Bit H'B1 Timer A 7 6 5 4 3 2 1 0 TCA7 TCA6 TCA5 TCA4 TCA3 TCA2 TCA1 TCA0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count value Rev. 8.00 Mar.
Appendix B Internal I/O Registers TCSRW—Timer Control/Status Register W Bit Initial value Read/Write 7 6 B6WI TCWE 1 0 R R/(W)*1 H'B2 5 4 B4WI TCSRWE 1 0 R R/(W)*1 Watchdog Timer 3 2 1 0 B2WI BOWI WRST 1 WDON 0 *2 1 0 R R/(W)*1 R R/(W)*1 Watchdog Timer Reset 0 Clearing conditions: Reset by RES pin When TCSRWE = 1, and 0 is written in both B0WI and WRST 1 Setting condition: When TCW overflows and an internal reset signal is generated Bit 0 Write Inhibit 0 Bit 0 is write-
Appendix B Internal I/O Registers TCW—Timer Counter W Bit H'B3 Watchdog Timer 7 6 5 4 3 2 1 0 TCW7 TCW6 TCW5 TCW4 TCW3 TCW2 TCW1 TCW0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value TMC—Timer Mode Register C Bit H'B4 Timer C 7 6 5 4 3 2 1 0 TMC7 TMC6 TMC5 ⎯ ⎯ TMC2 TMC1 TMC0 Initial value 0 0 0 1 1 0 0 0 Read/Write R/W R/W R/W ⎯ ⎯ R/W R/W R/W Clock Select 0 0 0 Internal clock: φ/8192 1 Internal cl
Appendix B Internal I/O Registers TCC—Timer Counter C Bit H'B5 Timer C 7 6 5 4 3 2 1 0 TCC7 TCC6 TCC5 TCC4 TCC3 TCC2 TCC1 TCC0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Count value Note: TCC is allocated to the same address as TLC. In a read, the TCC value is returned.
Appendix B Internal I/O Registers TCRF—Timer Control Register F Bit H'B6 Timer F 7 6 5 4 3 2 1 0 TOLH CKSH2 CKSH1 CKSH0 TOLL CKSL2 CKSL1 CKSL0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Clock Select L 0 Except for 11 Counting on external event (TMIF) rising/falling edge 0 1 1 1 1 Do not specify this combination Internal clock φ/32 Internal clock φ/16 Internal clock φ/4 Internal clock φw/4 1 0 0 1 1 Toggle Output Level L 0 1 Low level High level Cloc
Appendix B Internal I/O Registers TCSRF—Timer Control/Status Register F Bit H'B7 Timer F 7 6 5 4 3 2 1 0 OVFH CMFH OVIEH CCLRH OVFL CMFL OVIEL CCLRL Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/W R/W R/(W)* R/(W)* R/W R/W Counter Clear L 0 TCFL clearing by compare match is disabled 1 TCFL clearing by compare match is enabled Timer Overflow Interrupt Enable L 0 TCFL overflow interrupt request is disabled 1 TCFL overflow interrupt request is enabled Co
Appendix B Internal I/O Registers TCFH—8-Bit Timer Counter FH Bit H'B8 Timer F 7 6 5 4 3 2 1 0 TCFH7 TCFH6 TCFH5 TCFH4 TCFH3 TCFH2 TCFH1 TCFH0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Count value Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit timer counter (TCF).
Appendix B Internal I/O Registers OCRFL—Output Compare Register FL Bit 7 6 5 H'BB 4 3 Timer F 2 1 0 OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0 Initial value 1 1 1 1 1 1 1 1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a 16-bit output compare register (OCRF). Rev. 8.00 Mar.
Appendix B Internal I/O Registers TMG—Timer Mode Register G Bit Initial value Read/Write H'BC Timer G 7 6 5 4 3 2 1 0 OVFH OVFL OVIE IIEGS CCLR1 CCLR0 CKS1 CKS0 0 R/(W)* 0 R/(W)* 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Clock Select 0 0 Internal clock: counting on φ/64 1 Internal clock: counting on φ/32 1 0 Internal clock: counting on φ/2 1 Internal clock: counting on φW/4 Counter Clear 0 0 TCG clearing is disabled 1 TCG cleared by falling edge of input capture input signal 1 0
Appendix B Internal I/O Registers ICRGF—Input Capture Register GF Bit 7 6 H'BD 5 4 3 Timer G 2 1 0 ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Stores TCG value at falling edge of input capture signal ICRGR—Input Capture Register GR Bit 7 6 H'BE 5 4 3 Timer G 2 1 0 ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0 Initial value 0 0 0 0 0 0 0 0 Read/Write R R R R R R R R Stores TC
Appendix B Internal I/O Registers LPCR—LCD Port Control Register Bit H'C0 LCD Controller/Driver 7 6 5 4 3 2 1 0 DTS1 DTS0 CMX ⎯ SGS3 SGS2 SGS1 SGS0 Initial value 0 0 0 ⎯ 0 0 0 0 Read/Write R/W R/W R/W W R/W R/W R/W R/W Segment Driver Select Bit 3 Bit 2 Bit 1 Function of Pins SEG32 to SEG1 Bit 0 SEG32 to SEG28 to SEG24 to SEG20 to SEG16 to SEG12 to SEG8 to SEG4 to SGS3 SGS2 SGS1 SGS0 SEG29 SEG25 SEG21 SEG17 SEG13 SEG9 SEG5 SEG1 0 0 0 1 1 0 1 1 0 0 1 1 0 1
Appendix B Internal I/O Registers LCR—LCD Control Register Bit H'C1 LCD Controller/Driver 7 6 5 4 3 2 1 0 ⎯ PSW ACT DISP CKS3 CKS2 CKS1 CKS0 Initial value 1 0 0 0 0 0 0 0 Read/Write ⎯ R/W R/W R/W R/W R/W R/W R/W Frame Frequency Select Bit 3 Bit 2 Bit 1 Bit 1 CKS3 CKS2 CKS1 CKS0 0 0 0 1 1 1 1 1 1 1 1 * * * 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 Display Data Control 0 1 * 0 1 0 1 0 1 0 1 Operating Clock φw φw/2 φw/4 φ/2 φ/4 φ/8 φ/16 φ/32 φ/64 φ/128 φ/256 *: Don't care
Appendix B Internal I/O Registers LCR2—LCD Control Register 2 Bit H'C2 LCD 7 6 5 4 3 2 1 0 LCDAB ⎯ ⎯ ⎯ CDS3 CDS2 CDS1 CDS0 Initial value 0 1 1 ⎯ 0 0 0 0 Read/Write R/W ⎯ ⎯ W R/W R/W R/W R/W A Waveform/B Waveform Switching Control 0 Drive using A waveform 1 Drive using B waveform Removal of Split-Resistance Control CDS3 0 CDS2 CDS1 CDS0 1 1 1 Other than the above Split-resistance condition Split-resistance removed Split-resistance connected Note: The removal of split-
Appendix B Internal I/O Registers AMR—A/D Mode Register Bit H'C6 A/D Converter 7 6 5 4 3 2 1 0 CKS TRGE ⎯ ⎯ CH3 CH2 CH1 CH0 Initial value 0 0 1 1 0 0 0 0 Read/Write R/W R/W ⎯ ⎯ R/W R/W R/W R/W Channel Select Bit 3 Bit 2 Bit 1 CH3 CH2 CH1 0 0 * 1 0 Bit 0 CH0 1 1 0 0 1 1 1 * * 0 1 0 1 0 1 0 1 * Analog Input Channel No channel selected AN 0 AN 1 AN 2 AN 3 AN 4 AN 5 AN 6 AN 7 Do not specify this combination *: Don't care External Trigger Select 0 Disables start of
Appendix B Internal I/O Registers ADRRH—A/D Result Register H ADRRL—A/D Result Register L H'C4 H'C5 A/D Converter ADRRH Bit Initial value Read/Write 7 6 5 4 3 2 1 0 ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined R R R R R R R R A/D conversion result ADRRL Bit Initial value Read/Write 7 6 5 4 3 2 1 0 ADR1 ADR0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Undefined Undefined R R A/D conv
Appendix B Internal I/O Registers PMR1—Port Mode Register 1 Bit H'C8 I/O Port 7 6 5 4 3 2 1 0 IRQ3 ⎯ ⎯ IRQ4 TMIG ⎯ ⎯ ⎯ Initial value 0 1 ⎯ 0 0 ⎯ 1 ⎯ Read/Write R/W ⎯ W R/W R/W W ⎯ W P13/TMIG Pin Function Switch 0 Functions as P13 I/O pin 1 Functions as TMIG input pin P14/IRQ4/ADTRG Pin Function Switch 0 Functions as P14 I/O pin 1 Functions as IRQ4/ADTRG input pin P17/IRQ3/TMIF Pin Function Switch 0 Functions as P17 I/O pin 1 Functions as IRQ3/TMIF input pin Rev. 8.
Appendix B Internal I/O Registers PMR2—Port Mode Register 2 Bit H'C9 I/O Port 7 6 5 4 3 2 1 0 ⎯ ⎯ POF1 ⎯ ⎯ WDCKS NCS IRQ0 Initial value 1 1 0 1 1 0 0 0 Read/Write ⎯ ⎯ R/W ⎯ ⎯ R/W R/W R/W P43/IRQ0 Pin Function Switch 0 Functions as P43 I/O pin 1 Functions as IRQ0 input pin TMIG Noise Canceller Select 0 Noise cancellation function not used 1 Noise cancellation function used Watchdog Timer Switch 0 Selects φ8192* 1 Selects φW/32 P35 Pin Output Buffer PMOS On/Off Control 0
Appendix B Internal I/O Registers PMR3—Port Mode Register 3 Bit H'CA I/O Port 7 6 5 4 3 2 1 0 AEVL AEVH ⎯ ⎯ ⎯ TMOFH TMOFL UD Initial value 0 0 ⎯ ⎯ ⎯ 0 0 0 Read/Write R/W R/W W W W R/W R/W R/W P30/UD Pin Function Switch 0 Functions as P30 I/O pin 1 Functions as UD input pin P31/TMOFL Pin Function Switch 0 Functions as P31 I/O pin 1 Functions as TMOFL output pin P32/TMOFH Pin Function Switch 0 Functions as P32 I/O pin 1 Functions as TMOFH output pin P36/AEVH Pin Function
Appendix B Internal I/O Registers PMR5—Port Mode Register 5 Bit H'CC I/O Port 7 6 5 4 3 2 1 0 WKP7 WKP6 WKP5 WKP4 WKP3 WKP2 WKP1 WKP0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W P5n/WKPn/SEGn+1 Pin Function Switch 0 Functions as P5n I/O pin 1 Functions as WKPn input pin (n = 7 to 0) PWCR2—PWM2 Control Register Bit H'CD 7 6 5 4 3 ⎯ ⎯ ⎯ ⎯ ⎯ Initial value 1 1 1 1 1 Read/Write ⎯ ⎯ ⎯ ⎯ ⎯ 2 10-Bit PWM 1 0 PWCR22 PWCR21
Appendix B Internal I/O Registers PWDRU2—PWM2 Data Register U H'CE 10-Bit PWM 7 6 5 4 3 2 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value 1 1 1 1 1 1 0 0 Read/Write ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ W W Bit 0 1 PWDRU21 PWDRU20 Upper 2 bits of PWM2 waveform generation data PWDRL2—PWM2 Data Register L Bit 7 6 H'CF 5 4 3 10-Bit PWM 2 1 0 PWDRL27 PWDRL26 PWDRL25 PWDRL24 PWDRL23 PWDRL22 PWDRL21 PWDRL20 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Lower 8 bits of PWM2 waveform g
Appendix B Internal I/O Registers PWCR1—PWM1 Control Register Bit H'D0 7 6 5 4 3 ⎯ ⎯ ⎯ ⎯ ⎯ Initial value 1 1 1 1 1 Read/Write ⎯ ⎯ ⎯ ⎯ ⎯ 10-Bit PWM 2 1 PWCR12 PWCR11 PWCR10 0 0 0* 2 R/W W Clock Select 0 The input clock is φ (tφ*1 = 1/φ) The conversion period is 512/φ, with a minimum modulation width of 1/2φ The input clock is φ/2 (tφ*1 = 2/φ) The conversion period is 1,024/φ, with a minimum modulation width of 1/φ 1 The input clock is φ/4 (tφ*1 = 4/φ) The conversion period is 2,0
Appendix B Internal I/O Registers PWDRU1—PWM1 Data Register U Bit H'D1 10-Bit PWM 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ Initial value 1 1 1 1 1 1 0 0 Read/Write ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ W W PWDRU11 PWDRU10 Upper 2 bits of data for generating PWM1 waveform PWDRL1—PWM1 Data Register L Bit 7 6 H'D2 5 4 3 10-Bit PWM 2 1 0 PWDRL17 PWDRL16 PWDRL15 PWDRL14 PWDRL13 PWDRL12 PWDRL11 PWDRL10 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Lower 8 bits of data for gene
Appendix B Internal I/O Registers PDR4—Port Data Register 4 Bit H'D7 I/O Ports 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ P43 P42 P41 P40 Initial value 1 1 1 1 1 0 0 0 Read/Write ⎯ ⎯ ⎯ ⎯ R R/W R/W R/W Data for port 4 pins Reads P43 state PDR5—Port Data Register 5 Bit H'D8 I/O Ports 7 6 5 4 3 2 1 0 P5 7 P56 P55 P54 P53 P52 P51 P50 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data for port 5 pins PDR6—Port Data Register 6 Bi
Appendix B Internal I/O Registers PDR8—Port Data Register 8 Bit H'DB I/O Ports 7 6 5 4 3 2 1 0 P87 P86 P85 P84 P83 P82 P81 P80 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Data for port 8 pins PDR9—Port Data Register 9 Bit H'DC I/O Ports 7 6 5 4 3 2 1 0 ⎯ ⎯ P95 P94 P93 P92 P91 P90 Initial value 1 1 1 1 1 1 1 1 Read/Write ⎯ ⎯ R/W R/W R/W R/W R/W R/W Data for port 9 pins PDRA—Port Data Register A Bit H'DD
Appendix B Internal I/O Registers PUCR1—Port Pull-Up Control Register 1 Bit 7 6 H'E0 5 PUCR17 PUCR16* I/O Ports 3 4 2 1 0 ⎯ ⎯ ⎯ Initial value 0 0 ⎯ 0 0 ⎯ ⎯ ⎯ Read/Write R/W R/W W R/W R/W W W W ⎯ PUCR14 PUCR13 Port 1 Input Pull-up MOS Control 0 Input pull-up MOS is off 1 Input pull-up MOS is on Note: When the PCR1 specification is 0. (Input port specification) Note: * PUCR16 is not equipped with H8/38124 Group.
Appendix B Internal I/O Registers PUCR5—Port Pull-Up Control Register 5 Bit 7 6 5 H'E2 4 3 I/O Ports 2 0 1 PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50 Initial value 0 0 0 0 0 0 0 0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Port 5 Input Pull-up MOS Control 0 Input pull-up MOS is off 1 Input pull-up MOS is on Note: When the PCR5 specification is 0.
Appendix B Internal I/O Registers PCR1—Port Control Register 1 Bit H'E4 I/O Ports 7 6 5 4 3 2 1 0 PCR17 PCR16* ⎯ PCR14 PCR13 ⎯ ⎯ ⎯ Initial value 0 0 ⎯ 0 0 ⎯ ⎯ ⎯ Read/Write W W W W W W W W Port 1 Input/Output Select 0 Input pin 1 Output pin Note: * PCR16 is not equipped with H8/38124 Group.
Appendix B Internal I/O Registers PCR5—Port Control Register 5 Bit H'E8 I/O Ports 7 6 5 4 3 2 1 0 PCR57 PCR56 PCR55 PCR54 PCR53 PCR52 PCR51 PCR50 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 5 Input/Output Select 0 Input pin 1 Output pin PCR6—Port Control Register 6 Bit H'E9 I/O Ports 7 6 5 4 3 2 1 0 PCR6 7 PCR6 6 PCR6 5 PCR6 4 PCR6 3 PCR6 2 PCR6 1 PCR6 0 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port
Appendix B Internal I/O Registers PCR8—Port Control Register 8 Bit H'EB I/O Ports 7 6 5 4 3 2 1 0 PCR87 PCR86 PCR85 PCR84 PCR83 PCR82 PCR81 PCR80 Initial value 0 0 0 0 0 0 0 0 Read/Write W W W W W W W W Port 8 Input/Output Select 0 Input pin 1 Output pin PMR9—Port Mode Register 9 Bit 7 6 H'EC 5 I/O Ports 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ PIOFF/⎯* ⎯ PWM2 PWM1 Initial value 1 1 1 1 0 ⎯ 0 0 Read/Write ⎯ ⎯ ⎯ ⎯ R/W W R/W R/W P90/PWM1 Pin Function Switch
Appendix B Internal I/O Registers PCRA—Port Control Register A Bit H'ED I/O Ports 7 6 5 4 3 2 0 1 ⎯ ⎯ ⎯ ⎯ PCRA 3 PCRA 2 Initial value 1 1 1 1 0 0 0 0 Read/Write ⎯ ⎯ ⎯ ⎯ W W W W PCRA 1 PCRA 0 Port A Input/Output Select 0 Input pin 1 Output pin PMRB—Port Mode Register B Bit H'EE I/O Ports 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ ⎯ IRQ1 ⎯ ⎯ ⎯ Initial value 1 1 1 1 0 1 1 1 Read/Write ⎯ ⎯ ⎯ ⎯ R/W ⎯ ⎯ ⎯ PB3/AN3/IRQ1 Pin Function Switch 0 Functions as PB3/AN3
Appendix B Internal I/O Registers SYSCR1—System Control Register 1 Bit H'F0 System Control 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 LSON ⎯ MA1 MA0 Initial value 0 0 0 0 0 1 1 1 Read/Write R/W R/W R/W R/W R/W ⎯ R/W R/W Active (medium-speed) Mode Clock Select 0 0 φosc/16 1 φosc/32 1 0 φosc/64 1 φosc/128 Low Speed on Flag 0 The CPU operates on the system clock (φ) 1 The CPU operates on the subclock (φ SUB) Standby Timer Select 2 to 0 0 0 0 Wait time = 8,192 states*1 1 Wait time
Appendix B Internal I/O Registers SYSCR2—System Control Register 2 Bit H'F1 System Control 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ NESEL DTON MSON SA1 SA0 Initial value 1 1 1 1 0 0 0 0 Read/Write ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W Subactive Mode Clock Select Medium Speed on Flag 0 0 φW/8 1 φW/4 1 * φW/2 *: Don't care 0 Operates in active (high-speed) mode 1 Operates in active (medium-speed) mode Direct Transfer on Flag 0 • When a SLEEP instruction is executed in active mode, a transition is ma
Appendix B Internal I/O Registers IEGR—IRQ Edge Select Register Bit H'F2 System Control 7 6 5 4 3 2 1 0 ⎯ ⎯ ⎯ IEG4 IEG3 ⎯ IEG1 IEG0 Initial value 1 1 1 0 0 ⎯ 0 0 Read/Write ⎯ ⎯ ⎯ R/W R/W W R/W R/W IRQ0 Edge Select 0 Falling edge of IRQ0 pin input is detected 1 Rising edge of IRQ0 pin input is detected IRQ1 Edge Select 0 Falling edge of IRQ1, TMIC pin input is detected 1 Rising edge of IRQ1, TMIC pin input is detected IRQ3 Edge Select 0 Falling edge of IRQ3, TMIF pin inp
Appendix B Internal I/O Registers IENR1—Interrupt Enable Register 1 Bit H'F3 System Control 7 6 5 4 3 2 1 0 IENTA ⎯ IENWP IEN4 IEN3 IENEC2 IEN1 IEN0 Initial value 0 ⎯ 0 0 0 0 0 0 Read/Write R/W W R/W R/W R/W R/W R/W R/W IRQ1 to IRQ0 Interrupt Enable 0 Disables IRQ1 to IRQ0 interrupt, requests 1 Enables IRQ1 to IRQ0 interrupt requests IRQAEC Interrupt Enable 0 Disables IRQAEC interrupt requests 1 Enables IRQAEC interrupt requests IRQ4 and IRQ3 Interrupt Enable 0 Disables
Appendix B Internal I/O Registers IENR2—Interrupt Enable Register 2 Bit H'F4 7 6 5 4 3 System Control 2 1 0 IENDT IENAD ⎯ IENTG IENTC IENEC Initial value 0 0 ⎯ 0 0 0 0 0 Read/Write R/W R/W W R/W R/W R/W R/W R/W IENTFH IENTFL Asynchronous Event Counter Interrupt Enable 0 Disables asynchronous event counter interrupt requests 1 Enables asynchronous event counter interrupt requests Timer C Interrupt Enable 0 Disables timer C interrupt requests 1 Enables timer C interrupt req
Appendix B Internal I/O Registers OSCCR—Clock Pulse Generator Control Register H'F5 Clock Pulse Generator Note: This register is implemented on the H8/38124 Group only.
Appendix B Internal I/O Registers IRR1—Interrupt Request Register 1 Bit H'F6 System Control 7 6 5 4 3 2 1 0 IRRTA ⎯ ⎯ IRRI4 IRRI3 IRREC2 IRRI1 IRRI0 Initial value 0 ⎯ 1 0 0 0 0 0 Read/Write R/(W)* W ⎯ R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* IRQ1 and IRQ0 Interrupt Request Flags 0 Clearing condition: When IRRIn = 1, it is cleared by writing 0 1 Setting condition: When pin IRQn is designated for interrupt input and the designated signal edge is input (n = 1 or 0) IRQAEC Interr
Appendix B Internal I/O Registers IRR2—Interrupt Request Register 2 Bit H'F7 7 6 5 4 3 2 System Control 1 0 IRRDT IRRAD ⎯ IRRTC IRREC Initial value 0 0 ⎯ 0 0 0 0 0 Read/Write R/(W)* R/(W)* W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* IRRTG IRRTFH IRRTFL Asynchronous Event Counter Interrupt Request Flag 0 Clearing condition: When IRREC = 1, it is cleared by writing 0 1 Setting condition: When the asynchronous event counter value overflows Timer C Interrupt Request Flag 0 Clearing c
Appendix B Internal I/O Registers TMW—Timer Mode Register W H'F8 Watchdog Timer Note: This register is implemented on the H8/38124 Group only.
Appendix B Internal I/O Registers IWPR—Wakeup Interrupt Request Register Bit H'F9 System Control 7 6 5 4 3 2 1 0 IWPF7 IWPF6 IWPF5 IWPF4 IWPF3 IWPF2 IWPF1 IWPF0 Initial value 0 0 0 0 0 0 0 0 Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Wakeup Interrupt Request Register 0 Clearing condition: When IWPFn = 1, it is cleared by writing 0 1 Setting condition: When pin WKPn is designated for wakeup input and a falling edge is input at that pin (n = 7 to 0
Appendix B Internal I/O Registers CKSTPR1—Clock Stop Register 1 Bit 7 6 H'FA 4 5 3 System Control 2 1 0 ⎯ ⎯ Initial value 1 1 1 1 1 1 1 1 Read/Write ⎯ ⎯ R/W R/W R/W R/W R/W R/W S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP Timer A Module Standby Mode Control 0 Timer A is set to module standby mode 1 Timer A module standby mode is cleared Timer C Module Standby Mode Control 0 Timer C is set to module standby mode 1 Timer C module standby mode is cleared Timer F Module Standb
Appendix B Internal I/O Registers CKSTPR2—Clock Stop Register 2 Bit H'FB 7 6 5 4 3 System Control 2 1 0 LVDCKSTP* ⎯ ⎯ Initial value 1 1 1 1 1 1 1 1 Read/Write R/W ⎯ ⎯ R/W R/W R/W R/W R/W PW2CKSTP AECKSTP WDCKSTP PW1CKSTP LDCKSTP LCD Module Standby Mode Control 0 LCD is set to module standby mode 1 LCD module standby mode is cleared PWM1 Module Standby Mode Control 0 PWM1 is set to module standby mode 1 PWM1 module standby mode is cleared WDT Module Standby Mode Control 0 WDT
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.1 Block Diagrams of Port 1 SBY (low level during reset and in standby mode) PUCR1n VCC PMR1n P1n PDR1n VSS Internal data bus VCC PCR1n IRQm PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 n = 7 and 4 m = 4 and 3 Figure C.1(a) Port 1 Block Diagram (Pins P17 and P14) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams SBY (low level during reset and in standby mode) PUCR16 VCC PMR16 PDR16 P16 VSS PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 Internal data bus VCC PCR16 PUCR1: Port pull-up control register 1 Figure C.1(b) Port 1 Block Diagram (Pin P16, Products other than H8/38124 Group) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams SBY PUCR13 VCC PMR13 PDR13 P13 Internal data bus VCC PCR13 VSS Timer G module TMIG PDR1: Port data register 1 PCR1: Port control register 1 PMR1: Port mode register 1 PUCR1: Port pull-up control register 1 Figure C.1(c) Port 1 Block Diagram (Pin P13) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams C.2 Block Diagrams of Port 3 SBY PUCR3n VCC PMR3n P3n PDR3n VSS Internal data bus VCC PCR3n AEC module AEVH(P36) AEVL(P37) PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n = 7 and 6 Figure C.2(a) Port 3 Block Diagram (Pins P37 and P36) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams SBY PUCR35 VCC PMR25 P35 PDR35 VSS PDR3: Port data register 3 PCR3: Port control register 3 PUCR3: Port pull-up control register 3 PMR2 Port mode register 2 PCR35 Figure C.2(b) Port 3 Block Diagram (Pin P35) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams SBY PUCR3n VCC P3n PDR3n Internal data bus VCC PCR3n VSS PDR3: Port data register 3 PCR3: Port control register 3 n = 4 and 3 Figure C.2(c) Port 3 Block Diagram (Pins P34 and P33) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams SBY TMOFH (P32) TMOFL (P31) PUCR3n VCC PMR3n P3n PDR3n VSS PCR3n PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 n = 2 and 1 Figure C.2(d) Port 3 Block Diagram (Pins P32 and P31) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams SBY PUCR30 VCC PMR30 PDR30 P30 Internal data bus VCC PCR30 VSS Timer C module UD PDR3: Port data register 3 PCR3: Port control register 3 PMR3: Port mode register 3 PUCR3: Port pull-up control register 3 Figure C.2(e) Port 3 Block Diagram (Pin P30) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams C.3 Block Diagrams of Port 4 Internal data bus PMR20 P43 IRQ0 PMR2: Port mode register 2 Figure C.3(a) Port 4 Block Diagram (Pin P43) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams SBY SCINV3 VCC SPC32 SCI3 module TXD32 P42 PCR42 VSS Internal data bus PDR42 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3(b) Port 4 Block Diagram (Pin P42) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams SBY VCC SCI3 module RE32 RXD32 P41 PCR41 VSS SCINV2 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3(c) Port 4 Block Diagram (Pin P41) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams SBY SCI3 module SCKIE32 SCKOE32 VCC SCKO32 SCKI32 P40 PCR40 VSS Internal data bus PDR40 PDR4: Port data register 4 PCR4: Port control register 4 Figure C.3(d) Port 4 Block Diagram (Pin P40) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams C.4 Block Diagram of Port 5 SBY* PUCR5n VCC VCC P5n PDR5n VSS PCR5n Internal data bus PMR5n WKPn PDR5: Port data register 5 PCR5: Port control register 5 PMR5: Port mode register 5 PUCR5: Port pull-up control register 5 Note: * The value of SBY is fixed at 1 in the HD64F38024. n = 7 to 0 Figure C.4 Port 5 Block Diagram Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams C.5 Block Diagram of Port 6 SBY VCC PDR6n VCC PCR6n P6n Internal data bus PUCR6n VSS PDR6: Port data register 6 PCR6: Port control register 6 PUCR6: Port pull-up control register 6 n = 7 to 0 Figure C.5 Port 6 Block Diagram Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams C.6 Block Diagram of Port 7 SBY PDR7n PCR7n P7n VSS PDR7: Port data register 7 PCR7: Port control register 7 n = 7 to 0 Figure C.6 Port 7 Block Diagram Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams C.7 Block Diagram of Port 8 VCC PDR8n PCR8n P8n Internal data bus SBY VSS PDR8: Port data register 8 PCR8: Port control register 8 n = 7 to 0 Figure C.7 Port 8 Block Diagram Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams C.8 Block Diagrams of Port 9 PWM module PWMn+1 Internal data bus SBY PMR9n P9n PDR9n VSS PDR9: Port data register 9 n = 1 and 0 Figure C.8(a) Port 9 Block Diagram (Pins P91 and P90) P9n PDR9n VSS PDR9: Port data register 9 n = 5 to 2 Figure C.8(b) Port 9 Block Diagram (Pins P95 to P92) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams Internal data bus SBY P93 PDR93 VSS LVD module VREFSEL Vref PDR9: Port data register 9 Figure C.8(c) Port 9 Block Diagram (Pins P93, H8/38124 Group only) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams C.9 Block Diagram of Port A SBY VCC PCRAn PAn VSS PDRA: Port data register A PCRA: Port control register A n = 3 to 0 Figure C.9 Port A Block Diagram Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams C.10 Block Diagrams of Port B Internal data bus PBn A/D module DEC AMR3 to AMR0 VIN n = 7 to 0 Figure C.10(a) Port B Block Diagram Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams Internal data bus PB0 A/D module DEC AMR3 to AMR0 VIN LVD module VINTDSEL extD Figure C.10(b) Port B Block Diagram (Pin PB0, H8/38124 Group only) Rev. 8.00 Mar.
Appendix C I/O Port Block Diagrams Internal data bus PB1 A/D module DEC AMR3 to AMR0 VIN LVD module VINTUSEL extU Figure C.10(c) Port B Block Diagram (Pin PB1, H8/38124 Group only) Rev. 8.00 Mar.
Appendix D Port States in the Different Processing States Appendix D Port States in the Different Processing States Table D.
Appendix E List of Product Codes Appendix E List of Product Codes Table E.1 H8/38024 Group Product Code Lineup Product Type H8/38024 Group H8/38024 Mask ROM versions Regular specifications Wide-range specifications ZTAT versions Regular specifications Wide-range specifications F-ZTAT versions Regular specifications Wide-range specifications Part No.
Appendix E List of Product Codes Product Type H8/38024 Group H8/38023 Mask ROM versions Regular specifications Wide-range specifications H8/38022 Mask ROM versions Regular specifications Wide-range specifications H8/38021 Mask ROM versions Regular specifications Wide-range specifications H8/38020 Mask ROM versions Regular specifications Wide-range specifications Rev. 8.00 Mar. 09, 2010 Page 636 of 658 REJ09B0042-0800 Part No.
Appendix E List of Product Codes Product Type H8/38024S Group H8/38024S Mask ROM versions Regular specifications Wide-range specifications H8/38023S Mask ROM versions Regular specifications Wide-range specifications H8/38022S Mask ROM versions Regular specifications Wide-range specifications H8/38021S Mask ROM versions Regular specifications Wide-range specifications H8/38020S Mask ROM versions Regular specifications Wide-range specifications Part No.
Appendix E List of Product Codes Part No.
Appendix F Package Dimensions Appendix F Package Dimensions Dimensional drawings of the H8/38024 Group, H8/38024S Group, and H8/38124 Group packages FP-80A, FP-80B, and TFP-80C are shown in figures F.1, F.2, and F.3 below. JEITA Package Code P-QFP80-14x14-0.65 RENESAS Code PRQP0080JB-A Previous Code FP-80A/FP-80AV MASS[Typ.] 1.2g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Appendix F Package Dimensions JEITA Package Code P-QFP80-14x20-0.80 RENESAS Code PRQP0080GD-B Previous Code FP-80B/FP-80BV MASS[Typ.] 1.7g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. HD *1 D 64 41 65 40 bp c c1 HE *2 E b1 ZE Reference Symbol 25 80 1 Terminal cross section 24 c A2 A ZD θ F L A1 S L1 Detail F e y S *3 bp x M Figure F.2 FP-80B Package Dimensions Rev. 8.00 Mar.
Appendix F Package Dimensions JEITA Package Code P-TQFP80-12x12-0.50 RENESAS Code PTQP0080KC-A Previous Code TFP-80C/TFP-80CV MASS[Typ.] 0.4g NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Appendix F Package Dimensions JEITA Package Code P-TFLGA85-7x7-0.65 RENESAS Code PTLG0085JA-A Previous Code TLP-85V MASS[Typ.] 0.1g D w S B E w S A ×4 v y1 S A S y S ZD e A K Reference Symbol e J H G B F E Dimension in Millimeters Min Nom D 7.0 E 7.0 Max 0.15 v w 0.20 A 1.20 A1 D e b ZE C B A 0.65 0.30 0.35 0.08 y 0.10 y1 0.2 SD 1 2 3 4 5 6 φ b 7 φ 8 9 10 ×M S A B Figure F.4 TLP-85V Package Dimensions Rev. 8.00 Mar.
Appendix G Specifications of Chip Form Appendix G Specifications of Chip Form The specifications of the chip form of the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 are shown in figure G.1. The specifications of the chip form of the HCD64F38024 and HCD64F38024R are shown in figure G.2. The specifications of the chip form of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S are shown in figure G.3. Maximum plain X-direction: 3.99 ± 0.25 Y-direction: 3.
Appendix G Specifications of Chip Form Maximum plain X-direction: 2.91 ± 0.25 Y-direction: 2.91 ± 0.25 Max 0.03 0.28 ± 0.02 X-direction: 2.91 ± 0.05 Y-direction: 2.91 ± 0.05 Unit: mm Figure G.3 Chip Sectional Figure of the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Rev. 8.00 Mar.
Appendix H Form of Bonding Pads Appendix H Form of Bonding Pads The form of the bonding pads for the HCD64338024, HCD64338023, HCD64338022, HCD64338021, HCD64338020, HCD64F38024, HCD64F38024R, HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S is shown in figure H.1. Bonding area 5 mm 72 mm Metal layer 72 mm 5 mm Figure H.1 Bonding Pad Form Rev. 8.00 Mar.
Appendix I Specifications of Chip Tray Appendix I Specifications of Chip Tray The specifications of the chip tray for the HCD64338024, HCD64338023, HCD64338022, HCD64338021, and HCD64338020 are shown in figure I.1. The specifications of the chip tray for the HCD64F38024 and HCD64F38024R are shown in figure I.2. The specifications of the chip tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S are shown in figure I.3. 51 Chip direction Chip 3.99 Type name 51 3.99 6.
Appendix I Specifications of Chip Tray 51 Chip 4.24 Chip direction Type name 51 3.84 6.2 ± 0.1 6.9 ± 0.1 X-X' cross section 1.8 ± 0.1 0.6 ± 0.1 4.5 ± 0.05 6.2 ± 0.1 6.9 ± 0.1 X' 4.0 ± 0.1 X 4.5 ± 0.05 Chip tray name DAINIPPON-INK-&-CHEMICALS-INC. Type: CT015 Carved code: TCT45-060P Unit: mm Figure I.2 Specifications of Chip Tray for the HCD64F38024 and HCD64F38024R Rev. 8.00 Mar.
Appendix I Specifications of Chip Tray 51 Chip direction Chip Y Type name X 51 Chip tray name Type: CT290 Carved code:TCT036036-060T 3.6 ± 0.05 4.48 ± 0.1 X X‘ 5.34 ± 0.1 0.8 ± 0.05 Back of chip tray 3.6 ± 0.05 1.8 4.0 0.2 ± 0.1 5.34 ± 0.1 1.5 4.48 ± 0.1 X-X‘ Cross section unit: mm Figure I.3 Specifications of Chip Tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Rev. 8.00 Mar.
Main Revisions for This Edition Item Page Revision (See Manual for Details) 1.1 Overview 5 Table amended Table 1.1 Features 4.3 Subclock Generator 111 Item Specification Serial communication interface • SCI3: 8-bit synchronous/asynchronous serial interface Figure amended C1 C1 = C 2 = 15 pF (typ.) X1 Figure 4.8 Typical Connection to 32.768 kHz/38.4 kHz Crystal Oscillator (Subclock) X2 Frequency Crystal oscillator 38.4 kHz Seiko Instruments Inc. VTC-200 32.
Item Page Revision (See Manual for Details) 10.1.1 Features 333 Table amended 10.2.5 Serial Mode Register (SMR) 341 Data length 7, 8, 5 bits Stop bit length 1 or 2 bits Parity Even, odd, or none Receive error detection Parity, overrun, and framing errors Break detection Break detected by reading the RXD32 pin level directly when a framing error occurs Description amended Bit 2—5 Bit Communication (MP) When this bit is one, the format of 5 bits communication becomes possible.
Item Page Revision (See Manual for Details) 10.3.1 Overview 358 Description amended • Asynchronous Mode Table 10.8 SMR Settings and Corresponding Data Transfer Formats 359 Choice of parity addition, and addition of 1 or 2 stop bits. (The combination of these parameters determines the data transfer format and the character length.
Item Page Revision (See Manual for Details) 16.2.2 DC Characteristics 453 Table amended Values Table 16.2 DC Characteristics 16.4.2 DC Characteristics 469 Item Symbol Applicable Pins Input high voltage VIH Min Typ Max RES, 0.8 VCC — WKP0 to WKP7, 0.9 VCC — IRQ0, IRQ3, IRQ4, AEVL, AEVH, TMIC, TMIF, TMIG, ADTRG, SCK32 VCC + 0.3 IRQ1 0.8 VCC — AVCC + 0.3 0.9 VCC — AVCC + 0.3 Unit Test Condition V VCC + 0.3 Notes VCC = 4.0 V to 5.5 V Except the above V VCC = 4.0 V to 5.
Item Page Revision (See Manual for Details) 16.4.2 DC Characteristics 474 Table amended Values Table 16.8 DC Characteristics 16.4.7 Power Supply 482 Characteristics 16.6.2 DC Characteristics Table 16.16 DC Characteristics 487 Item Symbol Applicable Pins Min Watch mode current dissipation IWATCH VCC — Typ Max Unit Test Condition Notes 2.0 — μA *3 *4 VCC = 2.7 V, Ta = 25°C 32 kHz External Clock LCD not used — 2.6 — μA VCC = 2.
Item Page Revision (See Manual for Details) 16.6.2 DC Characteristics 492 Table amended Values Table 16.16 DC Characteristics Item Symbol Applicable Pins Min Typ Max Unit Test Condition Notes Subactive mode current dissipation ISUB — 6.2 — μA VCC = 1.8 V, LCD on 32 kHz External Clock (φSUB=φw/2) *1 *2 — 5.7 — μA VCC = 1.8 V, LCD on 32 kHz crystal resonator (φSUB=φw/2) — 4.4 — μA VCC = 2.7 V, LCD on 32 kHz crystal resonator (φSUB=φw/8) — 10 40 μA VCC = 2.
Item Page Revision (See Manual for Details) 16.8.2 DC Characteristics 506 Table amended Values Table 16.22 DC Characteristics Item Symbol Applicable Pins Input high voltage VIH Typ Max Unit Test Condition RES, VCC × 0.8 WKP0 to WKP7, IRQ0, IRQ3, IRQ4, AEVL, AEVH, VCC × 0.9 TMIC, TMIF, TMIG, ADTRG, SCK32 — VCC + 0.3 V — VCC + 0.3 IRQ1 VCC × 0.8 — AVCC + 0.3 VCC × 0.9 — AVCC + 0.3 16.8.10 Power 525 Supply Characteristics Newly added B.1 Addresses Table amended B.
Item Page Revision (See Manual for Details) B.
Item Page Appendix F Package 642 Dimensions Revision (See Manual for Details) Figure replaced Figure F.4 TLP-85V Package Dimensions Appendix I 648 Specifications of Chip Tray Figure replaced Figure I.3 Specifications of Chip Tray for the HCD64338024S, HCD64338023S, HCD64338022S, HCD64338021S, and HCD64338020S Rev. 8.00 Mar.
Rev. 8.00 Mar.
Renesas 8-Bit Single-Chip Microcomputer Hardware Manual H8/38024, H8/38024S, H8/38024R, H8/38124 Group Publication Date: 1st Edition, November, 2000 Rev.8.00, March 9, 2010 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2010. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8/38024, H8/38024S, H8/38024R, H8/38124 Group Hardware Manual REJ09B0042-0800
