Datasheet

Section 5 Power-Down Modes
Rev. 8.00 Mar. 09, 2010 Page 129 of 658
REJ09B0042-0800
5.2.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous event
counter, IRQAEC, IRQ
4
, IRQ
3
, IRQ
1
, IRQ
0
, WKP
7
to WKP
0
, SCI3, A/D converter), or by input at
the RES pin.
• Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φ(s) delay may occur
after the interrupt request signal occurrence, before the interrupt exception handling start.
• Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode
Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.