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RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER

M16C FAMILY / M16C/60 SERIES

Rev. 1.10

Revision date: Jul. 01, 2005

Hardware Manual

www.renesas.com

Before using this material, please visit our website to verify that this is the most

updated document available.

REJ09B0124-0110

M16C/6N Group

(M16C/6NK, M16C/6NM)

Summary of content (340 pages)

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REJ09B0124-0110 M16C/6N Group 16 (M16C/6NK, M16C/6NM) Hardware Manual RENESAS 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES Before using this material, please visit our website to verify that this is the most updated document available. Rev. 1.10 Revision date: Jul. 01, 2005 www.renesas.
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Keep safety first in your circuit designs! • Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
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How to Use This Manual 1. Introduction This hardware manual provides detailed information on the M16C/6N Group (M16C/6NK, M16C/6NM) of microcomputers. Users are expected to have basic knowledge of electric circuits, logical circuits and microcomputers. 2. Register Diagram The symbols, and descriptions, used for bit function in each register are shown below.
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3. M16C Family Documents The following documents were prepared for the M16C family (1).
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Table of Contents SFR Page Reference ............................................................................................................ B-1 1. Overview ............................................................................................................................... 1 1.1 Applications .................................................................................................................................................. 1 1.2 Performance Outline ..............................
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7.2 CPU Clock and Peripheral Function Clock ................................................................................................ 47 7.2.1 CPU Clock and BCLK ........................................................................................................................ 47 7.2.2 Peripheral Function Clock .................................................................................................................. 47 7.3 Clock Output Function ...........................................
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11. DMAC ................................................................................................................................ 82 11.1 Transfer Cycle .......................................................................................................................................... 87 11.1.1 Effect of Source and Destination Addresses .................................................................................... 87 11.1.2 Effect of Software Wait ........................................
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18. CAN Module .................................................................................................................... 202 18.1 CAN Module-Related Registers ............................................................................................................. 203 18.1.1 CAN Message Box ......................................................................................................................... 203 18.1.2 Acceptance Mask Registers ..............................................
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20.4 Standard Serial I/O Mode ...................................................................................................................... 259 20.4.1 ID Code Check Function ................................................................................................................ 259 20.4.2 Example of Circuit Application in Standard Serial I/O Mode .......................................................... 263 20.5 Parallel I/O Mode ............................................................
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22.18 Flash Memory Version ......................................................................................................................... 311 22.18.1 Functions to Prevent Flash Memory from Rewriting .................................................................... 311 22.18.2 Stop Mode .................................................................................................................................... 311 22.18.3 Wait Mode ........................................................
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SFR Page Reference Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 0027h 0028h 0029h 002Ah 002Bh 002Ch 002Dh 002Eh 002Fh 0030h 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Register Processor Mode Register 0 Processor Mode Register 1 System Clock Control Register 0 System
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Address 0080h 0081h 0082h 0083h 0084h 0085h 0086h 0087h 0088h 0089h 008Ah 008Bh 008Ch 008Dh 008Eh 008Fh 0090h 0091h 0092h 0093h 0094h 0095h 0096h 0097h 0098h 0099h 009Ah 009Bh 009Ch 009Dh 009Eh 009Fh 00A0h 00A1h 00A2h 00A3h 00A4h 00A5h 00A6h 00A7h 00A8h 00A9h 00AAh 00ABh 00ACh 00ADh 00AEh 00AFh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh Register Symbol Page Address 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00CBh 00CCh 00CDh 00C
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Address 0100h 0101h 0102h 0103h 0104h 0105h 0106h 0107h 0108h 0109h 010Ah 010Bh 010Ch 010Dh 010Eh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h 0119h 011Ah 011Bh 011Ch 011Dh 011Eh 011Fh 0120h 0121h 0122h 0123h 0124h 0125h 0126h 0127h 0128h 0129h 012Ah 012Bh 012Ch 012Dh 012Eh 012Fh 0130h 0131h 0132h 0133h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh Register Symbol Address 0140h 0141h 0142h 0143h 0144h 0145h 0146h 0147h 0148h 0149h 014Ah 014Bh 014Ch 014Dh 014Eh 014
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Address 0180h 0181h 0182h 0183h 0184h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h 01A6h 01A7h 01A8h 01A9h 01AAh 01ABh 01ACh 01ADh 01AEh 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh Register Symbol Page Flash Memory Control Register 1 FMR1 244 Flash Memory Control Register 0 FMR0 244 Address
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Address 0200h 0201h 0202h 0203h 0204h 0205h 0206h 0207h 0208h 0209h 020Ah 020Bh 020Ch 020Dh 020Eh 020Fh 0210h 0211h 0212h 0213h 0214h 0215h 0216h 0217h 0218h 0219h 021Ah 021Bh 021Ch 021Dh 021Eh 021Fh 0220h 0221h 0222h 0223h 0224h 0225h 0226h 0227h 0228h 0229h 022Ah 022Bh 022Ch 022Dh 022Eh 022Fh 0230h 0231h 0232h 0233h 0234h 0235h 0236h 0237h 0238h 0239h 023Ah 023Bh 023Ch 023Dh 023Eh 023Fh Register CAN0 Message Control Register 0 CAN0 Message Control Register 1 CAN0 Message Control Register 2 CAN0 Message C
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Address 0280h 0281h 0282h 0283h 0284h 0285h 0286h 0287h 0288h 0289h 028Ah 028Bh 028Ch 028Dh 028Eh 028Fh 0290h 0291h 0292h 0293h 0294h 0295h 0296h 0297h 0298h 0299h 029Ah 029Bh 029Ch 029Dh 029Eh 029Fh 02A0h 02A1h 02A2h 02A3h 02A4h 02A5h 02A6h 02A7h 02A8h 02A9h 02AAh 02ABh 02ACh 02ADh 02AEh 02AFh 02B0h 02B1h 02B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh Register Symbol Page Address 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02CBh 02CCh 02CDh 02C
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Address 0300h 0301h 0302h 0303h 0304h 0305h 0306h 0307h 0308h 0309h 030Ah 030Bh 030Ch 030Dh 030Eh 030Fh 0310h 0311h 0312h 0313h 0314h 0315h 0316h 0317h 0318h 0319h 031Ah 031Bh 031Ch 031Dh 031Eh 031Fh 0320h 0321h 0322h 0323h 0324h 0325h 0326h 0327h 0328h 0329h 032Ah 032Bh 032Ch 032Dh 032Eh 032Fh 0330h 0331h 0332h 0333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh Register Symbol Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034
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Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh Register Count Start Flag Clock Prescaler Reset Flag One-Shot Start Flag Trigger Select Register Up/Down Flag Symbol T
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Under development This document is under development and its contents are subject to change M16C/6N Group (M16C/6NK, M16C/6NM) SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER Rev.1.10 Jul 01, 2005 1. Overview The M16C/6N Group (M16C/6NK, M16C/6NM) of single-chip microcomputers are built using the high-performance silicon gate CMOS process using an M16C/60 Series CPU core and are packaged in 100-pin and 128-pin plastic molded LQFP.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.2 Performance Outline Tables 1.1 and 1.2 list a performance outline of M16C/6N Group (M16C/6NK, M16C/6NM). Table 1.1 Performance Outline of M16C/6N Group (100-pin Version: M16C/6NK) Performance Item Normal-ver. T/V-ver. CPU Number of Basic Instructions 91 instructions Minimum Instruction 41.7ns (f(BCLK) = 24MHz, 50.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NM) Performance Item Normal-ver. T/V-ver. CPU Number of Basic Instructions 91 instructions Minimum Instruction 41.7ns (f(BCLK) = 24MHz, 50.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.3 Block Diagram Figure 1.1 shows a block diagram of M16C/6N Group (M16C/6NK, M16C/6NM). 8 Port P0 8 8 Port P1 Port P3 SB ROM (1) A0 A1 FB INTB PC Rev.1.10 Jul 01, 2005 REJ09B0124-0110 page 4 of 318 Port P13 (3) (3) 2 8 Port P12 (3) 8 Port P11 (3) 8 8 Figure 1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.4 Product List Table 1.3 lists the M16C/6N Group (M16C/6NK, M16C/6NM) products and Figure 1.2 shows the type numbers, memory sizes and packages. Table 1.3 Product List Type No.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.5 Pin Configuration Figures 1.3 and 1.4 show the pin configuration (top view).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview 1.6 Pin Description Tables 1.4 and 1.5 list the pin descriptions. Table 1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1. Overview Table 1.5 Pin Description (100-pin and 128-pin Versions) (2) Signal Name Reference Pin Name VREF I/O Type Description Applies the reference voltage for the A/D converter and D/A I voltage input A/D converter converter. AN0 to AN7 I Analog input pins for the A/D converter. ADTRG I This is an A/D trigger input pin.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 2. Central Processing Unit (CPU) 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 bits, indicating the start address of an interrupt vector table. 2.5 Program Counter (PC) PC is configured with 20 bits, indicating the address of an instruction to be executed. 2.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 3. Memory 3. Memory Figure 3.1 shows a memory map of the M16C/6N Group (M16C/6NK, M16C/6NM). The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 512-Kbyte internal ROM is allocated to the addresses from 80000h to FFFFFh.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) 4. Special Function Register (SFR) SFR (Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.16 list the SFR information. Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 4. Special Function Register (SFR) Table 4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Reset 5. Reset Hardware reset, software reset, watchdog timer reset and oscillation stop detection reset are available to reset the microcomputer. 5.1 Hardware Reset ____________ The microcomputer resets pins, the CPU and SFR by setting the RESET pin.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Reset Recommended operation voltage VCC 0V RESET VCC RESET 0.2VCC or below 0.2VCC or below 0V Supply a clock with td(P-R) +20 or more cycles to the XIN pin NOTE 1. Use the shortest possible wiring to connect external circuit. Figure 5.1 Example Reset Circuit VCC XIN td(P-R) More than 20 cycle are needed RESET BCLK 28cycles BCLK FFFFCh FFFFEh Address Figure 5.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 5. Reset ____________ Table 5.1 Pin Status When RESET Pin Level is “L” Pin Name Status (CNVSS = VSS) P0, P1, P2, P3, P4, P5, P6, P7, Input port P8_0 to P8_4, P8_6, P8_7, P9, P10, P11, P12, P13, P14_0, P14_1 (2) NOTE: 1. P11, P12, P13, P14_0 and P14_1 pins are only in the 128-pin version.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 6. Processor Mode 6. Processor Mode Three processor mode is available single-chip mode only. Figures 6.1 and 6.2 show the processor mode related registers. Figure 6.3 shows the memory map.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 6.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 6.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7. Clock Generating Circuit 7.1 Types of Clock Generating Circuit Four circuits are incorporated to generate the system clock signal: • Main clock oscillation circuit • Sub clock oscillation circuit • On-chip oscillator • PLL frequency synthesizer Table 7.1 lists the clock generating circuit specifications. Figure 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit The following describes the clocks generated by the clock generating circuit. 7.1.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a resonator between the XIN and XOUT pins.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7.1.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well as the timer A and timer B count sources. In addition, an fC clock with the same frequency as that of the sub clock can be output from the CLKOUT pin.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7.1.3 On-chip Oscillator Clock This clock, approximately 1 MHz, is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit Using the PLL clock as the clock source for the CPU Set the CM07 bit to "0" (main clock), the CM17 to CM16 bits to "00b" (main clock undivided), and the CM06 bit to "0" (CM16 and CM17 bits enabled). (1) Set the PLC02 to PLC00 bits (multiplying factor). (When PLL clock > 16 MHz) Set the PM20 bit to "0" (2-wait state).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7.2 CPU Clock and Peripheral Function Clock Two type clocks: CPU clock to operate the CPU and peripheral function clocks to operate the peripheral functions. 7.2.1 CPU Clock and BCLK These are operating clocks for the CPU and watchdog timer.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7.4 Power Control Normal operation mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operation mode in this document. 7.4.1 Normal Operation Mode Normal operation mode is further classified into seven sub modes.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7.4.1.6 On-chip Oscillator Mode The on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock. The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock is activated, fC32 can be used as the count source for timers A and B. 7.4.1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7.4.2 Wait Mode In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the watchdog timer. However, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watchdog timer count source), the watchdog timer remains active.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7.4.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least amount of power is consumed in this mode. If the voltage applied to VCC is VRAM or more, the internal RAM is retained.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7.4.3.3 Exiting Stop Mode _______ Stop mode is exited by a hardware reset, NMI interrupt or peripheral function interrupt.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit Figure 7.12 shows the state transition from normal operation mode to stop mode and wait mode. Figure 7.13 shows the state transition in normal operation mode. Table 7.7 shows a state transition matrix describing allowed transition and setting. The vertical line shows current state and horizontal line show state after transition.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit Table 7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7.5 Oscillation Stop and Re-oscillation Detection Function The oscillation stop and re-oscillation detection function is such that main clock oscillation circuit stop and re-oscillation are detected. At oscillation stop, re-oscillation detection, reset or oscillation stop, re-oscillation detection interrupt request are generated.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 7. Clock Generating Circuit 7.5.3 How to Use Oscillation Stop and Re-oscillation Detection Function • The oscillation stop, re-oscillation detection interrupt shares the vector with the watchdog timer interrupt.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 8. Protection 8. Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by the PRCR register.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9. Interrupt 9.1 Type of Interrupts Figure 9.1 shows the types of interrupts.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9.2 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 9.2.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the UND instruction. 9.2.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9.3 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 9.3.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 9.3.1.1 NMI Interrupt _______ _______ An NMI interrupt is generated when input on the NMI pin changes state from high to low.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9.4 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the corresponding interrupt vector. Figure 9.2 shows the interrupt vector.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt Table 9.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9.5 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here does not apply to non-maskable interrupts.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9.5.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (enabled) enables the maskable interrupt. Setting the I flag to “0” (disabled) disables all maskable interrupts. 9.5.2 IR Bit The IR bit is set to “1” (interrupt requested) when an interrupt request is generated.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9.5.4 Interrupt Sequence An interrupt sequence — what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed — is described here.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9.5.5 Interrupt Response Time Figure 9.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes a time from when an interrupt request is generated till when the first instruction in the interrupt routine is executed.
PAGE 88
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9.5.7 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG register, 16 bits in total, are saved to the stack first. Next, the 16 low-order bits of the PC are saved. Figure 9.
PAGE 89
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9.5.8 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt sequence are restored from the stack by executing the REIT instruction at the end of the interrupt routine. Thereafter the CPU returns to the program which was being executed before accepting the interrupt request.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Priority level of each interrupt Level 0 (initial value) 9.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt ______ 9.6 INT Interrupt _______ INTi interrupt (i = 0 to 8) (1) is triggered by the edges of external inputs. The edge polarity is selected using the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9.
PAGE 94
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt ______ 9.7 NMI Interrupt _______ _______ ______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low. The NMI interrupt is a non-maskable interrupt. _______ The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register. This pin cannot be used as an input port. 9.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9. Interrupt 9.10 Address Match Interrupt An address match interrupt request is generated immediately before executing the instruction at the address indicated by the RMADi register (i = 0 to 3). Set the start address of any instruction in the RMADi register.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 9.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10. Watchdog Timer 10. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability of a system. The watchdog timer contains a 15-bit counter which counts down the clock derived by dividing the CPU clock using the prescaler.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 10.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11. DMAC 11. DMAC The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention. Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8- or 16-bit) data from the source address to the destination address. The DMAC uses the same data bus as used by the CPU.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11. DMAC Table 11.1 DMAC Specifications Item Specification No. of Channels 2 (cycle steal method) Transfer Memory Space • From any address in the 1-Mbyte space to a fixed address • From a fixed address to any address in the 1-Mbyte space • From a fixed address to a fixed address Maximum No.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11. DMAC DMA0 Request Cause Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM0SL Bit Symbol Address 03B8h After Reset 00h Function Bit Name DSEL0 DSEL1 DSEL2 RW DMA Request Cause Select Bit See NOTE 1 - RW RW DSEL3 (b5-b4) RW RW Nothing is assigned. When write, set to "0". When read, their contents are "0".
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11. DMAC DMA1 Request Cause Select Register b7 b6 b5 b4 b3 b2 b1 b0 Symbol DM1SL Bit Symbol Address 03BAh After Reset 00h Function Bit Name DSEL0 DSEL1 DSEL2 RW DMA Request Cause Select Bit RW See NOTE 1 RW DSEL3 (b5-b4) RW RW Nothing is assigned. When write, set to "0". When read, their contents are "0".
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11. DMAC DMAi Source Pointer (i = 0, 1) (1) (b23) b7 (b19) b3 (b16)(b15) b0 b7 (b8) b0 b7 b0 Symbol SAR0 SAR1 Address 0022h to 0020h 0032h to 0030h Function After Reset Indeterminate Indeterminate Setting Range 00000h to FFFFFh Set the source address of transfer Nothing is assigned. When write, set to "0". When read, their contents are "0". RW RW - NOTE: 1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11. DMAC 11.1 Transfer Cycle The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of transfer. The bus cycle itself is extended by a software wait. 11.1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11. DMAC 11.2 DMA Transfer Cycles Any combination of even or odd transfer read and write addresses is possible. Table 11.2 shows the number of DMA transfer cycles. Table 11.3 shows the coefficient j, k. The number of DMAC transfer cycles can be calculated as follows: No. of transfer cycles per transfer unit = No. of read cycles ✕ j + No. of write cycles ✕ k Table 11.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11. DMAC 11.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register (i = 0, 1) to “1” (enabled), the DMAC operates as follows: (1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON register is “1” (forward) or the DARi register value when the DAD bit in the DMiCON register is “1” (forward).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 11. DMAC 11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are detected active in the same sampling period (one period from a falling edge to the next falling edge of BCLK), the DMAS bit on each channel is set to “1” (DMA requested) at the same time.
PAGE 110
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12. Timers Eleven 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (six). The count source for each timer acts as a clock, to control such timer operations as counting, reloading, etc. Figures 12.1 and 12.2 show block diagrams of Timer A and Timer B configuration, respectively.
PAGE 111
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 1/2 Main clock f1 PLL clock On-chip oscillator clock 12.
PAGE 112
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12.1 Timer A Figure 12.3 shows a block diagram of the timer A. Figures 12.4 to 12.6 show the timer A-related registers. The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the same function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
PAGE 116
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12.1.1 Timer Mode In timer mode, the timer counts a count source generated internally. Table 12.1 lists specifications in timer mode. Figure 12.7 shows TAiMR register in timer mode. Table 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 12.2 lists specifications in event counter mode (when not processing two-phase pulse signal). Figure 12.
PAGE 118
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers Table 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value to “0” by Z-phase (counter initialization) input during twophase pulse signal processing.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. When the trigger occurs, the timer starts up and continues operating for a given period. Table 12.4 lists specifications in one-shot timer mode. Figure 12.11 shows the TAiMR register in the one-shot timer mode. Table 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12.1.4 Pulse Width Modulation (PWM) Mode In pulse width modulation mode, the timer outputs pulses of a given width in succession. The counter functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Table 12.5 lists specifications in pulse width modulation mode. Figure 12.12 shows TAiMR register in pulse width modulation mode. Figures 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 1 / fi ✕ (216 — 1) Count source Input signal to TAiIN pin "H" PWM pulse output from TAiOUT pin "H" IR bit in TAiIC register "1" "L" Trigger is not generated by this signal 1 / fj ✕ n "L" "0" Set to "0" upon accepting an interrupt request or by writing in program i = 0 to 4 fj: Frequency of count source (f1, f2, f8, f32, fC32) NOTES: 1. n = 0000h to FFFEh.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12.2 Timer B Figure 12.15 shows a block diagram of the timer B. Figures 12.16 and 12.17 show the timer B-related registers. Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0 to 5) to select the desired mode. • Timer mode : The timer counts an internal count source.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12.2.1 Timer Mode In timer mode, the timer counts a count source generated internally. Table 12.6 lists specifications in timer mode. Figure 12.18 shows TBiMR register in timer mode. Table 12.
PAGE 131
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Table 12.7 lists specifications in event counter mode. Figure 12.19 shows TBiMR register in event counter mode. Table 12.
PAGE 132
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12. Timers 12.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal. Table 12.8 lists specifications in pulse period and pulse width measurement mode. Figure 12.20 shows TBiMR register in pulse period and pulse width measurement mode. Figure 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 12.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13. Three-Phase Motor Control Timer Function 13. Three-Phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 13.1 lists the specifications of the three-phase motor control timer function. Figure 13.1 shows the block diagram for three-phase motor control timer function.
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Rev.1.10 Jul 01, 2005 REJ09B0124-0110 Timer B2 (Timer Mode) page 118 of 318 TA41 Register T Q INV11 (One-Shot Timer Mode) Timer A4 Counter Reload T Q INV11 (One-Shot Timer Mode) Timer A1 Counter TA11 Register Figure 13.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.
PAGE 138
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13. Three-Phase Motor Control Timer Function The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to “1”. When this function is selected, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are __ ___ ___ used to control three-phase PWM outputs (U, U, V, V, W and W).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 13.
PAGE 146
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14. Serial I/O Serial I/O is configured with 7 channels: UART0 to UART2 and SI/O3 to SI/O6 (1). NOTE: 1. 100-pin version supports 5 channels; UART0 to UART2, SI/O3, SI/O4 128-pin version supports 7 channels; UART0 to UART2, SI/O3 to SI/O6 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
PAGE 148
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
PAGE 150
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O UARTi Transmit Buffer Register (i = 0 to 2) (1) (b15) b7 (b8) b0 b7 b0 Symbol Address U0TB U1TB U2TB 03A3h to 03A2h 03ABh to 03AAh 01FBh to 01FAh Bit Symbol (b8-b0) (b15-b9) After Reset Indeterminate Indeterminate Indeterminate RW Function Transmit data WO Nothing is assigned When write, set to "0". When read, their contents are indeterminate.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
PAGE 153
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O UARTi Special Mode Register 2 (i = 0 to 2) b7 b6 b5 b4 b3 b2 b1 b0 Symbol U0SMR2 to U2SMR2 Bit Symbol Address 01EEh, 01F2h, 01F6h Bit Name After Reset X0000000b RW Function IICM2 I2C Mode Select Bit 2 See Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
PAGE 156
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.1 Clock Synchronous Serial I/O Mode The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 14.1 lists the specifications of the clock synchronous serial I/O mode. Table 14.2 lists the registers used in clock synchronous serial I/O mode and the register values set. Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Table 14.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table 14.3 shows pin functions for the case where the multiple transfer clock output pin select function is deselected. Table 14.4 lists the P6_4 pin functions during clock synchronous serial I/O mode.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.1.1 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode, follow the procedures below.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.1.3 LSB First/MSB First Select Function Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 14.13 shows the transfer format.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.1.5 Serial Data Logic Switching Function When the UiLCH bit in the UiC1 register (i = 0 to 2) = 1 (reverse), the data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 14.14 shows serial data logic.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O _______ _______ 14.1.1.7 CTS/RTS Function _______ ________ ________ When the CTS function is used transmit and receive operation start when “L” is applied to the CTSi/RTSi ________ ________ (i = 0 to 2) pin. Transmit and receive operation begins when the CTSi/RTSi pin is held “L”.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.2 Clock Asynchronous Serial I/O (UART) Mode The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. Table 14.5 lists the specifications of the UART mode. Table 14.6 lists the registers used in UART mode and the register values set. Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Table 14.7 lists the functions of the input/output pins during UART mode. Table 14.8 lists the P6_4 pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TXDi pin outputs an “H”. Figure 14.17 shows the typical transmit timings in UART mode. Figure 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O (1) Example of Transmit Timing when Transfer Data is 8-bit Long (parity enabled, one stop bit) The transfer clock stops momentarily as CTSi is "H" when the stop bit is checked. The transfer clock starts as the transfer starts immediately CTSi changes to "L".
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.2.2 Counter Measure for Communication Error Occurs If a communication error occurs while transmitting or receiving in UART mode, follow the procedures below.
PAGE 170
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.2.4 Serial Data Logic Switching Function The data written to the UiTB register has its logic reversed before being transmitted. Similarly, the received data has its logic reversed when read from the UiRB register. Figure 14.20 shows serial data logic.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O _______ _______ 14.1.2.6 CTS/RTS Function _______ ________ ________ When the CTS function is used transmit operation start when “L” is applied to the CTSi/RTSi (i = 0 to 2) ________ ________ pin. Transmit operation begins when the CTSi/RTSi pin is held “L”. If the “L” signal is switched to “H” during a transmit operation, the operation stops before the next data.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.3 Special Mode 1 (I2C Mode) I2C mode is provided for use as a simplified I2C interface compatible mode. Table 14.10 lists the specifications of the I2C mode. Figure 14.23 shows the block diagram for I2C mode. Table 14.11 lists the registers used in the I2C mode and the register values set. Table 14.12 lists the functions in I2C mode. Figure 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.3.1 Detection of Start and Stop Condition Whether a start or a stop condition has been detected is determined. A start condition-detected interrupt request is generated when the SDAi pin changes state from high to low while the SCLi pin is in the high state.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.3.4 Transfer Clock Data is transmitted/received using a transfer clock like the one shown in Figure 14.24. The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal SCLi) and an external clock supplied to the SCLi pin.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.3.7 ACK and NACK If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC bit in the UiSMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the UiSMR4 register is output from the SDAi pin.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.4 Special Mode 2 Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are selectable. Table 14.14 lists the specifications of Special Mode 2. Figure 14.27 shows communication control example for Special Mode 2. Table 14.15 lists the registers used in Special Mode 2 and the register values set. Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O P1_3 P1_2 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) Microcomputer (Master) P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) Microcomputer (Slave) P9_3 P7_2(CLK2) P7_1(RXD2) P7_0(TXD2) Microcomputer (Slave) Figure 14.27 Serial Bus Communication Control Example (UART2) Rev.1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.4.1 Clock Phase Setting Function One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit in the UiSMR3 register and the CKPOL bit in the UiC0 register. Make sure the transfer clock polarity and phase are the same for the master and salves to be communicated. Figure 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O "H" Slave control input "L" Clock input "H" (CKPOL= 0, CKPH = 0) "L" Clock input "H" (CKPOL = 1, CKPH = 0) "L" Data output timing "H" D0 "L" Data input timing D1 D2 D3 D4 D5 D6 D7 Indeterminate Figure 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.5 Special Mode 3 (IE Mode) In this mode, one bit of IEBus is approximated with one byte of UART mode waveform. Table 14.16 lists the registers used in IE mode and the register values set. Figure 14.31 shows the functions of bus collision detect function related bits.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O (1) ABSCS Bit in UiSMR Register (bus collision detect sampling clock select) If ABSCS bit = 0, bus collision is determined at the rising edge of the transfer clock Transfer clock ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP TXDi RXDi Input to TAjIN Timer Aj If ABSCS bit = 1, bus collision is determined when timer Aj (one-shot timer mode) underflows.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.6 Special Mode 4 (SIM Mode) (UART2) Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be implemented, and this mode allows to output a low from the TXD2 pin when a parity error is detected. Table 14.17 lists the specifications of SIM mode. Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Table 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Figure 14.33 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up. Microcomputer SIM card TXD2 RXD2 Figure 14.33 SIM Interface Connection 14.1.6.1 Parity Error Signal Output The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to “1”.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.1.6.2 Format When direct format, set the PRY bit in the U2MR register to “1”, the UFORM bit in the U2C0 register to “0” and the U2LCH bit in the U2C1 register to “0”. When inverse format, set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”. Figure 14.35 shows the SIM interface format.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.2 SI/Oi (i = 3 to 6) (1) SI/Oi is exclusive clock-synchronous serial I/Os. Figure 14.36 shows the block diagram of SI/Oi, and Figures 14.37 and 14.38 show the SI/Oi-related registers.Table 14.19 lists the specifications of SI/Oi. NOTE: 1. 100-pin version supports SI/O3 and SI/O4. 128-pin version supports SI/O3, SI/O4, SI/O5 and SI/O6.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O Table 14.19 SI/Oi Specifications Item Specification Transfer Data Format Transfer data length: 8 bits Transfer clock • SMi6 bit in SiC register = 1 (internal clock) : fj/ 2(n+1) Transmission/Reception fj = f1SIO, f8SIO, f32SIO.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.2.1 SI/Oi Operation Timing Figure 14.39 shows the SI/Oi operation timing. 1.5 cycle (max.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 14. Serial I/O 14.2.3 Functions for Setting an SOUTi Initial Value If the SMi6 bit in the SiC register = 0 (external clock), the SOUTi pin output can be fixed high or low when not transferring (1). Figure 14.41 shows the timing chart for setting an SOUTi initial value and how to set it. NOTE: 1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15. A/D Converter 15. A/D Converter The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method configured with a capacitive-coupling amplifier. The analog inputs share the pins with P10_0 to P10_7, _____________ P9_5, P9_6, P0_0 to P0_7, and P2_0 to P2_7. Similarly, ADTRG input shares the pin with P9_7.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15. A/D Converter 15.1 Mode Description 15.1.1 One-shot Mode In one-shot mode, analog voltage applied to a selected pin is A/D converted once. Table 15.2 lists the specifications of one-shot mode. Figure 15.4 shows the ADCON0 and ADCON1 registers in one-shot mode. Table 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15. A/D Converter 15.1.2 Repeat Mode In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table 15.3 lists the specifications of repeat mode. Figure 15.5 shows the ADCON0 and ADCON1 registers in repeat mode. Table 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15. A/D Converter 15.1.3 Single Sweep Mode In single sweep mode, analog voltage that is applied to selected pins is converted one-by-one to a digital code. Table 15.4 lists the specifications of single sweep mode. Figure 15.6 shows the ADCON0 and ADCON1 registers in single sweep mode. Table 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15. A/D Converter 15.1.4 Repeat Sweep Mode 0 In repeat sweep mode 0, analog voltage applied to selected pins is repeatedly converted to a digital code. Table 15.5 lists the specifications of repeat sweep mode 0. Figure 15.7 shows the ADCON0 and ADCON1 registers in repeat sweep mode 0. Table 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15. A/D Converter 15.1.5 Repeat Sweep Mode 1 In repeat sweep mode 1, analog voltage selectively applied to all pins is repeatedly converted to a digital code. Table 15.6 lists the specifications of repeat sweep mode 1. Figure 15.8 shows the ADCON0 and ADCON1 registers in repeat sweep mode 1. Table 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15. A/D Converter 15.2 Function 15.2.1 Resolution Select Function The desired resolution can be selected using the BITS bit in the ADCON1 register. If the BITS bit is set to “1” (10-bit conversion accuracy), the A/D conversion result is stored in the bit 0 to bit 9 in the ADi register (i = 0 to 7).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15. A/D Converter 15.2.5 Current Consumption Reducing Function When not using the A/D converter, its resistor ladder and reference voltage input pin (VREF) can be separated using the VCUT bit in the ADCON1 register. When separated, no current will flow from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 15. A/D Converter Microcomputer Sensor equivalent circuit R0 VIN R (7.8 kΩ) Sampling time C (1.5 pF) VC Sample and hold function enabled: 3 fAD Sample and hold function disabled: 2 fAD Figure 15.10 Analog Input Pin and External Sensor Equivalent Circuit Rev.1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 16. D/A Converter 16. D/A Converter This is an 8-bit, R-2R type D/A converter. These are two independent D/A converters. D/A conversion is performed by writing to the DAi register (i = 0, 1). To output the result of conversion, set the DAiE bit in the DACON register to “1” (output enabled).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 16. D/A Converter D/A Control Register (1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol Address After Reset DACON 03DCh 00h Bit Symbol Bit Name Function DA0E D/A0 Output Enable Bit 0 : Output disabled 1 : Output enabled DA1E D/A1 Output Enable Bit 0 : Output disabled 1 : Output enabled (b7-b2) RW Nothing is assigned. When write, set to "0".
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 17. CRC Calculation 17. CRC Calculation The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses a generator polynomial of CRC-CCITT (X16 + X12 + X5 + 1) to generate CRC code. The CRC code consists of 16 bits which are generated for each data block in given length, separated in 8-bit unit.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 17.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18. CAN Module The CAN (Controller Area Network) module for the M16C/6N Group (M16C/6NK, M16C/6NM) of microcomputers is a communication controller implementing the CAN 2.0B protocol. The M16C/6N Group (M16C/6NK, M16C/6NM) contains two CAN modules which can transmit and receive messages in both standard (11-bit) ID and extended (29-bit) ID formats. Figure 18.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.1 CAN Module-Related Registers The CANi (i = 0, 1) module has the following registers. 18.1.1 CAN Message Box A CAN module is equipped with 16 slots (16 bytes or 8 words each). Slots 14 and 15 can be used as Basic CAN. • Priority of the slots: The smaller the number of the slot, the higher the priority, in both transmission and reception.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.2 CANi Message Box (i = 0, 1) Table 18.1 shows the memory mapping of the CANi message box. It is possible to access to the message box in byte or word. Mapping of the message contents differs from byte access to word access. Byte access or word access can be selected by the MsgOrder bit of the CiCTLR register. Table 18.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module Figures 18.2 and 18.3 show the bit mapping in each slot in byte access and word access. The content of each slot remains unchanged unless transmission or reception of a new message is performed.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.3 Acceptance Mask Registers Figures 18.4 and 18.5 show the CiGMR register (i = 0, 1), the CiLMAR register, and the CiLMBR register, in which bit mapping in byte access and word access are shown.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.4 CAN SFR Registers Figures 18.6 to 18.11 show the CAN SFR registers.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module CANi Status Register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0STR C1STR Address 0212h 0232h Bit Symbol Bit Name After Reset 00h 00h Function RW b3 b2 b1 b0 Active Slot Bits (1) 0 0 0 0 : Slot 0 0 0 0 1 : Slot 1 0 0. 1 0 : Slot 2 ..
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module CANi Slot Status Register (i = 0, 1) (b15) b7 (b8) b0 b7 b0 Symbol C0SSTR C1SSTR Address 0215h, 0214h 0235h, 0234h After Reset 0000h 0000h Setting Values RW 0: Reception slot The message has been read. Transmission slot Transmission is not completed. 1: Reception slot The message has not been read. Transmission slot Transmission is completed.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module CANi Configuration Register (i = 0, 1) b7 b6 b5 b4 b3 b2 b1 b0 Symbol C0CONR C1CONR Bit Symbol Address 021Ah 023Ah After Reset Indeterminate Indeterminate Bit Name Function RW b3 b2 b1 b0 0 0 0 0 : Divide-by-1 of fCAN 0 0 0 1 : Divide-by-2 of fCAN 0 0 1 0 : Divide-by-3 of fCAN .....
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module CANi Receive Error Count Register (i = 0, 1) b7 b0 Symbol C0RECR C1RECR Address 021Ch 023Ch After Reset 00h 00h Counter Value Function Reception error counting function The value is incremented or decremented according to the CAN module’s error status. 00h to FFh (1) RW RO NOTE: 1. The value is indeterminate in bus off state.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.5 Operational Modes The CAN module has the following four operational modes. • CAN Reset/Initialization Mode • CAN Operation Mode • CAN Sleep Mode • CAN Interface Sleep Mode Figure 18.12 shows transition between operational modes.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.5.2 CAN Operation Mode The CAN operation mode is activated by setting the Reset bit in the CiCTLR register (i = 0, 1) to “0”. If the Reset bit is set to “0”, check that the State_Reset bit in the CiSTR register is set to “0”.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.5.5 Bus Off State The bus off state is entered according to the fault confinement rules of the CAN specification. When returning to the CAN operation mode from the bus off state, the module has the following two cases. In this time, the value of any CAN registers, except CiSTR, CiRECR and CiTECR registers, does not change.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.6 Configuration CAN Module System Clock The M16C/6N Group (M16C/6NK, M16C/6NM) has a CAN module system clock select circuit. Configuration of the CAN module system clock can be done through manipulating the CCLKR register and the BRP bit in the CiCONR register (i = 0, 1). For the CCLKR register, refer to 7. Clock Generating Circuit. Figure 18.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.8 Bit-rate Bit-rate depends on f1, the division value of the CAN module system clock, the division value of the baud rate prescaler, and the number of Tq of one bit. Table 18.2 shows the examples of bit-rate. Table 18.2 Examples of Bit-rate Bit-rate 24MHz 1Mbps 12Tq (1) 500kbps 12Tq (2) 24Tq (1) 125kbps 12Tq (8) 16Tq (6) 24Tq (4) 83.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.9 Acceptance Filtering Function and Masking Function These functions serve the users to select and receive a facultative message. The CiGMR register (i = 0, 1), the CiLMAR register, and the CiLMBR register can perform masking to the standard ID and the extended ID of 29 bits.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.10 Acceptance Filter Support Unit (ASU) The acceptance filter support unit has a function to judge valid/invalid of a received ID through table search. The IDs to receive are registered in the data table; a received ID is stored in the CiAFS register ( i = 0, 1), and table search is performed with a decoded received ID.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.11 Basic CAN Mode When the BasicCAN bit in the CiCTLR register (i = 0, 1) is set to “1” (Basic CAN mode enabled), slots 14 and 15 correspond to Basic CAN mode. In normal operation mode, each slot can handle only one type message at a time, either a data frame or a remote frame by setting CiMCTLj regisrer (j = 0 to 15).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.12 Return from Bus Off Function When the protocol controller enters bus off state, it is possible to make it forced return from bus off state by setting the RetBusOff bit in the CiCTLR register (i = 0, 1) to “1” (Force return from bus off). At this time, the error state changes from bus off state to error active state.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.15 Reception and Transmission Table 18.3 shows configuration of CAN reception and transmission mode. Table 18.3 Configuration of CAN Reception and Transmission Mode TrmReq RecReq Remote RspLock Communication Mode of Slot 0 0 Communication environment configuration mode: configure the communication mode of the slot.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.15.1 Reception Figure 18.20 shows the behavior of the module when receiving two consecutive CAN messages, that fit into the slot of the shown CiMCTLj register (i = 0, 1, j = 0 to 15) and leads to losing/overwriting of the first message.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.15.2 Transmission Figure 18.21 shows the timing of the transmit sequence. SOF ACK EOF IFS SOF (1) (4) TrmActive bit (1) (2) (3) SentData bit (3) CANi Successful Transmission Interrupt (3) TrmState bit (1) (2) TrmSucc bit MBOX bit Transmission slot No. CiSTR register TrmReq bit CiMCTLj register CTX i = 0, 1 j = 0 to 15 Figure 18.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 18. CAN Module 18.16 CAN Interrupt The CAN module provides the following CAN interrupts.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19. Programmable I/O Ports 19. Programmable I/O Ports The programmable input/output ports (hereafter referred to simply as I/O ports) consist of 87 lines P0 to P10 in the 100-pin version and consist of 113 lines P0 to P14 in the 128-pin version.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19. Programmable I/O Ports 19.1 PDi Register (100-pin Version: i = 0 to 10, 128-pin Version: i = 0 to 13) Figure19.7 shows the PDi register. This register selects whether the I/O port is to be used for input or output. The bits in this register correspond one for one to each port. No direction register bit for P8_5 is available. 19.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19. Programmable I/O Ports Pull-up selection Direction register P8_7 Data bus Port latch (NOTE 1) fC Rf Pull-up selection Rd Direction register P8_6 "1" Data bus Port latch Output (NOTE 1) NOTE: 1. Symbolizes a parasitic diode. Make sure the input voltage on each port will not exceed VCC. Figure19.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 19. Programmable I/O Ports Table 19.2 Unassigned Pin Handling Pin Name Connection Ports P0 to P7, P8_0 to P8_4, After setting for input mode, connect every pin to VSS via a resistor (pull-down); or after setting for output mode, leave these pins open.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20. Flash Memory Version Aside from the built-in flash memory, the flash memory version microcomputer has the same functions as the masked ROM version. In the flash memory version, the flash memory can perform in four rewrite mode: CPU rewrite mode, standard serial I/O mode, parallel I/O mode and CAN I/O mode. Table 20.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.1 Memory Map The flash memory contains the user ROM area and a boot ROM area. The user ROM area has space to store the microcomputer operating program a separate 4-Kbyte space as the block A. Figure 20.1 shows the block diagram of flash memory.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.1.1 Boot Mode The microcomputer enters boot mode when a hardware reset occurs while an “H ” signal is applied to the CNVSS and P5_0 pins and an “L ” signal is applied to the P5_5 pin. A program in the boot ROM area is executed. In boot mode, the FMR05 bit in the FMR0 register selects access to the boot ROM area or the user ROM area.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version ROM Code Protect Control Address b7 b6 b5 b4 b3 b2 b1 b0 Symbol ROMCP 1 1 1 1 1 1 Bit Symbol (b5-b0) Address 0FFFFFh Value when Shipped FFh (1) Bit Name Reserved Bit Function Set to "1" RW RW b7 b6 ROMCP1 ROM Code Protect Level 1 Set Bit (1) (2) (3) (4) 00: 0 1 : Protect enabled 10: 1 1 : Protect disabled RW RW NOTES: 1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3 CPU Rewrite Mode In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands. The user ROM area can be rewritten with the microcomputer is mounted on a board without using a parallel, serial or CAN programmer. In CPU rewrite mode, only the user ROM area shown in Figure 20.1 can be rewritten.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.1 EW0 Mode The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU rewrite mode enabled) and is ready to accept commands. EW0 mode is selected by setting the FMR11 bit in the FMR1 register to “0”. To set the FMR01 bit to “1”, set to “1” after first writing “0”.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.3 FMR0, FMR1 Registers Figure 20.4 shows FMR0 and FMR1 registers.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.3.1 FMR00 Bit This bit indicates the flash memory operating status. It is set to “0” while the program, block erase, erase all unlocked block, lock bit program, or read lock bit status command is being executed; otherwise, it is set to “1”. 20.3.3.2 FMR01 Bit The microcomputer can accept commands when the FMR01 bit is set to “1” (CPU rewrite mode).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.4 Precautions on CPU Rewrite Mode 20.3.4.1 Operating Speed Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to clock frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to “1” (with wait state). 20.3.4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.4.9 Writing Command and Data Write commands and data to even addresses in the user ROM area. 20.3.4.10 Wait Mode When entering wait mode, set the FMR01 bit in the FMR0 register to “0” (CPU rewrite mode disabled) before executing the WAIT instruction. 20.3.4.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.5 Software Commands Software commands are described below. The command code and data must be read and written in 16-bit unit, to and from even addresses in the user ROM area. When writing command code, the high-order 8 bits (D15 to D8) are ignored. Table 20.4 lists the software commands. Table 20.
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e e o e e s t s o Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.5.4 Program Command (40h) The program command writes 2-byte data to the flash memory. By writing “xx40h” in the first bus cycle and data to the write address in the second bus cycle, an auto program operation (data program and verify) will start.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.5.5 Block Erase Command The block erase command erases each block. By writing “xx20h” in the first bus cycle and “xxD0h” to the highest-order even address of a block in the second bus cycle, an auto erase operation (erase and verify) will start in the specified block.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.5.6 Erase All Unlocked Block The erase all unlocked block command erases all blocks except the block A. By writing “xxA7h” in the first bus cycle and “xxD0h” in the second bus cycle, an auto erase (erase and verify) operation will run continuously in all blocks except the block A.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.5.8 Read Lock Bit Status Command (71h) The read lock bit status command reads the lock bit state of a specified block.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.6 Data Protect Function Each block in the flash memory has a nonvolatile lock bit. The lock bit is enabled by setting the FMR02 bit in the FMR0 register to “0” (lock bit enabled). The lock bit allows each block to be individually protected (locked) against program and erase.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version Table 20.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.3.8 Full Status Check If an error occurs when a program or erase operation is completed, the FMR06, FMR07 bits in the FMR0 register are set to “1”, indicating a specific error. Therefore, execution results can be confirmed by checking these bits (full status check). Table 20.6 lists errors and FMR0 register state. Figure 20.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version Full status check FMR06 =1 and FMR07=1? YES Command sequence error (1) Execute the clear status register command and set the SR4 and SR5 bits to "0" (completed as expected). (2) Rewrite command and execute again. Erase error (1) Execute the clear status register command and set the SR5 bit to "0". (2) Execute the lock bit read status command.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.4 Standard Serial I/O Mode In standard serial I/O mode, the serial programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM) can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board. For more information about the serial programmer, contact your serial programmer manufacturer.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version Table 20.7 Pin Functions for Standard Serial I/O Mode Pin Name VCC1, VCC2, VSS CNVSS Description I/O Power supply Apply the voltage guaranteed for Program and Erase to VCC1 pin input and VCC2 to VCC2 pin. The VCC apply condition is that VCC2 = VCC1. Apply 0 V to VSS pin. CNVSS I Connect to VCC1 pin. Reset input I Reset input pin.
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Under development This document is under development and its contents are subject to change. 20.
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Under development This document is under development and its contents are subject to change. 20.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.4.2 Example of Circuit Application in Standard Serial I/O Mode Figures 20.15 and 20.16 show example of circuit application in standard serial I/O mode 1 and mode 2, respectively. Refer to the user’s manual of your serial programmer to handle pins controlled by a serial programmer.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.5 Parallel I/O Mode In parallel I/O mode, the user ROM area and the boot ROM area can be rewritten by a parallel programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM). Contact your parallel programmer manufacturer for more information on the parallel programmer. Refer to the user's manual included with your parallel programmer for instructions.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.6 CAN I/O Mode In CAN I/O mode, the CAN programmer supporting the M16C/6N Group (M16C/6NK, M16C/6NM) can be used to rewrite the flash memory user ROM area in the microcomputer mounted on a board. For more information about the CAN programmer, contact your CAN programmer manufacturer.
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Under development This document is under development and its contents are subject to change. 20.
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Under development This document is under development and its contents are subject to change. 20.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 20. Flash Memory Version 20.6.2 Example of Circuit Application in CAN I/O Mode Figure 20.19 shows example of circuit application in CAN I/O mode. Refer to the user’s manual of your CAN programmer to handle pins controlled by a CAN programmer.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21. Electric Characteristics 21. Electrical Characteristics Table 21.1 Absolute Maximum Ratings Condition Rated Value Unit VCC Supply Voltage (VCC1 = VCC2) VCC = AVCC –0.3 to 6.5 V AVCC Analog Supply Voltage VCC = AVCC VI Input RESET, CNVSS, BYTE, Voltage P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, Symbol Parameter –0.3 to 6.5 V –0.3 to VCC+0.3 V –0.3 to 6.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21. Electric Characteristics Table 21.2 Recommended Operating Conditions (1) Symbol (1) Parameter VCC Supply Voltage (VCC1 = VCC2) AVCC Analog Supply Voltage VSS Supply Voltage AVSS Analog Supply Voltage VIH HIGH Input P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, Voltage P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_0, P7_2 to P7_7, Min. 3.0 Standard Max.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21. Electric Characteristics Table 21.3 Recommended Operating Conditions (2) Symbol f(XIN) (1) Parameter Min. Main Clock Input Oscillation No Wait Mask ROM Version VCC = 3.0 to 5.5V Frequency (2) (3) (4) Standard Max. Typ.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 21.4 Electrical Characteristics (1) (1) Parameter Symbol VOH 21.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 21.5 Electrical Characteristics (2) Symbol ICC 21. Electric Characteristics (1) Parameter Measuring Condition Min. Power Supply Output pins are open Mask ROM f(BCLK) = 24MHz, Current and other pins are VSS. PLL operation, (VCC = 3.0 to 5.5V) Standard Typ. Max.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Table 21.6 A/D Conversion Characteristics Symbol (1) Parameter – Resolution INL Integral 10 bits Error 8 bits Absolute Measuring Condition Min. VREF = VCC VREF ANEX0, ANEX1 input, AN0 to AN7 input, Standard Typ. Max. 10 = VCC AN0_0 to AN0_7 input, AN2_0 to AN2_7 input = 5V External operation amp connection mode Nonlinearity – 21.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21. Electric Characteristics Table 21.8 Flash Memory Version Electrical Characteristics Parameter Symbol (1) Min. Standard Typ. Max. - Word Program Time 30 200 - Block Erase Time 1 4 - Erase All Unlocked Blocks Time - Lock Bit Program Time tps Flash Memory Circuit Stabilization Wait Time 1✕n 30 µs s 4✕n (2) Unit (2) s 200 µs 15 µs NOTES: 1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21. Electric Characteristics Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified) Table 21.11 External Clock Input (XIN Input) Symbol Parameter Standard Min. Max. 62.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21. Electric Characteristics Timing Requirements (Referenced to VCC = 5V, VSS = 0V, at Topr = –40 to 85°C unless otherwise specified) Table 21.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 21.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22. Usage Precaution 22.1 SFR There is the SFR which can not be read (containg bits that will result in unknown data when read). Please set these registers to their previous values with the instructions other than the read modify write instructions. Table 22.1 lists the registers contain bits that will result in unknown data when read and Table 22.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.2 External Clock Do not stop the external clock when it is connected to the XIN pin and the main clock is selected as the CPU clock. Rev.1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.3 PLL Frequency Synthesizer Stabilize supply voltage so that the standard of the power supply ripple is met. (Refer to 21. Electrical characteristics.) Rev.1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.4 Power Control ____________ When exiting stop mode by hardware reset, set RESET pin to “L” until a main clock oscillation is stabilized. Set the MR0 bit in the TAiMR register (i = 0 to 4) to “0” (pulse is not output) to use the timer A to exit stop mode.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution Suggestions to reduce power consumption. Ports The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A current flows in active I/O ports. A pass current flows in input ports that high-impedance state. When entering wait mode or stop mode, set non-used ports to input and stabilize the potential.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.5 Oscillation Stop, Re-oscillation Detection Function If the following conditions are all met, the following restriction occur in operation of oscillation stop, re-oscillation stop detection interrupt.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.6 Protection Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be set to “0” (write protected). The registers protected by the PRC2 bit should be changed in the next instruction after setting the PRC2 bit to “1”.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.7 Interrupt 22.7.1 Reading Address 00000h Do not read the address 00000h in a program. When a maskable interrupt request is accepted, the CPU reads interrupt information (interrupt number and interrupt request priority level) from the address 00000h during the interrupt sequence. At this time, the IR bit for the accepted interrupt is set to “0”.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.7.4 Changing Interrupt Generate Factor If the interrupt generate factor is changed, the IR bit of the interrupt control register for the changed interrupt may inadvertently be set to “1” (interrupt requested).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.7.6 Rewrite Interrupt Control Register (a) The interrupt control register for any interrupt should be modified in places where no interrupt requests may be generated. Otherwise, disable the interrupt before rewriting the interrupt control register.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.8 DMAC 22.8.1 Write to DMAE Bit in DMiCON Register (i = 0, 1) When both of the conditions below are met, follow the steps below. Conditions • The DMAE bit is set to “1” again while it remains set (DMAi is in an active state). • A DMA request may occur simultaneously when the DMAE bit is being written.
PAGE 308
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.9 Timers 22.9.1 Timer A 22.9.1.1 Timer A (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count starts).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.9.1.2 Timer A (Event Counter Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
PAGE 310
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.9.1.3 Timer A (One-shot Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.9.1.4 Timer A (Pulse Width Modulation Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR (i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).
PAGE 312
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.9.2 Timer B 22.9.2.1 Timer B (Timer Mode) The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR (i = 0 to 5) register and TBi register before setting the TBiS bit (1) in the TABSR or the TBSR register to “1” (count starts).
PAGE 313
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.9.2.3 Timer B (Pulse Period/pulse Width Measurement Mode) The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 5) register before setting the TBiS bit in the TABSR or TBSR register to “1” (count starts).
PAGE 314
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.10 Thee-Phase Motor Control Timer Function If there is a possibility that you may write data to TAi-1 register (i = 1, 2, 4) near Timer B2 overflow, read the value of TB2 register, verify that there is sufficient time until Timer B2 overflows, before doing an immediate write to TAi-1 register.
PAGE 315
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.11 Serial I/O 22.11.1 Clock Synchronous Serial I/O Mode 22.11.1.1 Transmission/reception _______ ________ With an external clock selected, and choosing the RTS function, the output level of the RTSi pin goes to “L” when the data-receivable status becomes ready, which informs the transmission side that the recep________ ________ tion has become ready.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.11.2 Special Modes 22.11.2.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.11.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.12 A/D Converter Set the ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before a trigger occurs). When the VCUT bit in the ADCON1 register is changed from “0” (VREF not connected) to “1” (VREF connected), start A/D conversion after passing 1 µs or longer.
PAGE 319
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution If the CPU reads the ADi register at the same time the conversion result is stored in the ADi register after completion of A/D conversion, an incorrect value may be stored in the ADi register. This problem occurs when a divide-by-n clock derived from the main clock or a sub clock is selected for CPU clock.
PAGE 320
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.13 CAN Module 22.13.1 Reading CiSTR Register (i = 0, 1) The CAN module on the M16C/6N Group (M16C/6NK, M16C/6NM) updates the status of the CiSTR register in a certain period. When the CPU and the CAN module access to the CiSTR register at the same time, the CPU has the access priority; the access from the CAN module is disabled.
PAGE 321
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution fCAN CPU read signal Updating period of CAN module CPU reset signal ✕ CiSTR register b8: State_Reset bit 0: CAN operation mode 1: CAN reset/initialization mode ✕ ✕ ✕ ✕ ✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read period, it does not enter reset mode, for the CPU read has the higher priority. i = 0, 1 Figure 22.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.13.2 Performing CAN Configuration If the Reset bit in the CiCTLR register (i = 0, 1) is changed from “0” (operation mode) to “1” (reset/ initialization mode) in order to place the CAN module from CAN operation mode into CAN reset/initialization mode, always be sure to check that the State_Reset bit in the CiSTR register is set to “1” (reset mode).
PAGE 323
Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.13.3 Suggestions to Reduce Power Consumption When not performing CAN communication, the operation mode of CAN transceiver should be set to “standby mode” or “sleep mode”.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.13.4 CAN Transceiver in Boot Mode When programming the flash memory in boot mode via CAN bus, the operation mode of CAN transceiver should be set to “high-speed mode” or “normal operation mode”.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.14 Programmable I/O Ports _______ If a low-level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC register = 1 (three-phase _______ output forcible cutoff by input on NMI pin enabled), the P7_2 to P7_5, P8_0 and P8_1 pins go to a highimpedance state.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.15 Dedicated Input Pin When dedicated input pin voltage is larger than VCC pin voltage, latch up occurs. When different power supplied to the system, and input voltage of unused dedicated input pin is larger than voltage of VCC pin, connect dedicated input pin to VCC via resistor (approximately 1kΩ). Figure 22.8 shows the circuit connection.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.16 Electrical Characteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics, operating margin, noise tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern, etc.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22.17 Mask ROM Version When using the masked ROM version, write nothing to internal ROM area. Rev.1.10 Jul 01, 2005 REJ09B0124-0110 page 310 of 318 22.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.18 Flash Memory Version 22.18.1 Functions to Prevent Flash Memory from Rewriting ID codes are stored in addresses 0FFFDFh, 0FFFE3h, 0FFFEBh, 0FFFEFh, 0FFFF3h, 0FFFF7h, and 0FFFFBh. If wrong data are written to theses addresses, the flash memory cannot be read or written in standard serial I/O mode and CAN I/O mode.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.18.8 Operation Speed Set the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1 register to clock frequency of 10 MHz or less before entering CPU rewrite mode (EW0 or EW1 mode). Also, set the PM17 bit in the PM1 register to “1” (with wait state). 22.18.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.19 Flash Memory Programming Using Boot Program When programming the internal flash memory using boot program, be careful about the pins state and connection as follows. 22.19.1 Programming Using Serial I/O Mode CTX0 pin : This pin automatically outputs “H” level. CRX0 pin : Connect to CAN transceiver or connect via resister to VCC (pull-up) Figure 22.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) 22. Usage Precaution 22.20 Noise Connect a bypass capacitor (approximately 0.1 µF) across the VCC1 and VSS pins, and VCC2 and VSS pins using the shortest and thicker possible wiring. Figure 22.11 shows the bypass capacitor connection.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Appendix 1. Package Dimensions Appendix 1. Package Dimensions JEITA Package Code RENESAS Code P-LQFP100-14x14-0.50 PLQP0100KB-A Previous Code MASS[Typ.] 100P6Q-A / FP-100U / FP-100UV 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Memo Rev.1.10 Jul 01, 2005 REJ09B0124-0110 page 316 of 318 Appendix 1.
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) Register Index Register Index A DM0SL ............................................ 84 AD0 to AD7 ................................... 184 DM1SL ............................................ 85 DTT ............................................... 121 ADCON0 .... 183,186,188,190,192,194 ADCON1 .... 183,186,188,190,192,194 ADCON2 ....................................... 184 ADIC ..
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Under development This document is under development and its contents are subject to change. M16C/6N Group (M16C/6NK, M16C/6NM) U0C0 to U2C0 ............................... 133 U0C1 to U2C1 ............................... 134 U0MR to U2MR ............................. 133 U0RB to U2RB .............................. 132 U0SMR to U2SMR ........................ 135 U0SMR2 to U2SMR2 .................... 136 U0SMR3 to U2SMR3 .................... 136 U0SMR4 to U2SMR4 .................... 137 U0TB to U2TB ......
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REVISION HISTORY Rev. Date M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Page Summary 1.00 Sep. 30, 2004 – First edition issued 1.01 Nov. 01, 2004 – Revised edition issued * Revised parts and revised contents are as follows (except for expressional change). 3 Table 1.2 Performance Outline of M16C/6N Group (128-pin Version: M16C/6NM) • Interrupt: Internal interrupt source is revised from “32 sources” to “34 sources”. 270 Table 21.
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REVISION HISTORY Rev. Date 1.10 Jul. 01, 2005 M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Description Page 212 Summary Figure 18.11 C0RECR, C1RECR Registers, C0TECR, C1TECR Registers, C0TSR, C1TSR Registers, and C0AFS, C1AFS Registers • C0RECR, C1RECR Registers: NOTE 2 is deleted. • C0TECR, C1TECR Registers: NOTE 1 is deleted. • C0TSR, C1TSR Registers: NOTE 1 is deleted. 223 228 18.15.1 Reception (1): “(refer to 18.15.2 Transmission)” is deleted. Figure 19.
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M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual Publication Data : Rev.1.00 Sep 30, 2004 Rev.1.10 Jul 01, 2005 Published by : Sales Strategic Planning Div. Renesas Technology Corp. © 2005. Renesas Technology Corp., All rights reserved. Printed in Japan.
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M16C/6N Group (M16C/6NK, M16C/6NM) Hardware Manual 2-6-2, Ote-machi, Chiyoda-ku, Tokyo, 100-0004, Japan