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To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry

Summary of content (59 pages)

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To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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M16C/30P Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. REJ03B0088-0122 Rev.1.22 Mar 30, 2007 Overview The M16C/30P Group of single-chip microcomputers is built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and is packaged in a 100-pin plastic molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed.
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M16C/30P Group 1.2 1. Overview Performance Outline Table 1.1 lists Performance Outline of M16C/30P Group. Table 1.1 Performance Outline of M16C/30P Group Item Performance Number of Basic Instructions 91 instructions Minimum Instruction 62.5ns(f(XIN)=16MHz, VCC1=VCC2=3.0 to 5.5V, no wait) Execution Time 100ns(f(XIN)=10MHz, VCC1=VCC2=2.7 to 5.5V, no wait) Operation Mode Single-chip, memory expansion and microprocessor mode Memory Space 1 Mbyte Memory Capacity See Table 1.
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M16C/30P Group 1.3 1. Overview Block Diagram Figure 1.1 is a M16C/30P Group Block Diagram.
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M16C/30P Group 1.4 1. Overview Product List Table 1.2 lists the M16C/30P group products and Figure 1.2 shows the Part No., Memory Size, and Package. Table 1.4 lists Product Code of MASK ROM version for M16C/30P. Figure 1.3 shows the Marking Diagram of Mask ROM Version for M16C/30P (Top View). Table 1.5 lists Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P. Figure 1.
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M16C/30P Group Table 1.3 1. Overview Product List (2) Part No.
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M16C/30P Group Table 1.4 1. Overview Product Code of MASK ROM version for M16C/30P Product Code Package Operating Ambient Temperature U1 Lead-free -20°C to 85°C U4 -40°C to 85°C PRQP0100JB-A (100P6S-A) 1. Standard Renesas Mark M1 6C M3 0 3 0 2 M D P - X X X F P A U1 XXXXXXX Part No. (See Figure 1.2 Part No., Memory Size, and Package) Chip version, product code and date code A : Shows chip version. Henceforth, whenever it changes a version, it continues with A, B, and C.
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M16C/30P Group Table 1.5 1.
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M16C/30P Group 1.5 1. Overview Pin Configuration Figures 1.5 to 1.6 show the pin configurations (top view).
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M16C/30P Group 1.
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M16C/30P Group Table 1.6 Pin No. FP GP 1.
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M16C/30P Group Table 1.7 1. Overview Pin Characteristics (2) Pin No.
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M16C/30P Group 1.6 1. Overview Pin Description Table 1.8 Pin Description (1) Signal Name Power supply input Analog power supply input Reset input Pin Name VCC1, VCC2 VSS AVCC AVSS RESET CNVSS CNVSS External data bus width select input BYTE Bus control pins D0 to D7 D8 to D15 A0 to A19 I : Input O : Output I/O Type Description I Apply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS pin. The VCC apply condition is that VCC1 = VCC2. I Applies the power supply for the A/D converter.
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M16C/30P Group Table 1.9 Signal Name Main clock input Main clock output Sub clock input Sub clock output Clock output 1. Overview Pin Description (2) Pin Name XIN I/O Type I Description I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To use the external clock, input the clock from XIN and leave XOUT open. XOUT O XCIN I XCOUT O CLKOUT The clock of the same cycle as fC, f8, or f32 is outputted.
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M16C/30P Group 2. 2. Central Processing Unit (CPU) Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a register bank. There are two register banks.
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M16C/30P Group 2.2 2. Central Processing Unit (CPU) Address Registers (A0 and A1) The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0. In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0). 2.3 Frame Base Register (FB) FB is configured with 16 bits, and is used for FB relative addressing. 2.
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M16C/30P Group 2.8.8 2. Central Processing Unit (CPU) Stack Pointer Select Flag (U Flag) ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”. The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software interrupt Nos. 0 to 31 is executed. 2.8.9 Processor Interrupt Priority Level (IPL) IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7.
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M16C/30P Group 3. 3. Memory Memory Figure 3.1 is a Memory Map of the M16C/30P group. The address space extends the 1 Mbyte from address 00000h to FFFFFh. The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte internal ROM is allocated to the addresses from F0000h to FFFFFh. The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start address of each interrupt routine here.
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M16C/30P Group 4. 4. Special Function Register (SFR) Special Function Register (SFR) SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.5 list the SFR information. Table 4.
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M16C/30P Group Table 4.2 Address 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h 0058h 0059h 005Ah 005Bh 005Ch 005Dh 005Eh 005Fh 0060h to 01AFh 01B0h 01B1h 01B2h 01B3h 01B4h 01B5h 01B6h 01B7h 01B8h 01B9h 01BAh 01BBh 01BCh 01BDh 01BEh 01BFh 01C0h to 024Fh 0250h 0251h 0252h 0253h 0254h 0255h 0256h 0257h 0258h 0259h 025Ah 025Bh 025Ch 025Dh 025Eh 025Fh 0260h to 033Fh 4.
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M16C/30P Group Table 4.3 Address 0340h 0341h 0342h 0343h 0344h 0345h 0346h 0347h 0348h 0349h 034Ah 034Bh 034Ch 034Dh 034Eh 034Fh 0350h 0351h 0352h 0353h 0354h 0355h 0356h 0357h 0358h 0359h 035Ah 035Bh 035Ch 035Dh 035Eh 035Fh 0360h 0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh 4.
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M16C/30P Group Table 4.4 Address 0380h 0381h 0382h 0383h 0384h 0385h 0386h 0387h 0388h 0389h 038Ah 038Bh 038Ch 038Dh 038Eh 038Fh 0390h 0391h 0392h 0393h 0394h 0395h 0396h 0397h 0398h 0399h 039Ah 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h 03A3h 03A4h 03A5h 03A6h 03A7h 03A8h 03A9h 03AAh 03ABh 03ACh 03ADh 03AEh 03AFh 03B0h 03B1h 03B2h 03B3h 03B4h 03B5h 03B6h 03B7h 03B8h 03B9h 03BAh 03BBh 03BCh 03BDh 03BEh 03BFh 4.
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M16C/30P Group Table 4.5 Address 03C0h 03C1h 03C2h 03C3h 03C4h 03C5h 03C6h 03C7h 03C8h 03C9h 03CAh 03CBh 03CCh 03CDh 03CEh 03CFh 03D0h 03D1h 03D2h 03D3h 03D4h 03D5h 03D6h 03D7h 03D8h 03D9h 03DAh 03DBh 03DCh 03DDh 03DEh 03DFh 03E0h 03E1h 03E2h 03E3h 03E4h 03E5h 03E6h 03E7h 03E8h 03E9h 03EAh 03EBh 03ECh 03EDh 03EEh 03EFh 03F0h 03F1h 03F2h 03F3h 03F4h 03F5h 03F6h 03F7h 03F8h 03F9h 03FAh 03FBh 03FCh 03FDh 03FEh 03FFh 4.
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M16C/30P Group 5. 5. Electrical Characteristics Electrical Characteristics Table 5.1 Absolute Maximum Ratings Symbol Condition Rated Value Unit VCC Supply Voltage(VCC1=VCC2) Parameter VCC1=VCC2=AVCC −0.3 to 6.5 V AVCC Analog Supply Voltage VCC1=VCC2=AVCC −0.3 to 6.5 V VI Input Voltage RESET, CNVSS, BYTE, P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 to P3_7, P4_0 to P4_7, P5_0 to P5_7, P6_0 to P6_7, P7_2 to P7_7, P8_0 to P8_7, P9_0 to P9_7, P10_0 to P10_7, VREF, XIN −0.3 to VCC+0.
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M16C/30P Group Table 5.2 5. Electrical Characteristics Recommended Operating Conditions (1) Symbol VCC Supply Voltage (VCC1=VCC2) AVCC Analog Supply Voltage VSS Supply Voltage AVSS Analog Supply Voltage VIH HIGH Input Voltage VIL Standard Parameter LOW Input Voltage Min. 2.7 Typ. Max. 5.0 5.5 Unit V VCC V 0 V 0 V P3_1 to P3_7, P4_0 to P4_7, P5_0 to P5_7 0.8VCC VCC V P0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0 (during single-chip mode) 0.
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M16C/30P Group Table 5.3 5. Electrical Characteristics A/D Conversion Characteristics (1) Symbol Parameter − Resolution INL Integral Non-Linearity Error − Measuring Condition Standard Min. Typ. VREF=VCC Absolute Accuracy 10bit Max. Unit 10 Bits VREF= VCC= 5V AN0 to AN7 input, AN0_0 to AN0_7 input, ANEX0, ANEX1 input ±5 LSB VREF= VCC= 3.3V AN0 to AN7 input, AN0_0 to AN0_7 input, ANEX0, ANEX1 input ±7 LSB 8bit VREF=VCC=5V, 3.
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M16C/30P Group Table 5.4 5. Electrical Characteristics Flash Memory Version Electrical Characteristics (1) Symbol Standard Parameter Min. Typ. Max. Unit − Program and Erase Endurance (2) − Word Program Time (VCC1=5.0V) 25 200 μs − Lock Bit Program Time 25 200 μs − Block Erase Time (VCC1=5.0V) 4-Kbyte block 0.3 4 s 8-Kbyte block 0.3 4 s − 32-Kbyte block 0.5 4 s − 64-Kbyte block 0.
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M16C/30P Group Table 5.6 5. Electrical Characteristics One Time Flash Version Electrical Characteristics (1) Symbol Standard Parameter Min. − Program Endurance − Word Program Time (VCC1=5.0V) tPS One Time Flash Memory Circuit Stabilization Wait Time − Data Hold Time (4) Max. 50 500 μs 15 μs 1 10 NOTES: 1. Referenced to VCC1=4.5 to 5.5V, 3.0 to 3.6V at Topr = 0 to 60 °C (U3, U5) unless otherwise specified. 2. Topr = -40 to 85 °C (U3) / -20 to 85 °C (U5). Table 5.
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M16C/30P Group Table 5.8 5. Electrical Characteristics Power Supply Circuit Timing Characteristics Symbol Parameter Measuring Condition td(P-R) Time for Internal Power Supply Stabilization During Powering-On td(R-S) td(W-S) Typ. VCC=2.7V to 5.5V Max.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Table 5.
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M16C/30P Group Table 5.10 5. Electrical Characteristics Electrical Characteristics (2) (1) Symbol ICC Parameter Power Supply Current In single-chip (VCC1=VCC2=4.0V to 5.5V) mode, the output pins are open and other pins are VSS Measuring Condition Standard Min. Typ. Max. Mask ROM f(XIN)=16MHz No division 10 15 mA One Time Flash f(XIN)=16MHz, No division 10 18 mA Flash Memory f(XIN)=16MHz, No division 12 18 mA One Time Flash f(XIN)=10MHz, VCC1=5.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.11 External Clock Input (XIN input) (1) Symbol Parameter Standard Min. Max. Unit tc External Clock Input Cycle Time 62.5 ns tw(H) External Clock Input HIGH Pulse Width 25 ns tw(L) External Clock Input LOW Pulse Width 25 tr External Clock Rise Time 15 ns tf External Clock Fall Time 15 ns ns NOTES: 1.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.13 Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max. Unit tc(TA) TAiIN Input Cycle Time 100 ns tw(TAH) TAiIN Input HIGH Pulse Width 40 ns tw(TAL) TAiIN Input LOW Pulse Width 40 ns Table 5.14 Timer A Input (Gating Input in Timer Mode) Symbol Parameter Standard Min. Max.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.19 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.25 Memory Expansion and Microprocessor Modes (for setting with no wait) Symbol Standard Parameter Min. Max.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 5V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.26 Memory Expansion and Microprocessor Modes (for 1 wait setting and external area access) Symbol Standard Parameter Min. Max.
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M16C/30P Group 5.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi tsu(D-C) td(C-Q) RXDi tw(INL) INTi input tw(INH) Figure 5.4 Timing Diagram (2) Rev.1.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RDY input tsu(RDY−BCLK) th(BCLK−RDY) (Common to setting with wait and setting without wait) BCLK tsu(HOLD−BCLK) th(BCLK−HOLD) HOLD input HLDA input td(BCLK−HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 td(BCLK−HLDA) Hi−Z (1) NOTES: 1.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (For setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) −3ns.min 25ns.max CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max −3ns.min ADi BHE td(BCLK-ALE) th(BCLK-ALE) -4ns.min 25ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 25ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 × tcyc-45)ns.max Hi-Z DBi tsu(DB-RD) th(RD-DB) 40ns.min 0ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) −3ns.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=5V Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Read timing BCLK td(BCLK-CS) th(BCLK-CS) −3ns.min 25ns.max CSi tcyc td(BCLK-AD) th(BCLK-AD) 25ns.max −3ns.min ADi BHE td(BCLK-ALE) th(RD-AD) 0ns.min th(BCLK-ALE) 25ns.max -4ns.min ALE td(BCLK-RD) th(BCLK-RD) 25ns.max 0ns.min RD tac2(RD-DB) (1.5 × tcyc-45)ns.max Hi-Z DBi th(RD-DB) tsu(DB-RD) 0ns.min 40ns.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Table 5.27 Electrical Characteristics (1) Symbol VOH VOH Parameter HIGH Output Voltage HIGH Output Voltage VOL LOW Output Voltage XOUT LOW Output Voltage XOUT Hysteresis Max. VCC−0.5 VCC IOH=−0.1mA VCC−0.5 VCC LOWPOWER IOH=−50μA VCC−0.5 VCC HIGHPOWER With no load applied 2.5 LOWPOWER With no load applied 1.6 0.5 IOL=0.1mA 0.5 LOWPOWER IOL=50μA 0.
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M16C/30P Group Table 5.28 5. Electrical Characteristics Electrical Characteristics (2) (1) Symbol ICC Parameter Power Supply Current In single-chip (VCC1=VCC2=2.7V to 3.6V) mode, the output pins are open and other pins are VSS Measuring Condition Standard Min. Typ. Max. Mask ROM f(XIN)=10MHz No division 8 11 mA One Time Flash f(XIN)=10MHz, No division 8 13 mA Flash Memory f(XIN)=10MHz, No division 8 13 mA Flash Memory Program f(XIN)=10MHz, VCC1=3.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.29 External Clock Input (XIN input) Symbol Parameter Standard Min. Max.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.31 Timer A Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max. Unit tc(TA) TAiIN Input Cycle Time 150 ns tw(TAH) TAiIN Input HIGH Pulse Width 60 ns tw(TAL) TAiIN Input LOW Pulse Width 60 ns Table 5.32 Timer A Input (Gating Input in Timer Mode) Symbol Parameter Standard Min. Max.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Timing Requirements (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.37 Timer B Input (Counter Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.43 Memory Expansion and Microprocessor Modes (for setting with no wait) Symbol Standard Parameter Min. Max.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Switching Characteristics (VCC1 = VCC2 = 3V, VSS = 0V, at Topr = −20 to 85°C / −40 to 85°C unless otherwise specified) Table 5.44 Memory Expansion and Microprocessor Modes (for 1 wait setting and external area access) Symbol Standard Parameter Min. Unit Max.
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M16C/30P Group 5.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V tc(CK) tw(CKH) CLKi tw(CKL) th(C-Q) TXDi tsu(D-C) td(C-Q) RXDi tw(INL) INTi input tw(INH) Figure 5.10 Timing Diagram (2) Rev.1.
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M16C/30P Group 5. Electrical Characteristics Memory Expansion Mode, Microprocessor Mode VCC1=VCC2=3V (Effective for setting with wait) BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RDY input tsu(RDY−BCLK) th(BCLK−RDY) (Common to setting with wait and setting without wait) BCLK th(BCLK−HOLD) tsu(HOLD−BCLK) HOLD input HLDA output td(BCLK−HLDA) P0, P1, P2, P3, P4, P5_0 to P5_2 (1) td(BCLK−HLDA) Hi−Z NOTES: 1.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Memory Expansion Mode, Microprocessor Mode (for setting with no wait) Read timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.max 0ns.min CSi tcyc td(BCLK-AD) th(BCLK-AD) 30ns.max ADi BHE 0ns.min td(BCLK-ALE) th(BCLK-ALE) -4ns.min 30ns.max th(RD-AD) 0ns.min ALE td(BCLK-RD) 30ns.max th(BCLK-RD) 0ns.min RD tac1(RD-DB) (0.5 × tcyc-60)ns.max Hi-Z DBi tsu(DB-RD) 50ns.min th(RD-DB) 0ns.min Write timing BCLK td(BCLK-CS) th(BCLK-CS) 30ns.
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M16C/30P Group 5. Electrical Characteristics VCC1=VCC2=3V Memory Expansion Mode, Microprocessor Mode (for 1-wait setting and external area access) Read timing BCLK td(BCLK−CS) th(BCLK−CS) 30ns.max 0ns.min CSi tcyc td(BCLK−AD) th(BCLK−AD) 30ns.max 0ns.min ADi BHE td(BCLK−ALE) th(RD−AD) th(BCLK−ALE) 0ns.min −4ns.min 30ns.max ALE td(BCLK−RD) th(BCLK−RD) 30ns.max 0ns.min RD tac2(RD−DB) (1.5 × tcyc−60)ns.max Hi−Z DBi th(RD−DB) tsu(DB−RD) 0ns.min 50ns.
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M16C/30P Group Appendix 1. Package Dimensions Appendix 1. Package Dimensions Diagrams showing the latest package dimensions and mounting information are available in the "Packages" section of the Renesas Technology website. JEITA Package Code RENESAS Code Previous Code MASS[Typ.] P-QFP100-14x20-0.65 PRQP0100JB-A 100P6S-A 1.6g HD *1 D 80 51 81 50 HE *2 E NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
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REVISION HISTORY M16C/30P Group Datasheet Description Rev. Date 0.70 Aug 26, 2004 − First Edition issued 0.80 Mar 18, 2005 − development support tools -> development tools − BCLK -> CPU clock 2 Table 1.1 Performance Outline of M16C/30P Group Serial interface is revised. 4 Figure 1.2 Type., Memory Size, and Package is partly revised. 8 Table 1.4 Pin Detection (2) is partly revised. 20 Note 2 Table 5.3 A/D Conversion Characteristics is partly revised. 21 Symbol of Table 5.
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REVISION HISTORY Rev. 1.10 Date Oct 01, 2005 M16C/30P Group Datasheet Description Page Summary 44 Figure 5.12 Timing Diagram (4) is added. 45 Figure 5.13 Timing Diagram (5) is added. 2 Table 1.1 Performance Outline of M16C/30P Group is partly revised. 4 Table 1.2 Product List is partly revised. Figure 1.2 Type No., Memory Size, and Package is partly revised. 5 Table 1.3 Product Code of Mask ROM version Version for M16C/30P is added. Figure 1.
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REVISION HISTORY Rev. Date 1.20 Oct 17, 2006 M16C/30P Group Datasheet Description Page Summary 1 Note is partly deleted. 2 Table 1.1 Performance Outline of M16C/30P Group is partly added. 4 Table 1.2 Product List is partly revised. 5 Figure 1.2 Type No., Memory Size, and Package is added. 7 Table 1.4 Product Code of One Time Flash version, Flash Memory version, and ROM-less version for M16C/30P is partly added. Figure 3.1 Memory Map is partly added. 17 19 Table 4.
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Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use.