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M32C/80 Group SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER REJ03B0038-0110 Rev.1.10 Nov. 01, 2005 1. Overview The M32C/80 Group microcomputer is a single-chip control unit that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/80 Group is available in 100-pin plastic molded LQFP/QFP package.
1. Overview M32C/80 Group 1.2 Performance Overview Table 1.1 lists performance overview of the M32C/80 Group. Table 1.
1. Overview M32C/80 Group 1.3 Block Diagram Figure 1.1 shows a block diagram of the M32C/80 Group microcomputer.
1. Overview M32C/80 Group 1.4 Product Information Table 1.2 lists the product information. Figure 1.2 shows the product numbering system. Table 1.
1. P70 and P71 are ports for the N-channel open drain output. Figure 1.3 Pin Assignment Rev. 1.10 Nov.
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1. Overview M32C/80 Group Table 1.
1. Overview M32C/80 Group Table 1.
1. Overview M32C/80 Group 1.6 Pin Description Table 1.4 Pin Description Signal name Power supply Analog power supply input Reset input Pin name I/O type VCC1, VCC2 VSS AVCC AVSS ____________ RESET I Supply voltage Description - Apply 3.0 to 5.5 V to both VCC1 and VCC2 pins. Apply 0 V to the I VCC1 VSS pin. VCC1 ≥ VCC2(1) Supplies power for the A/D converter.
1. Overview M32C/80 Group Table 1.4 Pin Description (Continued) Signal name Main clock input XIN XOUT Main clock output I Supply voltage VCC1 O VCC1 Pin name I/O type Description I/O pins for the main clock generation circuit. Connect a ceramic resonator or crystal oscillator between XIN and XOUT. To apply external clock, input the clock from XIN and leave XOUT open I/O pins for a sub clock oscillation circuit.
1. Overview M32C/80 Group Table 1.
2. Central Processing Unit (CPU) M32C/80 Group 2. Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The register bank is comprised of 8 registers (R0, R1, R2, R3, A0, A1, SB and FB) out of 28 CPU registers. Two sets of register banks are provided.
2. Central Processing Unit (CPU) M32C/80 Group 2.1 General Registers 2.1.1 Data Registers (R0, R1, R2 and R3) R0, R1, R2 and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R0 can be combined with R2 to be used as a 32-bit data register (R2R0). The same applies to R1 and R3. 2.1.
2. Central Processing Unit (CPU) M32C/80 Group 2.1.8.5 Register Bank Select Flag (B) The register bank 0 is selected when the B flag is set to "0". The register bank 1 is selected when this flag is set to "1". 2.1.8.6 Overflow Flag (O) The O flag is set to "1" when the result of an arithmetic operation overflows; otherwise "0". 2.1.8.7 Interrupt Enable Flag (I) The I flag enables a maskable interrupt. Interrupt is disabled when the I flag is set to "0" and enabled when the I flag is set to "1".
3. Memory M32C/80 Group 3. Memory Figure 3.1 shows a memory map of the M32C/80 Group. The M32C/80 Group provides 16-Mbyte address space addressed from 00000016 to FFFFFF16. The fixed interrupt vectors are allocated from address FFFFDC16 to FFFFFF16. It stores the starting address of each interrupt routine. The internal RAM is allocated from address 00040016 to higher. For example, a 8-Kbyte internal RAM is allocated from address 00040016 to 0023FF16.
4. Special Function Registers (SFRs) M32C/80 Group 4.
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5. Electrical Characteristics M32C/80 Group 5. Electrical Characteristics Table 5.1 Absolute Maximum Ratings Condition Value Unit VCC1, VCC2 Symbol Supply Voltage Parameter VCC1=AVCC -0.3 to 6.0 V VCC2 Supply Voltage - -0.3 to VCC1 V AVCC Analog Supply Voltage VI Input Voltage VCC1=AVCC RESET, CNVSS, BYTE, P60-P67, P72-P77, -0.3 to 6.0 V -0.3 to VCC1+0.3 V P80-P87, P90-P97, P100-P107, VREF, XIN P00-P07, P10-P17, P20-P27, P30-P37, -0.3 to VCC2+0.
5. Electrical Characteristics M32C/80 Group Table 5.2 Recommended Operating Conditions (VCC1= VCC2=3.0V to 5.5V at Topr=– 20 to 85oC unless otherwise specified) Symbol Parameter VCC1, VCC2 AV C C Supply Voltage (VCC1≥ VCC2) Analog Supply Voltage V SS Supply Voltage AV S S Analog Supply Voltage Input High ("H") Voltage IOH(peak) IOH(avg) IOL(peak) IOL(avg) Input Low ("L") Voltage Typ. 5.0 VCC1 Max. 5.
5. Electrical Characteristics M32C/80 Group Table 5.2 Recommended Operating Conditions (Continued) (VCC1=VCC2=3.0V to 5.5V at Topr=–20 to 85oC unless otherwise specified) Symbol f(BCLK) f(XIN) f(XCIN) CPU Operation Frequency Main Clock Input Frequency Min. On-chip Oscillator Frequency (Topr=25° C) f(PLL) PLL Clock Frequency Wait Time to Stabilize PLL Frequency Synthesizer Rev. 1.10 Nov. 01, 2005 Page 32 REJ03B0038-0110 of 56 Typ. Max. Unit VCC1=4.2 to 5.5 V 0 32 MHz VCC1=3.0 to 5.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=5V Table 5.3 Electrical Characteristics (VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr= –20 to 85oC, f(BCLK)=32MHZ unless otherwise specified) Symbol VOH Parameter Output High ("H") Voltage Condition P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOH=-5mA VCC2-2.0 Max. VCC2 P50-P57 P60-P67, P72-P77, P80-P84, P86, P87, P90- VCC1-2.0 VCC1 VCC2-0.3 VCC2 VCC1-0.3 VCC1 3.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=5V Table 5.4 A/D Conversion Characteristics (VCC1=VCC2=AVCC=VREF=4.2 to 5.5V, Vss= AVSS = 0V at Topr=–20 to 85oC, f(BCLK) = 32MHZ unless otherwise specified) Symbol Parameter Standard Measurement Condition Min. - INL Resolution VREF=VCC1 Integral Nonlinearity Error DNL Unit Typ. Max.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=5V Timing Requirements (VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr=–20 to 85oC unless otherwise specified) Table 5.6 External Clock Input Symbol Parameter Standard Min. Unit Max. tc External Clock Input Cycle Time 31.25 ns tw(H) External Clock Input High ("H") Width 13.75 ns 13.75 tw(L) External Clock Input Low ("L") Width tr External Clock Rise Time 5 ns ns tf External Clock Fall Time 5 ns Table 5.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=5V Timing Requirements (VCC1=VCC2=4.2 to 5.5V, VSS=0V at Topr=–20 to 85oC unless otherwise specified) Table 5.8 Timer A Input (Count Source Input in Event Counter Mode) Symbol Standard Parameter Min. Unit Max. tc(TA) TAiIN Input Cycle Time 100 ns tw(TAH) TAiIN Input High ("H") Width 40 ns tw(TAL) TAiIN Input Low ("L") Width 40 ns Table 5.9 Timer A Input (Gate Input in Timer Mode) Standard Symbol Parameter Min. Max.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=5V Timing Requirements (VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.13 Timer B Input (Count Source Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=5V Switching Characteristics (VCC1 = VCC2 = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.19 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space) Symbol Parameter td(BCLK-AD) Address Output Delay Time th(BCLK-AD) Address Output Hold Time (BCLK standard) Measurement Condition Standard Min. Unit Max.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=5V Switching Characteristics (VCC = 4.2 to 5.5V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=5V P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Figure 5.1 P0 to P10 Measurement Circuit Rev. 1.10 Nov.
5. Electrical Characteristics M32C/80 Group Vcc1=Vcc2=5V Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) [ Read Timing ] (1φ +1φ Bus Cycle) BCLK td(BCLK-CS) th(BCLK-CS) 18ns.max(1) -3ns.min CSi th(RD-CS) tcyc 0ns.min td(BCLK-AD) th(BCLK-AD) 18ns.max(1) -3ns.min ADi BHE th(RD-AD) 0ns.min td(BCLK-RD) 18ns.max RD th(BCLK-RD) tac1(RD-DB)(2) -5ns.min tac1(AD-DB)(2) DB Hi-Z tsu(DB-BCLK) th(RD-DB) 26ns.min(1) 0ns.min NOTES: 1.
5. Electrical Characteristics M32C/80 Group Vcc1=Vcc2=5V Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus) [ Read Timing ] (2φ +2φ Bus Cycle) BCLK td(BCLK-ALE) th(BCLK-ALE) -5ns.min 18ns.max ALE th(BCLK-CS) tcyc td(BCLK-CS) -3ns.min 18ns.max th(RD-CS)(1) CSi td(AD-ALE)(1) th(ALE-AD) ADi /DBi Address (1) tsu(DB-BCLK) 26ns.min Data input tdz(RD-AD) Address 8ns.max td(BCLK-AD) ADi BHE th(RD-DB) tac2(RD-DB)(1) 18ns.
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5. Electrical Characteristics M32C/80 Group Vcc1=Vcc2=5V Memory Expansion Mode and Microprocessor Mode BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input th(BCLK–RDY) tsu(RDY–BCLK) BCLK tsu(HOLD–BCLK) th(BCLK–HOLD) HOLD Input HLDA Output td(BCLK–HLDA) P0, P1, P2, P3, P4, P50 to P52 td(BCLK–HLDA) Hi–Z Measurement Conditions • VCC1=VCC2=4.2 to 5.5V • Input high and low voltage: VIH=4.0V, VIL=1.0V • Output high and low voltage: VOH=2.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=3.3V Table 5.21 Electrical Characteristics (VCC1=VCC2=3.0 to 3.6V, VSS=0V at Topr = –20 to 85oC, f(BCLK)=24MHZ unless otherwise specified) Symbol VOH Parameter Output High ("H") Voltage Condition P00-P07, P10-P17, P20-P27, P30-P37, P40-P47, IOH=-1mA P50-P57 P60-P67, P72-P77, P80-P84, P86, P87, P90P97, P100-P107 XOUT XCOUT IOH=-0.1mA High Power Low Power VOL Output Low ("L") Voltage VT+-VT- Hysteresis Standard Unit Min. Typ. VCC2-0.6 Max.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=3.3V Table 5.22 A/D Conversion Characteristics (VCC1=VCC2=AVCC=VREF= 3.0 to 3.6V, VSS=AVSS=0V at Topr = –20 to 85oC, f(BCLK) = 24MHZ unless otherwise specified) Symbol Parameter Standard Measurement Condition Unit Min. Typ. Max. - Resolution INL DNL Integral Nonlinearity Error No S&H (8-bit) VREF=VCC1 10 Bits VCC1=VCC2=VREF=3.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=3.3V Timing Requirements (VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.24 External Clock Input Symbol Parameter Standard Min. Unit Max. tc External Clock Input Cycle Time 41 ns tw(H) External Clock Input High ("H") Width 18 ns 18 tw(L) External Clock Input Low ("L") Width tr External Clock Rise Time 5 ns tf External Clock Fall Time 5 ns ns Table 5.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=3.3V Timing Requirements (VCC1=VCC2= 3.0 to 3.6V, VSS= 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.26 Timer A Input (Count Source Input in Event Counter Mode) Symbol Standard Parameter Min. Unit Max. tc(TA) TAiIN Input Cycle Time 100 ns tw(TAH) TAiIN Input High ("H") Width 40 ns tw(TAL) TAiIN Input Low ("L") Width 40 ns Table 5.27 Timer A Input (Gate Input in Timer Mode) Standard Symbol Parameter Min. Max.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=3.3V Timing Requirements (VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.31 Timer B Input (Count Source Input in Event Counter Mode) Symbol Parameter Standard Min. Max.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=3.3V Switching Characteristics (VCC1=VCC2=3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.37 Memory Expansion Mode and Microprocessor Mode (when accessing external memory space) Symbol Parameter Measurement Condition Standard Min. Unit Max.
5. Electrical Characteristics M32C/80 Group VCC1=VCC2=3.3V Switching Characteristics (VCC1 = VCC2 = 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85oC unless otherwise specified) Table 5.38 Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space with the multiplexed bus) Symbol Parameter Measurement Condition Standard Min. Unit Max.
5. Electrical Characteristics M32C/80 Group Vcc1=Vcc2=3.3V Memory Expansion Mode and Microprocessor Mode (when accessing an external memory space) [Read Timing] (1φ + 1φ Bus Cycles) BCLK td(BCLK-CS) th(BCLK-CS) 0ns.min 18ns.max(1) CSi th(RD-CS) tcyc 0ns.min td(BCLK-AD) th(BCLK-AD) 18ns.max(1) ADi BHE 0ns.min td(BCLK-RD) 18ns.max th(RD-AD) 0ns.min RD th(BCLK-RD) tac1(RD-DB)(2) -3ns.min tac1(AD-DB)(2) DB Hi-Z tsu(DB-BCLK) th(RD-DB) 30ns.min(1) 0ns.min NOTES: 1.
M32C/80 Group 5. Electrical Characteristics Vcc1=Vcc2=3.3V Memory Expansion Mode and Microprocessor Mode (when accessing external memory space and using the multiplexed bus) [ Read Timing ] (2φ +2φ Bus Cycles) BCLK td(BCLK-ALE) th(BCLK-ALE) 18ns.max -2ns.min ALE th(BCLK-CS) tcyc td(BCLK-CS) 0ns.min 18ns.max th(RD-CS)(1) CSi td(AD-ALE)(1) th(ALE-AD) ADi /DBi (1) Address tsu(DB-BCLK) 30ns.min Data input tdz(RD-AD) Address 8ns.max td(BCLK-AD) ADi BHE th(RD-DB) tac2(RD-DB)(1) 18ns.
5. Electrical Characteristics M32C/80 Group Vcc1=Vcc2=3.
M32C/80 Group 5. Electrical Characteristics Vcc1=Vcc2=3.3V Memory Expansion Mode and Microprocessor Mode BCLK RD (Separate bus) WR, WRL, WRH (Separate bus) RD (Multiplexed bus) WR, WRL, WRH (Multiplexed bus) RDY input tsu(RDY–BCLK) BCLK tsu(HOLD–BCLK) th(BCLK–HOLD) HOLD input HLDA output td(BCLK–HLDA) td(BCLK–HLDA) P0, P1, P2, P3, P4, P50 to P52 Hi–Z Measurement Conditions: • VCC1=VCC2=3.0 to 3.6V • Input high and low voltage: VIH=2.4V, VIL=0.6V • Output high and low voltage: VOH=1.5V, VOL=1.
Package Dimensions M32C/80 Group Package Dimensions JEITA Package Code P-LQFP100-14x14-0.50 RENESAS Code PLQP0100KB-A Previous Code 100P6Q-A / FP-100U / FP-100UV MASS[Typ.] 0.6g HD *1 D 51 75 NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
M32C/80 Group Datasheet REVISION HISTORY Rev. Date Description Summary Page 0.10 Sep., 02 – New Document 0.11 Sep., 02 3 Table 1.1.1 “CAN” deleted 0.12 Nov., 02 3 Table 1.1.1 “4.2 to 5.5V” --> “3.0 to 5.5V” "3.0 to 3.6V (f(XIN)=20MHz without software wait)" deleted "26mA (f(XIN)=20MHz without software wait,Vcc=3.3V)" deleted 0.30 Aug., 02 – 1. Overview 1.2 Performance Outline 1.3 Block Diagram 1.5 Pin Assignments Table 1.3 Pin Characteristics for 100-Pin Package 1.6 Pin Description 2.
M32C/80 Group Datasheet REVISION HISTORY Rev. Date Description Summary Page 1.10 Nov., 05 30All pages 1 2 3 9 Electrical Characteristics • This capter added Package code chnaged: 100P6Q-A to PLQP0100KB-A and 100P6S-A to PRQP0100JB-A Overview • Note that the M32C/80 Group is ROMless device added • Table 1.1 M32C/80 Group Performance Item "HDLC Data Processing" changed to "Intelligent I/O Communication Function"; item "Flash Memory" deleted • Figure 1.
M32C/80 Group Datasheet REVISION HISTORY Rev. Date Description Summary Page 53 • Figure 5.7 VCC1=VCC2=3.
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