Datasheet

Page 47
65fo5002,10.voN01.1.veR
0110-8300B30JER
5. Electrical Characteristics
VCC1=VCC2=3.3V
puorG08/C23M
Timing Requirements
(VCC1=VCC2= 3.0 to 3.6V, VSS = 0V at Topr = –20 to 85
o
C unless otherwise specified)
Table 5.24 External Clock Input
Table 5.25 Memory Expansion Mode and Microprocessor Mode
lobmySretemaraP
dradnatS
tinU
.niM.xaM
ctemiTelcyCtupnIkcolClanretxE 14sn
wt
)H( htdiW)"H"(hgiHtupnIkcolClanretxE 81sn
wt
)L( htdiW)"L"(woLtupnIkcolClanretxE 81sn
rtemiTesiRkcolClanretxE 5sn
ftemiTllaFkcolClanretxE 5sn
lobmySretemaraP
dradnatS
tinU
.niM.xaM
1cat
)BD-DR( )dradnatsDR(emiTsseccAtupnIataD )1etoN(sn
1cat
)BD-DA( )dradnatsSC,dradnatsDA(emiTsseccAtupnIataD )1etoN(sn
2cat
)BD-DR( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDR(emiTsseccAtupnIataD )1etoN(sn
2cat
)BD-DA( )subdexelpitlumehthtiwecapsagnisseccanehw,dradnatsDA(emiTsseccAtupnIataD )1etoN(sn
ust
)KLCB-BD( emiTputeStupnIataD 03sn
ust
)KLCB-YDR( emiTputeStupnIYDR 04sn
ust
)KLCB-DLOH( emiTputeStupnIDLOH 06sn
ht
)BD-DR( emiTdloHtupnIataD 0sn
ht
)YDR-KLCB( emiTdloHtupnIYDR 0sn
ht
)DLOH-KLCB( emiTdloHtupnIDLOH 0sn
dt
)ADLH-KLCB( emiTyaleDtuptuOADLH 52sn
:ETON
atresnI.selcycsublanretxednaycnceuqerfKLCBotgnidrocca,snoitauqegniwollofehtmorfdeniatboebnacseulaV.1
(f,ycneuqerfnoitarepoehtrewolroetatstiaw
KLCB .evitagensieulavdetaluclacehtfi,)
tac1(RD – DB) =
f
(BCLK) X 2
– 35
10 X m
9
[ns] (if external bus cycle is aφ + bφ, m=(bx2)+1)
t
ac2(AD – DB) =
f
(BCLK) X 2
– 35
10 X p
9
[ns] (if external bus cycle is aφ + bφ, p={(a+b-1)x2}+1)
– 35
10 X n
9
[ns] (if external bus cycle is aφ + bφ, n=a+b)
f
(BCLK)
t
ac1(AD – DB) =
t
ac2(RD – DB) =
f
(BCLK) X 2
– 35
10 X m
9
[ns] (if external bus cycle is aφ + bφ, m=(bx2)-1)