REJ09B0163-0100Z 16 H8S/2111B Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family / H8S/2100 Series H8S/2111B Rev.1.00 Revision Date: May.
Rev. 1.
Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage.
General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins.
Configuration of This Manual This manual comprises the following items: 1. 2. 3. 4. 5. 6. General Precautions on Handling of Product Configuration of This Manual Preface Contents Overview Description of Functional Modules • CPU and System-Control Modules • On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module.
Preface The H8S/2111B is a microcomputer (MCU) made up of the H8S/2000 CPU employing Renesas Technology's original architecture as its core, and the peripheral functions required to configure a system. The H8S/2000 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a simple and optimized instruction set for high-speed operation. The H8S/2000 CPU can handle a 16-Mbyte linear address space.
Rules: Register name: Bit order: Number notation: Signal notation: Related Manuals: The following notation is used for cases when the same or a similar function, e.g. serial communication interface, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB is on the left and the LSB is on the right. Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
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Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 Features............................................................................................................................. 1 Internal Block Diagram..................................................................................................... 2 Pin Description.....................................................................................................
2.8 2.9 Processing States............................................................................................................... 46 Usage Notes ...................................................................................................................... 48 2.9.1 Note on TAS Instruction Usage........................................................................... 48 2.9.2 Note on STM/LDM Instruction Usage ................................................................ 48 2.9.
5.5 5.6 5.7 5.8 5.4.1 External Interrupts ............................................................................................... 76 5.4.2 Internal Interrupts ................................................................................................ 77 Interrupt Exception Handling Vector Table...................................................................... 78 Interrupt Control Modes and Interrupt Operation ............................................................. 80 5.6.
7.4 Port 4................................................................................................................................. 107 7.4.1 Port 4 Data Direction Register (P4DDR)............................................................. 107 7.4.2 Port 4 Data Register (P4DR) ............................................................................... 107 7.4.3 Pin Functions ....................................................................................................... 108 7.5 Port 5.
7.12.5 Pin Functions ....................................................................................................... 135 7.12.6 Input Pull-Up MOS in Ports C and D .................................................................. 135 7.13 Ports E, F........................................................................................................................... 136 7.13.1 Port E and Port F Data Direction Registers (PEDDR, PFDDR) .......................... 136 7.13.
9.4 9.5 9.6 9.7 9.3.7 Timer Control/Status Register (TCSR)................................................................ 163 9.3.8 Timer Control Register (TCR)............................................................................. 166 9.3.9 Timer Output Compare Control Register (TOCR) .............................................. 167 Operation .......................................................................................................................... 169 9.4.1 Pulse Output .........
10.6 10.7 10.8 10.9 10.10 10.5.1 TCNT Count Timing ........................................................................................... 207 10.5.2 Timing of CMFA and CMFB Setting at Compare-Match ................................... 207 10.5.3 Timing of Timer Output at Compare-Match........................................................ 208 10.5.4 Timing of Counter Clear at Compare-Match ....................................................... 208 10.5.5 TCNT External Reset Timing.................
11.6.5 System Reset by RESO Signal ............................................................................ 233 11.6.6 Counter Values during Transitions between High-Speed, Sub-Active, and Watch Modes ................................................................................................ 233 Section 12 Serial Communication Interface (SCI)............................................ 235 12.1 Features................................................................................................
12.8.6 SCI Operations during Mode Transitions ............................................................ 273 12.8.7 Switching from SCK Pins to Port Pins ................................................................ 276 Section 13 I2C Bus Interface (IIC) .....................................................................277 13.1 Features............................................................................................................................. 277 13.2 Input/Output Pins .............
14.4.6 KBF Setting Timing and KCLK Control............................................................. 362 14.4.7 Receive Timing.................................................................................................... 363 14.4.8 KCLK Fall Interrupt Operation ........................................................................... 364 14.5 Usage Notes ...................................................................................................................... 365 14.5.
16.4.2 Scan Mode ........................................................................................................... 419 16.4.3 Input Sampling and A/D Conversion Time ......................................................... 421 16.4.4 External Trigger Input Timing............................................................................. 422 16.5 Interrupt Sources............................................................................................................... 423 16.
19.2 19.3 19.4 19.5 19.6 19.7 19.8 Duty Correction Circuit .................................................................................................... 459 Medium-Speed Clock Divider .......................................................................................... 459 Bus Master Clock Select Circuit....................................................................................... 459 Subclock Input Circuit ...............................................................................
22.5 Flash Memory Characteristics .......................................................................................... 527 22.6 Usage Note........................................................................................................................ 529 22.7 Timing Chart..................................................................................................................... 529 22.7.1 Clock Timing ....................................................................................
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Figures Section 1 Overview Figure 1.1 Internal Block Diagram ................................................................................................. 2 Figure 1.2 Pin Arrangement............................................................................................................ 3 Section 2 CPU Figure 2.1 Exception Vector Table (Normal Mode)..................................................................... 17 Figure 2.2 Stack Structure in Normal Mode ......................................
Section 8 Figure 8.1 Figure 8.2 Figure 8.3 Figure 8.4 8-Bit PWM Timer (PWM) Block Diagram of PWM Timer................................................................................. 147 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = B'1000) ..... 154 Example of PWM Setting.......................................................................................... 155 Example when PWM is Used as D/A Converter.......................................................
Figure 10.13 Timing of Input Capture Signal (Input capture signal is input during TICRR and TICRF read) ............................. 213 Figure 10.14 Conflict between TCNT Write and Clear.............................................................. 216 Figure 10.15 Conflict between TCNT Write and Count-Up....................................................... 216 Figure 10.16 Conflict between TCOR Write and Compare-Match ............................................ 217 Section 11 Figure 11.1 Figure 11.
Figure 12.20 Figure 12.21 Figure 12.22 Figure 12.23 Sample Flowchart of Simultaneous Serial Transmission and Reception .............. 270 Sample Flowchart for Mode Transition during Transmission............................... 274 Pin States during Transmission in Asynchronous Mode (Internal Clock) ............ 274 Pin States during Transmission in Clocked Synchronous Mode (Internal Clock)..................................................................................................... 275 Figure 12.
Figure 13.25 Figure 13.26 Figure 13.27 Figure 13.28 Figure 13.29 Figure 13.30 Figure 13.31 Figure 13.32 Figure 13.33 Figure 13.34 Figure 13.35 IRIC Setting Timing and SCL Control (1) ............................................................ 331 IRIC Setting Timing and SCL Control (2) ............................................................ 332 IRIC Setting Timing and SCL Control (3) ............................................................ 333 Block Diagram of Noise Canceler......................
Section 16 A/D Converter Figure 16.1 Block Diagram of A/D Converter ........................................................................... 414 Figure 16.2 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected)....................................................... 420 Figure 16.3 A/D Conversion Timing.......................................................................................... 421 Figure 16.4 External Trigger Input Timing ..............................................
Figure 22.4 Connection of VCL Capacitor................................................................................. 529 Figure 22.5 System Clock Timing .............................................................................................. 529 Figure 22.6 Oscillation Settling Timing ..................................................................................... 530 Figure 22.7 Oscillation Setting Timing (Exiting Software Standby Mode)................................ 530 Figure 22.
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Tables Section 1 Overview Table 1.1 Pin Functions in Each Operating Mode .................................................................... 4 Table 1.2 Pin Functions ............................................................................................................ 9 Section 2 CPU Table 2.1 Instruction Classification ........................................................................................ 29 Table 2.2 Operation Notation .............................................................
Table 7.4 Table 7.5 Table 7.6 Table 7.7 Table 7.8 Table 7.9 Input Pull-Up MOS States (Port 3)....................................................................... 106 Input Pull-Up MOS States (Port 6)....................................................................... 116 Input Pull-Up MOS States (Port A) ...................................................................... 128 Input Pull-Up MOS States (Port B) ......................................................................
Table 12.7 Table 12.8 Table 12.9 Table 12.10 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) .... 248 Serial Transfer Formats (Asynchronous Mode).................................................... 250 SSR Status Flags and Receive Data Handling ...................................................... 257 SCI Interrupt Sources........................................................................................ 271 Section 13 I2C Bus Interface (IIC) Table 13.1 Pin Configuration.......
Section 19 Clock Pulse Generator Table 19.1 Damping Resistance Values ................................................................................. 456 Table 19.2 Crystal Resonator Parameters ............................................................................... 456 Table 19.3 External Clock Input Conditions .......................................................................... 458 Table 19.4 External Clock Output Stabilization Delay Time .................................................
Section 1 Overview 1.
Internal Block Diagram Port A Port 2 Port 1 P17/PW7 P16/PW6 P15/PW5 P14/PW4 P13/PW3 P12/PW2 P11/PW1 P10/PW0 Port 3 P37/SERIRQ P36/LCLK P35/LRESET P34/LFRAME P33/LAD3 P32/LAD2 P31/LAD1 P30/LAD0 Port B Bus controller P27 P26 P25 P24 P23 P22 P21 P20 PB7/WUE7 PB6/WUE6 PB5/WUE5 PB4/WUE4 PB3/WUE3 PB2/WUE2 PB1/WUE1/LSCI PB0/WUE0/LSMI Port C Port 9 PA7/KIN15/PS2CD PA6/KIN14/PS2CC PA5/KIN13/PS2BD PA4/KIN12/PS2BC PA3/KIN11/PS2AD PA2/KIN10/PS2AC PA1/KIN9 PA0/KIN8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 Port D P4
1.3.1 Pin Arrangement 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 P66/FTOB/KIN6/IRQ6 P65/FTID/KIN5 P64/FTIC/KIN4 P63/FTIB/KIN3 P62/FTIA/KIN2/TMIY P61/FTOA/KIN1 P60/FTCI/KIN0/TMIX AVref AVCC P77 P76 P75/AN5 Pin Description P13/PW3 P14/PW4 P15/PW5 P16/PW6 P17/PW7 P20 P21 P22 P23 P24 P25 P26 P27 VSS PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 VCC P67/TMOX/KIN7/IRQ7 1.
1.3.2 Table 1.1 Pin Functions in Each Operating Mode Pin Functions in Each Operating Mode Pin Name Pin No.
Pin Name Pin No.
Pin Name Pin No.
Pin Name Pin No.
Pin Name Pin No.
1.3.3 Table 1.2 Pin Functions Pin Functions Pin No. Type Symbol TFP-144 I/O Name and Function Power VCC 1, 86 Input VCL VCCB 13 36 Input Input VSS Input XTAL EXTAL 7, 42, 95, 111, 139 143 144 φ 18 Output Power supply pin. Connect the pin to the system power supply. Power supply pin. Connect the pin to VCC. The power supply for the port A input/output buffer. Ground pin. Connect to the system power supply (0 V). Pins for connection to crystal resonators.
Pin No. Type Symbol TFP-144 I/O Name and Function 78 79 84 80 81 82 Input Output Output Input Input Input The counter clock input pin. The output compare A output pin. The output compare B output pin. The input capture A input pin. The input capture B input pin. The input capture C input pin. FTID TMO0 TMO1 TMOX TMOY* TMOA TMOB ExTMOX* TMCI0 TMCI1 TMRI0 TMRI1 83 137 3 85 43 48 47 44 136 2 138 4 Input Output The input capture D input pin. The waveform output pins for the output compare function.
Pin No. Type Symbol Host interface LAD3 to (LPC) LAD0 LFRAME LRESET LCLK SERIRQ TFP-144 I/O Name and Function 124 to 121 Input/ Output Input LPC command, address, and data input/output pins. Input pin that indicates the start of an LPC cycle or forced termination of an abnormal LPC cycle. Input pin that indicates an LPC reset. The LPC clock input pin. Input/output pin for LPC serialized host interrupts (HIRQ1, SMI, HIRQ6, HIRQ9 to HIRQ12).
Pin No. Type Symbol TFP-144 I/O Name and Function 14 135 53 51 Input/ Output I2C clock I/O pins. The output type is NMOS open-drain output. SDA0 SDA1 ExSDAA* ExSDAB* P17 to P10 17 138 54 52 104 to 110, 112 Input/ Output I2C data I/O pins. The output type is NMOS open-drain output. Input/ Output Eight input/output pins. P27 to P20 96 to 103 Eight input/output pins.
Section 2 CPU The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control. This section describes the H8S/2000 CPU. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes. 2.
• Two CPU operating modes Normal mode Advanced mode • Power-down state Transition to power-down state by SLEEP instruction Selectable CPU clock speed 2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. • Register configuration The MAC register is supported only by the H8S/2600 CPU. • Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU.
2.1.2 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers Eight 16-bit extended registers and one 8-bit control register have been added. • Expanded address space Normal mode supports the same 64-Kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space.
2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-Kbyte address space. Advanced mode supports a maximum 16-Mbyte address space. The mode is selected by the LSI's mode pins. 2.2.1 Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU in normal mode. • Address space Linear access to a maximum address space of 64 Kbytes is possible.
H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Reset exception vector (Reserved for system use) (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2.1 Exception Vector Table (Normal Mode) SP PC (16 bits) (a) Subroutine Branch SP CCR CCR* PC (16 bits) (b) Exception Handling Note: * Ignored when returning. Figure 2.2 Stack Structure in Normal Mode Rev. 1.
2.2.2 Advanced Mode • Address space Linear access to a maximum address space of 16 Mbytes is possible. • Extended registers (En) The extended registers (E0 to E7) can be used as 16-bit registers. They can also be used as the upper 16-bit segments of 32-bit registers or address registers. • Instruction set All instructions and addressing modes can be used.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode, the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF.
2.3 Address Space Figure 2.5 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-Kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. The usable modes and address spaces differ depending on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.4 Register Configuration The H8S/2000 CPU has the internal registers shown in figure 2.6. There are two types of registers: general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit extended control register (EXR), and an 8-bit condition code register (CCR).
2.4.1 General Registers The H8S/2000 CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Free area SP (ER7) Stack area Figure 2.8 Stack 2.4.2 Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched for read, the least significant PC bit is regarded as 0.) 2.4.3 Extended Control Register (EXR) EXR does not affect operation in this LSI.
2.4.4 Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions.
Bit Initial Bit Name Value 0 C 2.4.5 R/W Undefined R/W Description Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by Add instructions, to indicate a carry Subtract instructions, to indicate a borrow Shift and rotate instructions, to indicate a carry The carry flag is also used as a bit accumulator by bit manipulation instructions.
2.5 Data Formats The H8S/2000 CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, …, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2.9 shows the data formats of general registers.
Data Type Register Number Word data Rn Data Image 15 0 MSB Word data 15 0 MSB Longword data LSB En LSB ERn 31 16 15 MSB En 0 Rn LSB [Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB : Least significant bit Figure 2.9 General Register Data Formats (2) Rev. 1.
2.5.2 Memory Data Formats Figure 2.10 shows the data formats in memory. The H8S/2000 CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
2.6 Instruction Set The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function as shown in table 2.1. Table 2.
2.6.1 Table of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in tables 2.3 to 2.10 is defined below. Table 2.
Table 2.3 Data Transfer Instructions Instruction Size*1 Function MOV B/W/L (EAs) → Rd, Rs → (EAd) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE MOVTPE POP B B W/L Cannot be used in this LSI. Cannot be used in this LSI. @SP+ → Rn Pops a general register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.
Table 2.4 Arithmetic Operations Instructions (1) Instruction Size* Function ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Subtraction on immediate data and data in a general register cannot be performed in bytes. Use the SUBX or ADD instruction.
Table 2.4 Arithmetic Operations Instructions (2) Instruction Size*1 Function DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder. CMP B/W/L NEG B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets the CCR bits according to the result.
Table 2.5 Logic Operations Instructions Instruction Size* Function AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
Table 2.7 Bit Manipulation Instructions (1) Instruction Size* Function BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ∼ (
Table 2.7 Bit Manipulation Instructions (2) Instruction Size* Function BXOR B C ⊕ ( of ) → C Logically exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ∼ ( of ) → C Logically exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
Table 2.8 Branch Instructions Instruction Size Function Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Table 2.9 System Control Instructions Instruction Size* TRAPA RTE SLEEP LDC — — — B/W STC ANDC ORC XORC NOP Note: * B: Byte W: Word Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) → CCR, (EAs) → EXR Moves the memory operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
2.6.2 Basic Instruction Formats The H8S/2000 CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op), a register field (r), an effective address extension (EA), and a condition field (cc). Figure 2.11 shows examples of instruction formats. • Operation field Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction.
2.7 Addressing Modes and Effective Address Calculation The H8S/2000 CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic operations instructions can use the register direct and immediate addressing modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn) A 16-bit or 32-bit displacement contained in the instruction code is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 2.7.
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 The 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data contained in an instruction code can be used directly as an operand. The ADDS, SUBS, INC, and DEC instructions implicitly contain immediate data in their instruction codes. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. 2.7.
2.7.8 Memory Indirect—@@aa:8 This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand which contains a branch address. The upper bits of the 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode, the memory operand is a word operand and the branch address is 16 bits long.
2.7.9 Effective Address Calculation Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal mode, the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. Table 2.13 Effective Address Calculation (1) No 1 Addressing Mode and Instruction Format op 2 Effective Address Calculation Effective Address (EA) Register direct (Rn) rm Operand is general register contents.
Table 2.13 Effective Address Calculation (2) No 5 Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA) Absolute address @aa:8 31 op 24 23 Don't care abs @aa:16 31 op 0 24 23 16 15 0 Don't care Sign extension abs @aa:24 31 op 8 7 H'FFFF 24 23 0 Don't care abs @aa:32 op 31 6 Immediate #xx:8/#xx:16/#xx:32 op 7 0 24 23 Don't care abs Operand is immediate data.
2.8 Processing States The H8S/2000 CPU has four main processing states: the reset state, exception handling state, program execution state, and program stop state. Figure 2.13 indicates the state transitions. • Reset state In this state the CPU and on-chip peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state.
Program execution state SLEEP instruction with LSON = 0, PSS = 0, SSBY = 1 End of exception handling Request for exception handling SLEEP instruction with LSON = 0, SSBY = 0 Sleep mode Interrupt request Exception-handling state External interrupt request Software standby mode RES = high Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state*3 Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low.
2.9 Usage Notes 2.9.1 Note on TAS Instruction Usage When using the TAS instruction, use registers ER0, ER1, ER4 and ER5. The TAS instruction is not generated by the Renesas Technology H8S and H8/300 series C/C++ compilers. When the TAS instruction is used as a user-defined intrinsic function, use registers ER0, ER1, ER4 and ER5. 2.9.
2.9.4 EEPMOV Instruction 1. EEPMOV is a block-transfer instruction and transfers the byte size of data indicated by R4L, which starts from the address indicated by R5, to the address indicated by R6. R5 R6 R5 + R4L R6 + R4L 2. Set R4L and R6 so that the end address of the destination address (value of R6 + R4L) does not exceed H'FFFF (the value of R6 must not change from H'FFFF to H'0000 during execution). R5 R6 R5 + R4L Invalid H'FFFF R6 + R4L Rev. 1.
Rev. 1.
Section 3 MCU Operating Modes 3.1 MCU Operating Mode Selection This LSI has two operating modes (modes 2 and 3). The operating mode is determined by the setting of the mode pins (MD1 and MD0). Table 3.1 shows the MCU operating mode selection. Table 3.1 lists the MCU operating modes. Table 3.
3.2 Register Descriptions The following registers are related to the operating mode. Mode control register (MDCR) System control register (SYSCR) Serial timer control register (STCR) 3.2.1 Mode Control Register (MDCR) MDCR is used to monitor the current operating mode. Bit Initial Bit Name Value R/W Description 7 EXPE R/W Reserved 0 The initial value should not be changed.
3.2.2 System Control Register (SYSCR) SYSCR selects a system pin function, monitors a reset source, selects the interrupt control mode and the detection edge for NMI, pin location selection, enables or disables register access to the on-chip peripheral modules, and enables or disables on-chip RAM address space. Bit Initial Bit Name Value R/W Description 7 and 6 — R/W Reserved All 0 The initial value should not be changed.
Bit Initial Bit Name Value R/W Description 1 HIE R/W Host Interface Enable 0 Controls CPU access to the keyboard matrix interrupt, input pull-up MOS control registers (KMIMR, KMPCR, and KMIMRA), and the 8-bit timer (TMR_X and TMR_Y) registers (TCR_X/TCR_Y, TCSR_X/TCSR_Y, TICRR/TCORA_Y, TICRF/TCORB_Y, TCNT_X/TCNT_Y, TCORC/TISR, TCORA_X, and TCORB_X, TCONRI, and TCONRS). 0: In areas H'(FF)FFF0 to H'(FF)FFF7 and H'(FF)FFFC to H'(FF)FFFF, CPU access to 8-bit timer (TMR_X and TMR_Y) is permitted.
3.2.3 Serial Timer Control Register (STCR) STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and selects the input clock of the timer counter. Bit Initial Bit Name Value R/W Description 7 IICS R/W I2C Extra Buffer Select 0 Specifies bits 7 to 4 of port A as output buffers similar to SLC and SDA. These pins are used to implement 2 an I C interface only by software. 0: PA7 to PA4 are normal input/output pins.
Bit Initial Bit Name Value R/W Description 3 FLSHE R/W Flash Memory Control Register Enable 0 Enables or disables CPU access for flash memory registers (FLMCR1, FLMCR2, EBR1, EBR2), control registers in power-down state (SBYCR, LPWRCR, MSTPCRH, MSTPCRL), and control registers of onchip peripheral modules (PCSR, SYSCR2). 0: Registers in power-down state and control registers of on-chip peripheral modules are accessed in an area from H'(FF)FF80 to H'(FF)FF87.
3.4 Address Map Figures 3.1 and 3.2 show the address map in each operating mode.
Mode 3 (EXPE = 0) Normal mode Single-chip mode Mode 2 (EXPE = 0) Advanced mode Single-chip mode H'000000 H'0000 On-chip ROM On-chip ROM H'00FFFF Reserved area H'DFFF H'01FFFF H'FFE080 H'FFE480 Reserved area H'E080 H'E480 On-chip RAM On-chip RAM H'EFFF H'FFEFFF H'FFF800 H'FFFE4F H'FFFE50 H'FFFEFF H'FFFF00 H'FFFF7F H'FFFF80 H'FFFFFF Reserved area Internal I/O registers 3 Internal I/O registers 2 On-chip RAM (128 bytes) Internal I/O registers 1 H'F800 H'FE4F H'FE50 H'FEFF H'FF00 H'FF7F H'FF80
Section 4 Exception Handling 4.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, interrupt, direct transition, or trap instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Table 4.
4.2 Exception Sources and Exception Vector Table Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Table 4.
4.3 Reset A reset has the highest exception priority. When the RES pin goes low, all processing halts and this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at power-on. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset initializes the internal state of the CPU and the registers of on-chip peripheral modules. The chip can also be reset by overflow of the watchdog timer.
4.3.2 Interrupts after Reset If an interrupt is accepted after a reset and before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 4.3.
4.4 Interrupt Exception Handling Interrupts are controlled by the interrupt controller. The sources to start interrupt exception handling are external interrupt sources (NMI, IRQ7 to IRQ0, KIN15 to KIN0, and WUE7 to WUE0) and internal interrupt sources from the on-chip peripheral modules. NMI is an interrupt with the highest priority. For details, refer to section 5, Interrupt Controller. Interrupt exception handling is conducted as follows: 1.
4.6 Stack Status after Exception Handling Figure 4.2 shows the stack after completion of trap instruction exception handling and interrupt exception handling. Normal mode SP CCR Advanced mode SP CCR CCR* PC (16 bits) PC (24 bits) Note: Ignored on return. Figure 4.2 Stack Status after Exception Handling Rev. 1.
4.7 Usage Note When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The stack should always be accessed in words or longwords, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W Rn (or MOV.W @SP+, Rn) POP.L ERn (or MOV.
Rev. 1.
Section 5 Interrupt Controller 5.1 Features • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with ICR An interrupt control register (ICR) is provided for setting interrupt priorities. Three priority levels can be set for each module for all interrupts except NMI and address break.
CPU INTM1, INTM0 SYSCR NMIEG NMI input NMI input IRQ input IRQ input ISR KIN input WUE input Interrupt request Vector number ISCR IER KMIMR WUEMR Priority check I, UI KIN and WUE input Internal interrupt request WOVI0 to IBFI3 CCR ICR Interrupt controller [Legend] ICR: Interrupt control register ISCR: IRQ sense control register IER: IRQ enable register ISR: IRQ status register KMIMR: Keyboard matrix interrupt mask register WUEMR: Wake-up event interrupt mask register SYSCR: System control
5.3 Register Descriptions The interrupt controller has the following registers. For details on the system control register (SYSCR), refer to section 3.2.2, System Control Register (SYSCR).
Table 5.2 Correspondence between Interrupt Source and ICR Register Bit Bit Name ICRA ICRB 7 ICRn7 IRQ0 — 6 ICRn6 IRQ1 FRT 5 ICRn5 IRQ2, IRQ3 — 4 ICRn4 IRQ4, IRQ5 — 3 ICRn3 IRQ6, IRQ7 TMR_0 2 ICRn2 — TMR_1 1 ICRn1 WDT_0 TMR_X, TMR_Y 0 ICRn0 WDT_1 Keyboard buffer controller [Legend] n: A to C : Reserved. The write value should always be 0. 5.3.2 ICRC — SCI_1 — IIC_0 IIC_1 TMR_A, TMR_B LPC — Address Break Control Register (ABRKCR) ABRKCR controls the address breaks.
5.3.3 Break Address Registers A to C (BARA to BARC) The BAR registers specify an address that is to be a break address. An address in which the first byte of an instruction exists should be set as a break address. In normal mode, addresses A23 to A16 are not compared. • BARA Bit Initial Bit Name Value 7 to 0 A23 to A16 All 0 R/W Description R/W Addresses 23 to 16 The A23 to A16 bits are compared with A23 to A16 in the internal address bus.
5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL) The ISCR registers select the source that generates an interrupt request at pins IRQ7 to IRQ0.
5.3.5 IRQ Enable Register (IER) IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit Initial Bit Name Value R/W Description 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E R/W R/W R/W R/W R/W R/W R/W R/W IRQn Enable (n = 7 to 0) The IRQn interrupt request is enabled when this bit is 1. 5.3.6 IRQ Status Register (ISR) 0 0 0 0 0 0 0 0 The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests.
• KMIMRA Bit Initial Bit Name Value R/W Description 7 6 5 4 3 2 1 0 KMIMR15 KMIMR14 KMIMR13 KMIMR12 KMIMR11 KMIMR10 KMIMR9 KMIMR8 R/W R/W R/W R/W R/W R/W R/W R/W Keyboard Matrix Interrupt Mask 15 to 8 These bits enable or disable a key-sensing input interrupt request (KIN15 to KIN8).
Figure 5.2 shows the relationship between interrupts IRQ7 and IRQ6, interrupts KIN15 to KIN0, interrupts WUE7 to WUE0, and registers KMIMRA, KMIMR, and WUEMRB.
5.4 Interrupt Sources 5.4.1 External Interrupts There are four types of external interrupts: NMI, IRQ7 to IRQ0, KIN15 to KIN0 and WUE7 to WUE0. WUE7 to WUE0 and KIN15 to KIN8 share the IRQ7 interrupt source, and KIN7 to KIN0 share the IRQ6 interrupt source. Of these, NMI, IRQ7, IRQ6, and IRQ2 to IRQ0 can be used to restore this LSI from software standby mode.
When pin IRQ7 is used as an IRQ7 interrupt pin, set all of bits KMIMR15 to KMIMR8 and WUEMR7 to WUEMR0 to 1. If any of these bits is cleared to 0, IRQ7 interrupt input from the IRQ7 pin will be ignored. Since interrupt request flags IRQ7F to IRQ0F are set each time the setting condition is satisfied, regardless of the IER setting, refer to a needed flag only.
5.5 Interrupt Exception Handling Vector Table Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Modules set at the same priority will conform to their default priorities. Priorities within a module are fixed. An interrupt control level can be specified for a module to which an ICR bit is assigned.
Origin of Interrupt Source Vector Address Name Vector Normal Number Mode ICR Priority TMR_0 CMIA0 (Compare match A) CMIB0 (Compare match A) OVI0 (Overflow) Reserved for system use 64 65 66 67 H'0080 H'0082 H'0084 H'0086 H'000100 H'000104 H'000108 H'00010C ICRB3 High TMR_1 CMIA1 (Compare match A) CMIB1 (Compare match B) OVI1 (Overflow) Reserved for system use 68 69 70 71 H'0088 H'008A H'008C H'008E H'000110 H'000114 H'000118 H'00011C ICRB2 TMR_X, TMR_Y CMIAY (Compare match A) CMIBY (Compar
5.6 Interrupt Control Modes and Interrupt Operation The interrupt controller has two modes: Interrupt control mode 0 and interrupt control mode 1. Interrupt operations differ depending on the interrupt control mode. NMI interrupts and address break interrupts are always accepted except for in reset state or in hardware standby mode. The interrupt control mode is selected by SYSCR. Table 5.4 shows the interrupt control modes. Table 5.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
5.6.2 Interrupt Control Mode 1 In interrupt control mode 1, mask control is applied to three levels for IRQ and on-chip peripheral module interrupt requests by comparing the I and UI bits in CCR in the CPU, and the ICR setting. • An interrupt request with interrupt control level 0 is accepted when the I bit in CCR is cleared to 0.
Figure 5.6 shows a flowchart of the interrupt acceptance operation. 1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. According to the interrupt control level specified in ICR, the interrupt controller only accepts an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt request with interrupt control level 0 (no priority).
Program excution state No Interrupt generated? Yes Yes NMI No No An interrupt with interrupt control level 1? Hold pending Yes IRQ0 Yes No No IRQ0 No Yes IRQ1 No IRQ1 Yes Yes IFBFI3 IFBFI3 Yes Yes No I=0 I=0 Yes No UI = 0 No Yes Yes Save PC and CCR I 1, UI 1 Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 1 Rev. 1.
(1) (2) (4) Instruction prefetch (3) Internal processing Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.) code (not executed) (2) (4) Instruction Instruction prefetch address (Instruction is not executed.
5.6.4 Interrupt Response Times Table 5.5 shows interrupt response times − the intervals between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.5 are explained in table 5.6. Table 5.5 Interrupt Response Times No.
5.7 Address Break 5.7.1 Features This LSI can determine the specific address prefetch by the CPU to generate an address break interrupt by setting ABRKCR and BAR. If an address break interrupt is generated, the address break interrupt exception handling is performed. With this function, the execution start point of a program containing a bug is detected and execution is branched to the correcting program. 5.7.2 Block Diagram Figure 5.8 shows a block diagram of the address break.
5.7.3 Operation If the CPU prefetches an address specified in BAR by setting ABRKCR and BAR, an address break interrupt can be generated. This address break function generates an interrupt request to the interrupt controller at prefetch, and determines the priority by the interrupt controller. When an interrupt is accepted, an interrupt exception handling is activated after the current instruction has been completed.
Figure 5.9 shows an example of address timing.
5.8 Usage Notes 5.8.1 Conflict between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupt requests, the disabling becomes effective after execution of the instruction.
5.8.2 Instructions that Disable Interrupts The instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions are executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit or UI bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.8.3 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.
Rev. 1.
Section 6 Bus Controller (BSC) Since this LSI does not have an externally extended function, it does not have an on-chip bus controller (BSC). Considering the software compatibility with similar products, you must be careful to set appropriate values to the control registers for the bus controller. 6.1 Register Descriptions The bus controller has the following registers. • Bus control register (BCR) • Wait state control register (WSCR) 6.1.
6.1.2 Wait State Control Register (WSCR) Bit Initial Bit Name Value R/W Description 7 — 0 R/W Reserved 6 — 0 R/W The initial value should not be changed. 5 ABW 1 R/W Bus Width Control The initial value should not be changed. 4 AST 1 R/W Access State Control The initial value should not be changed. 3 WMS1 0 R/W Wait Mode Select 1, 0 2 WMS0 0 R/W The initial value should not be changed.
Section 7 I/O Ports This LSI has fifteen I/O ports (ports 1 to 6, 8, 9, and A to G), and one input-only port (port 7). Table 7.1 is a summary of the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port) and data registers (DR, ODR) that store output data. Ports 1 to 3, 6, and A to F have on-chip input pull-up MOSs.
Table 7.
Port Description Mode 2and Mode 3 I/O Status Port 6 General I/O port also functioning as interrupt input, FRT input/output, TMR_X and TMR_Y input/output, and keysense interrupt input On-chip input pullup MOSs Port 7 General input port also functioning as A/D converter analog input Port 8 General I/O port also functioning as interrupt input, SCI_1 input/output, LPC input/output, and IIC_1 input/output pins Port 9 General I/O port also functioning as IIC_0 input/output, subclock input, φ output, i
Port Description Port A General I/O port also functioning as key-sense interrupt input and keyboard buffer controller input/output pins Port B General I/O port also functioning as wakeup event interrupt input and LPC input/output pins Port C General I/O port Port D General I/O port Rev. 1.
Port Description Mode 2and Mode 3 I/O Status Port E General I/O port PE7 On-chip input pullup MOSs PE6 PE5 PE4 PE3 PE2 PE1 PE0 Port F General I/O port also PF7/TMOY* On-chip input pullfunctioning as TMR_X, up MOSs PF6/ExTMOX* TMR_Y, TMR_A, and TMR_B input/output pins PF5/ExTMIY* PF4/ExTMIX* PF3/TMOB PF2/TMOA PF1/TMIB PF0/TMIA PG7/ExSCLB* Port G General I/O port also functioning as IIC_1 and PG6/ExSDAB* IIC_0 input/output pins PG5/ExSCLA* PG4/ExSDAA* PG3 PG2 PG1 PG0 Note: * The program development tool
7.1 Port 1 Port 1 is an 8-bit I/O port. Port 1 pins also function as PWM output pins. Port 1 has the following registers. • Port 1 data direction register (P1DDR) • Port 1 data register (P1DR) • Port 1 pull-up MOS control register (P1PCR) 7.1.1 Port 1 Data Direction Register (P1DDR) P1DDR specifies input or output for the pins of port 1 on a bit-by-bit basis.
7.1.3 Port 1 Pull-Up MOS Control Register (P1PCR) P1PCR controls the on/off state of the port 1 on-chip input pull-up MOSs. Bit Bit Name Initial Value R/W Description 7 P17PCR 0 R/W 6 5 4 3 2 1 0 P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W When a P1PCR bit is set to 1 with the input port setting, the input pull-up MOS is turned on. 7.1.
7.1.5 Port 1 Input Pull-Up MOS Port 1 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 7.2 summarizes the input pull-up MOS states. Table 7.2 Input Pull-Up MOS States (Port 1) Reset Hardware Standby Mode Software Standby Mode In Other Operations Off Off On/Off On/Off [Legend] Off: Input pull-up MOS is always off.
7.2.2 Port 2 Data Register (P2DR)) P2DR stores output data for port 2. Bit Bit Name Initial Value R/W Description 7 P27DR 0 R/W 6 5 4 3 2 1 0 P26DR P25DR P24DR P23DR P22DR P21DR P20DR 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly, regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. 7.2.
7.2.5 Port 2 Input Pull-Up MOS Port 2 has an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be specified as on or off on a bit-by-bit basis. Table 7.3 summarizes the input pull-up MOS states. Table 7.3 Input Pull-Up MOS States (Port 2) Reset Hardware Standby Mode Software Standby Mode In Other Operations Off Off On/Off On/Off [Legend] Off: Input pull-up MOS is always off.
7.3.2 Port 3 Data Register (P3DR) P3DR stores output data of port 3. Bit Bit Name Initial Value R/W Description 7 P37DR 0 R/W 6 5 4 3 2 1 0 P36DR P35DR P34DR P33DR P32DR P31DR P30DR 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly, regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. 7.3.
7.3.4 Pin Functions • P37/SERIRQ, P36/LCLK, P35/LRESET, P34/LFRAME, P33/LAD3, P32/LAD2, P31/LAD1, P30/LAD0 The pin function is switched as shown below according to the combination of the LPC3E to LPC1E bits in HICR0 of the host interface (LPC) and the P3nDDR bit. LPCmE All 0 Not all 0 P3nDDR 0 1 0 Pin Function P37 to P30 input pins P37 to P30 output pins LPC input/output pins Note: The combination of bits not described in the above table must not be used.
7.4 Port 4 Port 4 is an 8-bit I/O port. Port 4 pins also function as TMR_0 and TMR_1 I/O pins, and the IIC_1 I/O pin. The output type of P42 is NMOS push-pull output. The output type of SDA1 is NMOS open-drain output. Port 4 has the following registers. • Port 4 data direction register (P4DDR) • Port 4 data register (P4DR) 7.4.1 Port 4 Data Direction Register (P4DDR) P4DDR specifies input or output for the pins of port 4 on a bit-by-bit basis.
7.4.3 Pin Functions • P47 The pin function is switched as shown below according to the combination of the P47DDR bit. P47DDR Pin Function 0 P47 input pin 1 P47 output pin • P46 The pin function is switched as shown below according to the combination of the P46DDR bit. P46DDR Pin Function 0 P46 input pin 1 P46 output pin • P45/TMRI1 The pin function is switched as shown below according to the combination of the P45DDR bit.
• P43/TMCI1 The pin function is switched as shown below according to the state of the P43DDR bit. P43DDR Pin Function Note: * 0 P43 input pin 1 P43 output pin TMCI1 input pin* When the external clock is selected by the bits CKS2 to CKS0 in TCR1 of TMR_1, this pin is used as the TMCI1 input pin. • P42/TMRI0/SDA1 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_1, the IIC1AS and the IIC1BS bits in PGCTL*2, and the P42DDR bit.
7.5 Port 5 Port 5 is a 3-bit I/O port. Port 5 pins also function as SCI_1 extended I/O pins, and the IIC_0 I/O pin. P52 and ExSCK1 are NMOS push-pull outputs, and SCL0 is an NMOS open-drain output. Port 5 has the following registers. • Port 5 data direction register (P5DDR) • Port 5 data register (P5DR) 7.5.1 Port 5 Data Direction Register (P5DDR) P5DDR specifies input or output for the pins of port 5 on a bit-by-bit basis.
7.5.3 Pin Functions • P52/ExSCK1*/SCL0 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, the CKE0 and CKE1 bits in SCR, the SPS1 bit*1 in SPSR, the ICE bit in ICCR of IIC_0, the IIC0AS and the IIC0BS bits in PGCTL*2, and the P52DDR bit.
• P50/ExTxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1, the SPS1 bit* in SPSR, and the P50DDR bit. SPS1* TE P50DDR Pin Function Note: 7.6 * 0 — 0 P50 input pin 1 0 1 P50 output pin 0 1 P50 input P50 output pin pin The program development tool (emulator) does not support this function. 1 — ExTxD1 output pin* Port 6 Port 6 is an 8-bit I/O port.
7.6.2 Port 6 Data Register (P6DR) P6DR stores output data for port 6. Bit Bit Name Initial Value R/W Description 7 P67DR 0 R/W 6 5 4 3 2 1 0 P66DR P65DR P64DR P63DR P62DR P61DR P60DR 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly, regardless of the actual pin states. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. 7.6.
7.6.4 System Control Register 2 (SYSCR2) SYSCR2 is not available in this LSI although originally designed to control the port 6 operations. Bit Bit Name Initial Value R/W Description 7 to 0 — All 0 R/W Reserved The initial value should not be changed. 7.6.5 Pin Functions • P67/TMOX/KIN7/IRQ7 The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR of TMR_X, the IOSX bit*2 in TCRXY, and the P67DDR bit.
• P66/FTOB/KIN6/IRQ6 The pin function is switched as shown below according to the combination of the OEB bit in TOCR of the FRT and the P66DDR bit. OEB P66DDR Pin Function Note: * 0 1 1 — P66 output pin FTOB output pin IRQ6 input pin, KIN6 input pin* This pin is used as the IRQ6 input pin when bit IRQ6E is set to 1 in IER while the KMIMR6 bit in KMIMR is 0. It can always be used as the KIN6 input pin.
• P61/FTOA/KIN1 The pin function is switched as shown below according to the combination of the OEA bit in TOCR of the FRT, and the P61DDR bit. OEA P61DDR Pin Function Note: * 0 0 P61 input pin 1 P61 output pin KIN1 input pin* This pin can always be used as the KIN1 input pin. 1 — FTOA input pin • P60/FTCI/KIN0/TMIX P60DDR Pin Function Note: * 7.6.
7.7 Port 7 Port 7 is an 8-bit input only port. Port 7 pins also function as the A/D converter analog input pins. Port 7 has the following register. • Port 7 input data register (P7PIN) 7.7.1 Port 7 Input Data Register (P7PIN) P7PIN reflects the pin states of port 7. Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value R/W Description P77PIN Undefined* R When a P7PIN read is performed, the pin states are always read.
7.8 Port 8 Port 8 is an 8-bit I/O port. Port 8 pins also function as SCI_1 I/O pins, the IIC_1 I/O pins, LPC I/O pins, and interrupt input pins. The output type of P86 and SCK1 is NMOS push-pull output. The output type of SCL1 is NMOS open-drain output and direct bus driving is enabled. Port 8 has the following registers. • Port 8 data direction register (P8DDR) • Port 8 data register (P8DR) 7.8.
7.8.3 Pin Functions • P86/IRQ5/SCK1/SCL1 The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI_1, the CKE0 and CKE1 bits in SCR, the SPS1 bit*2 in SPSR, the ICE bit in ICCR of IIC_1, the IIC1AS and the IIC1BS bits in PGCTL*3, and the 86DDR bit.
• P84/IRQ3/TxD1 The pin function is switched as shown below according to the combination of the TE bit in SCR of SCI_1, the SPS1 bit*2 in SPSR, and the P84DDR bit. 2 1 1 — 0 1 — 0 1 P84 input P84 output TxD1 P84 input pin P84 output pin pin pin output pin IRQ3 input pin*1 Notes: 1. When the IRQ3E bit in IER is set to 1, this pin is used as the IRQ3 input pin. 2. The program development tool (emulator) does not support this function.
• P81/GA20 The pin function is switched as shown below according to the combination of the FGA20E bit in HICR0 and the P81DDR bit. FGA20E P81DDR Pin Function Note: * 0 1 1 0* P81 output pin GA20 output pin GA20 input pin When bit FGA20E is set to 1 in HICR0, the P81DDR bit should be cleared to 0. 0 P81 input pin • P80/PME The pin function is switched as shown below according to the combination of the PMEE bit in HICR0 and the P80DDR bit.
7.9 Port 9 Port 9 is an 8-bit I/O port. Port 9 pins also function as the interrupt input pins, IIC_0 I/O pin, subclock input pin, and system clock (φ) output pin. P97 is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability. Port 9 has the following registers. • Port 9 data direction register (P9DDR) • Port 9 data register (P9DR) 7.9.1 Port 9 Data Direction Register (P9DDR) P9DDR specifies input or output for the pins of port 9 on a bit-by-bit basis.
7.9.3 Pin Functions • P97/SDA0 The pin function is switched as shown below according to the combination of the ICE bit in ICCR of IIC_0, the IIC0AS and the IIC0BS bits in PGCTL*, and the P97DDR bit. P97ICE = ICE • (IIC0AS+IIC0BS)* P97ICE* 0 1 P97DDR 0 1 — Pin Function P97 input pin P97 output pin SDA0 I/O pin Note: When this pin is set as the P97 output pin, it is an NMOS push-pull output. SDA0 is an NMOS open-drain output, and has direct bus drive capability.
• P92/IRQ0 The pin function is switched as shown below according to the state of the P92DDR bit. P92DDR Pin Function Note: * 0 P92 input pin 1 P92 output pin IRQ0 input pin* When bit IRQ0E in IER is set to 1, this pin is used as the IRQ0 input pin. • P91/IRQ1 The pin function is switched as shown below according to the state of the P91DDR bit. P91DDR Pin Function Note: * 0 P91 input pin 1 P91 output pin IRQ1 input pin* When bit IRQ1E in IER is set to 1, this pin is used as the IRQ1 input pin.
7.10 Port A Port A is an 8-bit I/O port. Port A pins also function as keyboard buffer controller I/O pins, and key-sense interrupt input pins. Port A input/output operates by VccB power independent from the Vcc power. Up to 5 V can be applied to port A pins if VccB power is 5 V. Port A has the following registers. PADDR and PAPIN have the same address. • Port A data direction register (PADDR) • Port A output data register (PAODR) • Port A input data register (PAPIN) 7.10.
7.10.3 Port A Input Data Register (PAPIN) PAPIN indicates the port A state. Bit 7 6 5 4 3 2 1 0 Note: Bit Name Initial Value R/W Description PA7PIN Undefined* R Reading PAPIN always returns the pin states. PAPIN has the same address as PADDR. If a write is PA6PIN Undefined* R performed, the port A settings will change.
• PA5/KIN13/PS2BD The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_1 of the keyboard buffer controller, and the PA5DDR bit. KBIOE PA5DDR Pin Function Note: * 0 1 1 — PA5 output pin PS2BD output pin KIN13 input pin, PS2BD input pin* When the KBIOE bit is set to 1 or the IICS bit in STCR is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2BD or KIN13 input pin.
• PA2/KIN10/PS2AC The pin function is switched as shown below according to the combination of the KBIOE bit in KBCRH_0 of the keyboard buffer controller, and the PA2DDR bit. KBIOE PA2DDR Pin Function Note: * 0 1 1 — PA2 output pin PS2AC output pin KIN10 input pin, PS2AC input pin* When the KBIOE bit is set to 1, this pin is an NMOS open-drain output, and has direct bus drive capability. This pin can always be used as the PS2AC or KIN10 input pin.
7.11 Port B Port B is an 8-bit I/O port. Port B pins also have LPC input/output pins, and wakeup event interrupt input pins function. Port B has the following registers. • Port B data direction register (PBDDR) • Port B output data register (PBODR) • Port B input data register (PBPIN) 7.11.1 Port B Data Direction Register (PBDDR) PBDDR specifies input or output for the pins of port B on a bit-by-bit basis.
7.11.3 Port B Input Data Register (PBPIN) PBPIN indicates the port B state. Bit Initial Bit Name Value 7 PB7PIN 6 5 4 3 2 1 0 Note: R/W Undefined* R Description Reading PBPIN always returns the pin states. PBPIN has the same address as P8DDR. If a write is performed, data will be written to P8DDR and the port 8 settings will change.
• PB0/WUE0/LSMI The pin function is switched as shown below according to the combination of the LSMIE bit in HICR0 of the host interface (LPC) and the PB0DDR bit. LSMIE PB0DDR Pin Function 1 1 0*1 PB0 output pin LSMI output pin 2 WUE0 input pin* , LSMI input pin*2 Notes: 1. When the LSMIE bit in HICR0 is set to 1, the PB0DDR bit should be cleared to 0. 2. This pin can always be used as the WUE0 or LSMI input pin. 7.11.
7.12 Ports C, D Port C and port D are two sets of 8-bit I/O ports. Port C and port D have the following registers. • • • • • • • • Port C data direction register (PCDDR) Port C output data register (PCODR) Port C input data register (PCPIN) Port C Nch-OD control register (PCNOCR) Port D data direction register (PDDDR) Port D output data register (PDODR) Port D input data register (PDPIN) Port D Nch-OD control register (PDNOCR) 7.12.
7.12.2 Port C and Port D Output Data Registers (PCODR, PDODR) PCODR and PDODR store output data for the pins on ports C and D. Bit Initial Bit Name Value R/W Description 7 PC7ODR 0 R/W 6 5 4 3 2 1 0 PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR R/W R/W R/W R/W R/W R/W R/W PCODR can always be read or written to, regardless of the contents of PCDDR.
Bit 7 6 5 4 3 2 1 0 Note: 7.12.4 Initial Bit Name Value R/W Description PD7PIN Undefined* R PDPIN indicates the port D state. PDPIN has the same address as PDDDR. If a write is performed, the port D PD6PIN Undefined* R settings will change. PD5PIN Undefined* R PD4PIN Undefined* R PD3PIN Undefined* R PD2PIN Undefined* R PD1PIN Undefined* R PD0PIN Undefined* R * The initial value is determined according to the PD7 to PD0 pin states.
7.12.5 Pin Functions DDR NOCR ODR N-ch. driver P-ch. driver Input pull-up MOS Pin function 7.12.6 0 — 0 1 0 1 OFF OFF OFF 0 ON OFF 1 1 OFF ON ON 0 ON 1 OFF OFF OFF Input pin Output pin Input Pull-Up MOS in Ports C and D Port C and port D have an on-chip input pull-up MOS function that can be controlled by software. This input pull-up MOS function can be switched on or off on a bit-by-bit basis. Table 7.8 is a summary of the input pull-up MOS states. Table 7.
7.13 Ports E, F Ports E and F are two sets of 8-bit I/O ports. Port F also functions as I/O pins for TMR_X*, TMR_Y*, TMR_A, and TMR_B. Ports E and F have the following registers. • • • • • • • • Port E data direction register (PEDDR) Port E output data register (PEODR) Port E input data register (PEPIN) Port E Nch-OD control register (PENOCR) Port F data direction register (PFDDR) Port F output data register (PFODR) Port F input data register (PFPIN) Port F Nch-OD control register (PFNOCR) Note: * 7.13.
7.13.2 Port E and Port F Output Data Registers (PEODR, PFODR) PEODR and PFODR store output data for the pins on ports E and F. Bit Bit Name Initial Value R/W Description 7 PE7ODR 0 R/W 6 5 4 3 2 1 0 PE6ODR PE5ODR PE4ODR PE3ODR PE2ODR PE1ODR PE0ODR 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W PEODR can always be read or written to, regardless of the contents of PEDDR.
7.13.3 Port E and Port F Input Data Registers (PEPIN, PFPIN) Reading PEPIN and PFPIN always returns the pin states. Bit Bit Name Initial Value 7 PE7PIN Undefined* R 6 5 4 3 2 1 0 Note: Description PEPIN indicates the port E state. PEPIN has the same address as PEDDR. If a write is performed, the port E settings will change.
• PF6/ExTMOX The pin function is switched as shown below according to the combination of the IOSX bit* in TCRXY of TMR_X, the OS3 to OS0 bits in TCSR_X, and the PF6DDR bit. IOSX* OS3 to OS0 PF6DDR Pin Function Notes: * 0 — 1 All 0 0 1 0 1 PF6 PF6 PF6 PF6 input pin output pin input pin output pin The program development tool (emulator) does not support this function. Not all 0 — ExTMOX output pin* • PF5/ExTMIY The pin function is switched as shown below according to the state of the PF5DDR bit.
• PF2/TMOA The pin function is switched as shown below according to the combination of the OS3 to OS0 bits in TCSR_A of TMR_A and the PF2DDR bit. OS3 to OS0 PF3DDR Pin Function All 0 0 PF2 input pin 1 PF2 output pin Not all 0 — TMOA output pin • PF1/TMIB The pin function is switched as shown below according to the state of the PF1DDR bit. PF1DDR Pin Function Note: * 0 PF1 input pin 1 PF1 output pin TMIB input pin* This pin can always be used as the TMIB input pin.
Bit Bit Name Initial Value R/W Description 0: CMOS (p-channel driver enabled) 1: N-channel open drain (p-channel driver disabled) 7 PF7NOCR 0 R/W 6 5 4 3 2 1 0 PF6NOCR PF5NOCR PF4NOCR PF3NOCR PF2NOCR PF1NOCR PF0NOCR 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W 7.13.6 Pin Functions DDR 0 NOCR — ODR 0 1 N-ch. driver OFF P-ch. driver OFF Input pull-up OFF ON MOS Pin function Input pin Note: * Includes when set as the timer output pin. 7.13.
7.14 Port G Port G is an 8-bit I/O port. Port G pins also function as IIC_0 and IIC_1 I/O pins. The output type of port G is NMOS push-pull output. The output type of ExSCLB*, ExSDAB*, ExSCLA*, and ExSDAA* is NMOS open-drain output and the pins can directly drive the bus. Port G has the following registers. For details of PGCTL, see section 13.3.9, Port G Control Register (PGCTL).
7.14.2 Port G Output Data Register (PGODR) PGODR stores output data for the pins on port G. Bit Bit Name Initial Value R/W Description 7 PG7ODR 0 R/W 6 5 4 3 2 1 0 PG6ODR PG5ODR PG4ODR PG3ODR PG2ODR PG1ODR PG0ODR 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W PGODR can always be read or written to, regardless of the contents of PGDDR. 7.14.3 Port G Input Data Register (PGPIN) Reading PGPIN always returns the pin states.
7.14.4 Pin Functions • PG7/ExSCLB The pin function is switched as shown below according to the combination of the IIC1BS and the IIC0BS bits in PGCTL of the IIC* and the PG7DDR bit. IIC1BS and IIC0BS* All 0 Not all 0 PG7DDR 0 1 — Pin Function PG7 input pin PG7 output pin ExSCLB I/O pin* Note: * The program development tool (emulator) does not support this function. The output type of ExSCLB is NMOS open-drain output and this pin has direct bus drive capability.
• PG3, PG2, PG1, PG0 The pin function is switched as shown below according to the state of the PGnDDR bit. PGnDDR Pin Function [Legend] n = 3 to 0 7.14.5 0 PGn input pin 1 PGn output pin Port G Nch-OD Control Register (PGNOCR) PGNOCR specifies the output driver type for pins on port G which are configured as outputs on a bit-by-bit basis.
Rev. 1.
Section 8 8-Bit PWM Timer (PWM) This LSI has an on-chip pulse width modulation (PWM) timer with eight outputs. Eight output waveforms are generated from a common time base, enabling PWM output with a high carrier frequency to be produced using pulse division. Connecting a low pass filter externally to the LSI enables the PWM to function as an 8-bit D/A converter. 8.
8.2 Input/Output Pins Table 8.1 shows the PWM output pins. Table 8.1 Pin Configuration Name Abbreviation I/O Function PWM output 7 to 0 PW7 to PW0 Output PWM timer pulse output 7 to 0 8.3 Register Descriptions The PWM has the following registers. To access PCSR, the FLSHE bit in the serial timer control register (STCR) must be cleared to 0. For details on the serial timer control register (STCR), see section 3.2.3, Serial Timer Control Register (STCR).
8.3.1 PWM Register Select (PWSL) PWSL is used to select the input clock and the PWM data register. Bit Bit Name Initial Value R/W Description 7 PWCKE 0 R/W 6 PWCKS 0 R/W PWM Clock Enable PWM Clock Select These bits, together with bits PWCKC, PWCKB and PWCKA in PCSR, select the internal clock input to TCNT in the PWM. For details, see table 8.2. The resolution, PWM conversion period, and carrier frequency depend on the selected internal clock, and can be obtained from the following equations.
Table 8.2 Internal Clock Selection PWSL PCSR PWCKE PWCKS PWCKC PWCKB PWCKA Description 0 — — — — Clock input is disabled 1 0 — — — φ (system clock) is selected 1 0 0 0 φ/2 is selected 0 0 1 φ/4 is selected 0 1 0 φ/8 is selected 0 1 1 φ/16 is selected 1 0 0 φ/256 is selected* 1 0 1 φ/512 is selected* 1 1 0 φ/1024 is selected* 1 1 1 φ/4096 is selected* Note: * Table 8.
8.3.2 PWM Data Registers 7 to 0 (PWDR7 to PWD0) PWDR are 8-bit readable/writable registers. The PWM has eight PWM data registers. Each PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16.
8.3.4 PWM Output Enable Register A (PWOERA) PWOERA switches between PWM output and port output. Bit Bit Name Initial Value R/W Description 7 OE7 0 R/W Output Enable 7 to 0 6 OE6 0 R/W 5 OE5 0 R/W 4 OE4 0 R/W These bits, together with P1DDR, specify the P1n/PWn pin state. Bits OE7 to OE0 correspond to outputs PW7 to PW0.
8.4 Operation The upper four bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. Table 8.4 shows the duty cycles of the basic pulse. Table 8.4 Duty Cycle of Basic Pulse Upper 4 Bits Basic Pulse Waveform (Internal) B'0000 H: 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 L: B'0001 B'0010 B'0011 B'0100 B'0101 B'0110 B'0111 B'1000 B'1001 B'1010 B'1011 B'1100 B'1101 B'1110 B'1111 Rev. 1.
The lower four bits of PWDR specify the position of pulses added to the 16 basic pulses. An additional pulse adds a high period (when OS = 0) with a width equal to the resolution before the rising edge of a basic pulse. When the upper four bits of PWDR are B'0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same. Table 8.5 shows the positions of the additional pulses added to the basic pulses, and figure 8.2 shows an example of additional pulse timing. Table 8.
8.4.1 PWM Setting Example 1-conversion cycle Duty cycle Basic waveform Additiona pulse H'7F 127/256 112 pulses 15 pulses H'80 128/256 128 pulses 0 pulses H'81 129/256 128 pulses 1 pulse H'82 130/256 128 pulses 2 pulses PWDR setting example 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 : Pulse added Combination of the basic pulse and added pulse outputs 0/256 to 255/256 of dudty cycle as low ripple wave form. Figure 8.3 Example of PWM Setting 8.4.
8.5 8.5.1 Usage Notes Module Stop Mode Setting PWM operation can be enabled or disabled by the module stop control register. In the initial state, PWM operation is disabled. Access to PWM registers is enabled when module stop mode is cancelled. For details, see section 20, Power-Down Modes. Rev. 1.
Section 9 16-Bit Free-Running Timer (FRT) This LSI has an on-chip 16-bit free-running timer (FRT). The FRT operates on the basis of the 16bit free-running counter (FRC), and outputs two independent waveforms, and measures the input pulse width and external clock periods. 9.1 Features • Selection of four clock sources One of the three internal clocks (φ/2, φ/8, or φ/32), or an external clock input can be selected (enabling use as an external event counter).
Figure 9.1 shows a block diagram of the FRT.
9.2 Input/Output Pins Table 9.1 lists the FRT input and output pins. Table 9.
9.3.1 Free-Running Counter (FRC) FRC is a 16-bit readable/writable up-counter. The clock source is selected by bits CKS1 and CKS0 in TCR. FRC can be cleared by compare-match A. When FRC overflows from H'FFFF to H'0000, the overflow flag bit (OVF) in TCSR is set to 1. FRC should always be accessed in 16-bit units; cannot be accessed in 8-bit units. FRC is initialized to H'0000. 9.3.
9.3.4 Output Compare Registers AR and AF (OCRAR, OCRAF) OCRAR and OCRAF are 16-bit readable/writable registers. When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added alternately to OCRA, and the result is written to OCRA. The write operation is performed on the occurrence of compare-match A. In the 1st compare-match A after setting the OCRAMS bit to 1, OCRAF is added.
9.3.6 Timer Interrupt Enable Register (TIER) TIER enables and disables interrupt requests. Bit Bit Name Initial Value R/W Description 7 ICIAE 0 R/W Input Capture Interrupt A Enable Selects whether to enable input capture interrupt A request (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
Bit Bit Name Initial Value R/W Description 2 OCIBE 0 R/W Output Compare Interrupt B Enable Selects whether to enable output compare interrupt B request (OCIB) when output compare flag B (OCFB) in TCSR is set to 1. 0: OCIB requested by OCFB is disabled 1: OCIB requested by OCFB is enabled 1 OVIE 0 R/W Timer Overflow Interrupt Enable Selects whether to enable a free-running timer overflow request interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.
Bit Bit Name Initial Value R/W Description 6 ICFB 0 R/(W)* Input Capture Flag B This status flag indicates that the FRC value has been transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value has been transferred to ICRB. Only 0 can be written to this bit to clear the flag.
Bit Bit Name Initial Value R/W Description 3 OCFA 0 R/(W)* Output Compare Flag A This status flag indicates that the FRC value matches the OCRA value. Only 0 can be written to this bit to clear the flag. [Setting condition] When FRC = OCRA [Clearing condition] Read OCFA when OCFA = 1, then write 0 to OCFA 2 OCFB 0 R/(W)* Output Compare Flag B This status flag indicates that the FRC value matches the OCRB value. Only 0 can be written to this bit to clear the flag.
9.3.8 Timer Control Register (TCR) TCR selects the rising or falling edge of the input capture signals, enables the input capture buffer mode, and selects the FRC clock source. Bit Bit Name Initial Value R/W Description 7 IEDGA 0 R/W Input Edge Select A Selects the rising or falling edge of the input capture A signal (FTIA).
Bit Bit Name Initial Value R/W Description 1 CKS1 0 R/W Clock Select 1, 0 0 CKS0 0 Select clock source for FRC. 00: φ/2 internal clock source 01: φ/8 internal clock source 10: φ/32 internal clock source 11: External clock source (counting at FTCI rising edge) 9.3.
Bit Bit Name Initial Value R/W Description 4 OCRS 0 R/W Output Compare Register Select OCRA and OCRB share the same address. When this address is accessed, the OCRS bit selects which register is accessed. The operation of OCRA or OCRB is not affected. 0: OCRA is selected 1: OCRB is selected 3 OEA 0 R/W Output Enable A Enables or disables output of the output compare A output pin (FTOA).
9.4 Operation 9.4.1 Pulse Output Figure 9.2 shows an example of 50%-duty pulses output with an arbitrary phase difference. When a compare match occurs while the CCLRA bit in TCSR is set to 1, the OLVLA and OLVLB bits are inverted by software. FRC H'FFFF Counter clear OCRA OCRB H'0000 FTOA FTOB Figure 9.2 Example of Pulse Output Rev. 1.
9.5 Operation Timing 9.5.1 FRC Increment Timing Figure 9.3 shows the FRC increment timing with an internal clock source. Figure 9.4 shows the increment timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is shorter than 1.5 system clocks (φ). φ Internal clock FRC input clock FRC N–1 N N+1 Figure 9.
9.5.2 Output Compare Output Timing A compare-match signal occurs at the last state when the FRC and OCR values match (at the timing when the FRC updates the counter value). When a compare-match signal occurs, the level selected by the OLVL bit in TOCR is output at the output compare pin (FTOA or FTOB). Figure 9.5 shows the timing of this operation for compare-match A.
9.5.4 Input Capture Input Timing The rising or falling edge can be selected for the input capture input timing by the IEDGA to IEDGD bits in TCR. Figure 9.7 shows the usual input capture timing when the rising edge is selected. φ Input capture input pin Input capture signal Figure 9.7 Input Capture Input Signal Timing (Usual Case) If ICRA to ICRAD are read when the corresponding input capture signal arrives, the internal input capture signal is delayed by one system clock (φ). Figure 9.
9.5.5 Buffered Input Capture Input Timing ICRC and ICRD can operate as buffers for ICRA and ICRB, respectively. Figure 9.9 shows how input capture operates when ICRC is used as ICRA's buffer register (BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDGA = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges of FTIA. φ FTIA Input capture signal FRC n n+1 N N+1 ICRA M n n N ICRC m M M n Figure 9.
9.5.6 Timing of Input Capture Flag (ICF) Setting The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB, ICRC, or ICRD). Figure 9.11 shows the timing of setting the ICFA to ICFD flag. φ Input capture signal ICFA to ICFD FRC N ICRA to ICRD N Figure 9.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting 9.5.
9.5.8 Timing of FRC Overflow Flag Setting The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000). Figure 9.13 shows the timing of setting the OVF flag. φ FRC H'FFFF H'0000 Overflow signal OVF Figure 9.13 Timing of Overflow Flag (OVF) Setting 9.5.9 Automatic Addition Timing When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to OCRA is performed.
9.5.10 Mask Signal Generation Timing When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a signal that masks the ICRD input capture signal is generated. The mask signal is set by the input capture signal. The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and an FRC compare-match. Figure 9.15 shows the timing of setting the mask signal. Figure 9.16 shows the timing of clearing the mask signal.
9.6 Interrupt Sources The free-running timer can request seven interrupts: ICIA to ICID, OCIA, OCIB, and FOVI. Each interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the interrupt controller for each interrupt. Table 9.2 lists the sources and priorities of these interrupts. Table 9.
9.7.2 Conflict between FRC Write and Increment If an FRC increment pulse is generated during the state after an FRC write cycle, the write takes priority and FRC is not incremented. Figure 9.18 shows the timing for this type of conflict. Write cycle of FRC T1 T2 φ Address FRC address Internal write signal FRC input clock FRC M N Write data Figure 9.18 FRC Write-Increment Conflict 9.7.
Write cycle of OCR T2 T1 φ Address OCR address Internal write signal FRC N OCR N N+1 M Write data Compare-match signal Disabled Figure 9.19 Conflict between OCR Write and Compare-Match (When Automatic Addition Function is Not Used) φ Address OCRAR (OCRAF) address Internal write signal OCRAR (OCRAF) Compare-match signal Old data New data Disabled FRC N OCR N N+1 Automatic addition is not performed because compare-match signals are disabled. Figure 9.
9.7.4 Switching of Internal Clock and FRC Operation When the internal clock is changed, the changeover may cause FRC to increment. This depends on the time at which the clock is switched (bits CKS1 and CKS0 are rewritten), as shown in table 9.3. When an internal clock is used, the FRC clock is generated on detection of the falling edge of the internal clock scaled from the system clock (φ). If the clock is changed when the old source is high and the new source is low, as in case no. 3 in table 9.
No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits Switching from high to low FRC Operation Clock before switchover Clock after switchover * FRC clock FRC N N+1 N+2 CKS bit rewrite 4 Switching from high to high Clock before switchover Clock after switchover FRC clock FRC N N+1 N+2 CKS bit rewrite Note: * Generated on the assumption that the switchover is a falling edge; FRC is incremented. 9.7.
Rev. 1.
Section 10 8-Bit Timer (TMR) This LSI has an on-chip 8-bit timer module (TMR_0, TMR_1, TMR_Y, TMR_X, TMR_B, and TMR_A) with six channels operating on the basis of an 8-bit counter. The 8-bit timer module can be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two registers. 10.
Table 10.
Figures 10.1 to 10.3 show block diagrams of 8-bit timers.
Internal clock sources TMR_X φ, φ/2, φ/4, φ/2048*, φ/4096*, φ/8192* TMR_Y φ/4, φ/256, φ/2048, φ/4096*, φ/8192*, φ/16384* ExTMCIY*/TMCIY ExTMCIX*/TMCIX Clock select * Clock X Clock Y * Compare-match AX Compare-match AY Overflow X Overflow Y TCORA_Y TCORA_X Comparator A_Y Comparator A_X TCNT_Y TCNT_X Clear Y Compare- match BX TMOY* ExTMRIY*/TMRIY Compare-match BY Clear X Comparator B_Y Comparator B_X TCORB_Y TCORB_X Control logic ExTMOX*/TMOX ExTMRIX*/TMRIX Input capture TICRR TICRF TICR
Internal clock sources TMR_A φ, φ/2, φ/4, φ/2048, φ/4096, φ/8192 TMR_B φ/4, φ/256, φ/2048, φ/4096, φ/8192, φ/16384 Clock select Clock A Clock B Compare-match AA Compare-match AB Overflow A Overflow B TCORA_B TCORA_A Comparator A_B Comparator A_A TCNT_B TCNT_A Clear B Compare- match BA TMOB TMRIB Compare-match BB Control logic TMOA TMRIA Clear A Comparator B_B Comparator B_A TCORB_B TCORB_A Input capture Internal bus External clock sources TMCIB TMCIA TICRR_A TICRF_A TICR_A TCSR_B TCS
10.2 Input/Output Pins Table 10.2 summarizes the input and output pins of the TMR. Table 10.
10.3 Register Descriptions The TMR has the following registers. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR).
For both TMR_Y and TMR_X Timer XY control register (TCRXY) TMR_B Timer counter_B (TCNT_B) Time constant register A_B (TCORA_B) Time constant register B_B (TCORB_B) Timer control register_B (TCR_B) Timer control/status register_B (TCSR_B) Timer input select register_B (TISR_B) TMR_A Timer counter_A (TCNT_A) Time constant register A_A (TCORA_A) Time constant register B_A (TCORB_A) Timer control register_A (TCR_A) Timer control/status register_A (TCSR_A) Input capture register_A (TICR_A) Input capture register
10.3.1 Timer Counter (TCNT) Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16bit register, so they can be accessed together by word access. The clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external reset input signal, comparematch A signal or compare-match B signal. The method of clearing can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from H'FF to H'00), the OVF bit in TCSR is set to 1.
10.3.4 Timer Control Register (TCR) TCR selects the TCNT clock source and the condition by which TCNT is cleared, and enables/disables interrupt requests. TCR_Y can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 1. TCR_X can be accessed when the HIE bit in SYSCR is 0 and the TMRX/Y bit in TCONRS is 0.
Table 10.
Table 10.
Table 10.
10.3.5 Timer Control/Status Register (TCSR) TCSR indicates the status flags and controls compare-match output.
TCSR_1 Bit Bit Name Initial Value R/W 7 CMFB 0 R/(W)* 6 5 4 3 2 1 0 Note: Description Compare-Match Flag B [Setting condition] When the values of TCNT_1 and TCORB_1 match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_1 and TCORA_1 match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_1 overflows from H'FF to H'00 [
TCSR_Y Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)*1 6 CMFA 0 R/(W)*1 5 OVF 0 R/(W)*1 4 ICIE 0 R/W Compare-Match Flag B [Setting condition] When the values of TCNT_Y and TCORB_Y match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB Compare-Match Flag A [Setting condition] When the values of TCNT_Y and TCORA_Y match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA Timer Overflow Flag [Setting condition] When TCNT_Y overflows from H'FF to
TCSR_X Bit Bit Name Initial Value R/W 7 CMFB 0 R/(W)* 6 5 4 3 2 1 0 Note: Description Compare-Match Flag B [Setting condition] When the values of TCNT_X and TCORB_X match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_X and TCORA_X match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_X overflows from H'FF to H'00
TCSR_B Bit Bit Name Initial Value R/W Description 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICIE 0 R/W Compare-Match Flag B [Setting condition] When the values of TCNT_B and TCORB_B match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB Compare-Match Flag A [Setting condition] When the values of TCNT_B and TCORA_B match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA Timer Overflow Flag [Setting condition] When TCNT_B overflows from H'FF to H'
TCSR_A Bit Bit Name Initial Value R/W 7 CMFB 0 R/(W)* 6 5 4 3 2 1 0 Note: Description Compare-Match Flag B [Setting condition] When the values of TCNT_A and TCORB_A match [Clearing condition] Read CMFB when CMFB = 1, then write 0 in CMFB CMFA 0 R/(W)* Compare-Match Flag A [Setting condition] When the values of TCNT_A and TCORA_A match [Clearing condition] Read CMFA when CMFA = 1, then write 0 in CMFA OVF 0 R/(W)* Timer Overflow Flag [Setting condition] When TCNT_A overflows from H'FF to H'00
10.3.6 Time Constant Register (TCORC) TCORC is an 8-bit readable/writable register. The sum of contents of TCORC and TICR is always compared with TCNT. When a match is detected, a compare-match C signal is generated. However, comparison at the T2 state in the write cycle to TCORC and at the input capture cycle of TICR is disabled. TCORC is initialized to H'FF. 10.3.7 Input Capture Registers R and F (TICRR, TICRF, TICRR_A and TICRF_A) TICRR and TICRF are 8-bit read-only registers.
10.3.9 Timer Connection Register I (TCONRI) TCONRI controls the input capture function. Bit Bit Name Initial Value R/W Description 7 to 5 — All 0 R/W Reserved The initial value should not be changed. 4 ICST 0 R/W Input Capture Start Bit TMR_X has input capture registers (TICRR and TICRF). TICRR and TICRF can measure the width of a pulse by means of a single capture operation under the control of the ICST bit.
Table 10.4 Registers Accessible by TMR_X/TMR_Y TMRX/Y 0 1 H'FFF0 H'FFF1 H'FFF2 H'FFF3 H'FFF4 H'FFF5 H'FFF6 H'FFF7 TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TMR_X TCR_X TCSR_X TICRR TICRF TCNT TCORC TCORA_X TCORB_X TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TMR_Y TCR_Y TCSR_Y TCORA_Y TCORB_Y TCNT_Y TISR 10.3.11 Timer XY Control Register (TCRXY) TCRXY selects the TMR_X and TMR_Y output pins and internal clock.
10.3.12 Timer AB Control Register (TCRAB) TCRAB selects the internal clock or controls the input capture function in the TMR_A and TMR_B. Bit Bit Name Initial Value R/W Description 7, 6 All 0 R/W 5 CKSA 0 R/W Reserved The initial value should not be modified. TMR_A Clock Select For details about selection, see the clock conditions in table 10.3. 4 CKSB 0 R/W TMR_B Clock Select For details about selection, see the clock conditions in table 10.3.
10.4 Operation 10.4.1 Pulse Output Figure 10.4 shows an example for outputting an arbitrary duty pulse. 1. Clear the CCLR1 bit in TCR to 0 so that TCNT is cleared according to the compare match of TCORA, and then set the CCLR0 bit to 1. 2. Set the OS3 to OS0 bits in TCSR to B'0110 so that 1 is output according to the compare match of TCORA and 0 is output according to the compare match of TCORB.
10.5 Operation Timing 10.5.1 TCNT Count Timing Figure 10.5 shows the TCNT count timing with an internal clock source. Figure 10.6 shows the TCNT count timing with an external clock source. The pulse width of the external clock signal must be at least 1.5 system clocks (φ) for a single edge and at least 2.5 system clocks (φ) for both edges. The counter will not increment correctly if the pulse width is less than these values. φ Internal clock TCNT input clock TCNT N–1 N N+1 Figure 10.
φ TCNT N TCOR N N+1 Compare-match signal CMF Figure 10.7 Timing of CMF Setting at Compare-Match 10.5.3 Timing of Timer Output at Compare-Match When a compare-match signal occurs, the timer output changes as specified by the OS3 to OS0 bits in TCSR. Figure 10.8 shows the timing of timer output when the output is set to toggle by a compare-match A signal. φ Compare-match A signal Timer output pin Figure 10.8 Timing of Toggled Timer Output by Compare-Match A Signal 10.5.
10.5.5 TCNT External Reset Timing TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure 10.10 shows the timing of clearing the counter by an external reset input. φ External reset input pin Clear signal N–1 TCNT H'00 N Figure 10.10 Timing of Counter Clear by External Reset Input 10.5.
10.6 TMR_0 and TMR_1 Cascaded Connection If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, the 16-bit count mode or compare-match count mode is available. 10.6.1 16-Bit Count Mode When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with TMR_0 occupying the upper 8 bits and TMR_1 occupying the lower 8 bits.
10.7 TMR_Y and TMR_X Cascaded Connection If bits CKS2 to CKS0 in either TCR_Y or TCR_X are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, 16-bit count mode or compare-match count mode can be selected by the settings of the CKSX and CKSY bits in TCRXY. 10.7.
10.7.3 Input Capture Operation TMR_X has input capture registers (TICRR and TICRF). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIX (TMR_X input capture input signal) is detected after its rising edge has been detected, the value of TCNT_X at that time is transferred to both TICRR and TICRF. 10.
10.8.3 Input Capture Operation TMR_A has input capture registers (TICRR_A and TICRF_A). A narrow pulse width can be measured with TICRR and TICRF, using a single capture. If the falling edge of TMRIA (TMR_A input capture input signal) is detected after its rising edge has been detected, the value of TCNT_A at that time is transferred to both TICRR and TICRF. Input Capture Signal Input Timing: Figure 10.12 shows the timing of the input capture operation.
Selection of Input Capture Signal Input: TMRIX (input capture input signal of TMR_X) is selected according to the setting of the ICST bit in TCONRI. The input capture signal selection is shown in table 10.5. Table 10.5 Input Capture Signal Selection TCONRI Bit 4 ICST Description 0 1 Input capture function not used TMIX pin input selection TMRIA (input capture input signal of TMR_A) is selected according to the setting of the ICST but in TCRAB. The input capture signal selection is shown in table 10.6.
10.9 Interrupt Sources TMR_0, TMR_1, and TMR_Y can generate three types of interrupts: CMIA, CMIB, and OVI. TMR_X can generate an ICIX interrupt. TMR_A can generate four types of interrupts, CMIA, CMIB, OVI and ICIA. Table 10.7 shows the interrupt sources and priorities. Each interrupt source can be enabled or disabled independently by interrupt enable bits in TCR or TCSR. Independent signals are sent to the interrupt controller for each interrupt. Table 10.
10.10 Usage Notes 10.10.1 Conflict between TCNT Write and Counter Clear If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure 10.14, clearing takes priority and the counter write is not performed. TCNT write cycle by CPU T2 T1 T 3* φ Address TCNT address Internal write signal Counter clear signal N TCNT H'00 Note: * TMR_A, TMR_B Figure 10.14 Conflict between TCNT Write and Clear 10.10.
10.10.3 Conflict between TCOR Write and Compare-Match If a compare-match occurs during the T2 state of a TCOR write cycle as shown in figure 10.16, the TCOR write takes priority and the compare-match signal is disabled. With TMR_X, and TMR_A, a TICR input capture conflicts with a compare-match in the same way as with a write to TCORC. In this case also, the input capture takes priority and the compare-match signal is disabled.
10.10.5 Switching of Internal Clocks and TCNT Operation TCNT may increment erroneously when the internal clock is switched over. Table 10.9 shows the relationship between the timing at which the internal clock is switched (by writing to the CKS1 and CKS0 bits) and the TCNT operation. When the TCNT clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in table 10.
No. 3 Timing of Switchover by Means of CKS1 and CKS0 Bits Clock switching from high to low level∗3 TCNT Clock Operation Clock before switchover Clock after switchover *4 TCNT clock TCNT N N+1 N+2 CKS bit rewrite 4 Clock switching from high to high level Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit rewrite Notes: 1. 2. 3. 4. Includes switching from low to stop, and from stop to low. Includes switching from stop to high.
Rev. 1.
Section 11 Watchdog Timer (WDT) This LSI incorporates two watchdog timer channels (WDT_0 and WDT_1). The watchdog timer can generate an internal reset signal or an internal NMI interrupt signal if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. Simultaneously, it can output an overflow signal (RESO) externally. When this watchdog function is not needed, the WDT can be used as an interval timer.
Internal NMI (Interrupt request signal*2) RESO signal*1 Interrupt control Overflow Clock Clock selection Reset control Internal reset signal*1 TCNT_0 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/131072 Internal clock Internal bus WOVI0 (Interrupt request signal) TCSR_0 Bus interface Module bus WDT_0 Internal NMI (Interrupt request signal*2) RESO signal*1 Interrupt control Overflow Clock Clock selection Reset control Internal reset signal*1 φ/2 φ/64 φ/128 φ/512 φ/2048 φ/8192 φ/32768 φ/
11.2 Input/Output Pins The WDT has the pins listed in table 11.1. Table 11.1 Pin Configuration Name Symbol I/O Function Reset output pin RESO Output Outputs the counter overflow signal in watchdog timer mode Input Inputs the clock pulses to the WDT_1 prescaler counter External sub-clock input pin EXCL 11.3 Register Descriptions The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have to be written to in a method different from normal registers.
11.3.2 Timer Control/Status Register (TCSR) TCSR selects the clock source to be input to TCNT, and the timer mode. • TCSR_0 Bit 7 Bit Name OVF Initial Value 0 R/W Description 1 R/(W)* Overflow Flag Indicates that TCNT has overflowed (changes from H'FF to H'00). [Setting condition] When TCNT overflows (changes from H'FF to H'00) However, when internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset.
Bit Bit Name Initial Value R/W Description 2 CKS2 0 R/W Clock Select 2 to 0 1 CKS1 0 R/W 0 CKS0 0 R/W Selects the clock source to be input to. The overflow frequency for φ = 10 MHz is enclosed in parentheses. 000: φ/2 (frequency: 51.2 µs) 001: φ/64 (frequency: 1.64 ms) 010: φ/128 (frequency: 3.28 ms) 011: φ/512 (frequency: 13.1 ms) 100: φ/2048 (frequency: 52.4 ms) 101: φ/8192 (frequency: 209.7 ms) 110: φ/32768 (frequency: 0.84 s) 111: φ/131072 (frequency: 3.36 s) Notes: 1.
Bit Bit Name Initial Value R/W Description 4 PSS 0 R/W Prescaler Select Selects the clock source to be input to TCNT. 0: Counts the divided cycle of φ–based prescaler (PSM) 1: Counts the divided cycle of φSUB–based prescaler (PSS) 3 RST/NMI 0 R/W Reset or NMI Selects to request an internal reset or an NMI interrupt when TCNT has overflowed.
11.4 Operation 11.4.1 Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT bit and the TME bit in TCSR to 1. While the WDT is used as a watchdog timer, if TCNT overflows without being rewritten because of a system malfunction or another error, an internal reset or NMI interrupt request is generated. TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
TCNT value Overflow H'FF Time H'00 WT/IT = 1 TME = 1 Write H'00 to TCNT OVF = 1* RESO and internal reset signals generated WT/IT = 1 Write H'00 to TME = 1 TCNT RESO signal 132 system clocks Internal reset signal 518 system clocks [Legend] WT/IT: Timer mode select bit TME: Timer enable bit Overflow flag OVF: Note: * After the OVF bit becomes 1, it is cleared to 0 by an internal reset. The XRST bit is also cleared to 0. Figure 11.2 Watchdog Timer Mode (RST/NMI = 1) Operation Rev. 1.
11.4.2 Interval Timer Mode When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows, as shown in figure 11.3. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit of TCSR is set to 1. The timing is shown figure 11.4.
RESO Signal Output Timing 11.4.3 When TCNT overflows in watchdog timer mode, the OVF bit in TCSR is set to 1. When the RST/NMI bit is 1 here, the internal reset signal is generated for the entire LSI. At the same time, the low level signal is output from the RESO pin. The timing is shown in figure 11.5. φ TCNT H'FF H'00 Overflow signal (internal signal) OVF 132 states RESO signal Internal reset signal 518 states Figure 11.5 Output Timing of RESO signal 11.
11.6 Usage Notes 11.6.1 Notes on Register Access The watchdog timer's registers, TCNT and TCSR differ from other registers in being more difficult to write to. The procedures for writing to and reading from these registers are given below. Writing to TCNT and TCSR (Example of WDT_0): These registers must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. TCNT and TCSR both have the same write address.
11.6.2 Conflict between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 11.7 shows this operation. TCNT write cycle T1 T2 φ Address Internal write signal TCNT input clock TCNT M N Counter write data Figure 11.7 Conflict between TCNT Write and Increment 11.6.
11.6.5 System Reset by RESO Signal Inputting the RESO output signal to the RESO pin of this LSI prevents the LSI from being initialized correctly; the RESO signal must not be logically connected to the RES pin of the LSI. To reset the entire system by the RESO signal, use the circuit as shown in figure 11.8. This LSI Reset input Reset signal for entire system RES RESO Figure 11.8 Sample Circuit for Resetting System by RESO Signal 11.6.
Rev. 1.
Section 12 Serial Communication Interface (SCI) This LSI has a serial communication interface (SCI). The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA).
RDR SCMR TDR BRR SSR φ SCR ExRxD*/RxD RSR TSR Baud rate generator SMR φ/4 φ/16 Transmission/ reception control ExTxD*/TxD Parity generation φ/64 Clock Parity check External clock ExSCK*/SCK [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register TEI TXI RXI ERI SCR: SSR: SCMR: BRR: Serial control register Serial status register Smart card mode register Bit rate register Note: * The program develo
12.3 Register Descriptions The SCI has the following registers. • • • • • • • • • • Receive shift register (RSR) Receive data register (RDR) Transmit data register (TDR) Transmit shift register (TSR) Serial mode register (SMR) Serial control register (SCR) Serial status register (SSR) Serial interface mode register (SCMR) Bit rate register (BRR) Serial pin select register (SPSR)* Note: * The program development tool (emulator) does not support this function. 12.3.
12.3.4 Transmit Shift Register (TSR) TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 12.3.5 Serial Mode Register (SMR) SMR is used to set the SCI's serial transfer format and select the on-chip baud rate generator clock source.
Bit Bit Name Initial Value R/W Description 2 MP 0 R/W Multiprocessor Mode (enabled only in asynchronous mode) When this bit is set to 1, the multiprocessor communication function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode. 1 CKS1 0 R/W Clock Select 1,0 0 CKS0 0 R/W These bits select the clock source for the on-chip baud rate generator.
Bit Bit Name Initial Value R/W Description 3 MPIE 0 R/W Multiprocessor Interrupt Enable (enabled only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, refer to section 12.
12.3.7 Serial Status Register (SSR) SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Bit Bit Name Initial Value R/W Description 7 TDRE 1 R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data.
Bit Bit Name Initial Value R/W Description 3 PER 0 R/(W)* Parity Error [Setting condition] • When a parity error is detected during reception [Clearing condition] • 2 TEND 1 R When 0 is written to PER after reading PER = 1 Transmit End [Setting conditions] • When the TE bit in SCR is 0 • When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing conditions] • 1 MPB 0 R When 0 is written to TDRE after reading TDRE = 1 Multiprocessor Bit MPB stores t
12.3.8 Serial Interface Mode Register (SCMR) SCMR selects SCI functions and its format. Bit Bit Name Initial Value R/W Description 7 to 4 — All 1 R Reserved These bits are always read as 1 and cannot be modified. 3 SDIR 0 R/W Data Transfer Direction Selects the serial/parallel conversion format. 0: TDR contents are transmitted with LSB-first. Receive data is stored as LSB first in RDR. 1: TDR contents are transmitted with MSB-first. Receive data is stored as MSB first in RDR.
12.3.9 Bit Rate Register (BRR) BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 12.2 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 12.
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1) Operating Frequency φ (MHz) 4 4.9152 5 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) 110 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 207 0.16 1 255 0.00 2 64 0.16 300 1 103 0.16 1 127 0.00 1 129 0.16 600 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 25 0.16 0 31 0.00 0 32 –1.
Table 12.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2) Operating Frequency φ (MHz) 6 6.144 7.3728 8 Bit Rate (bit/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 106 –0.44 2 108 0.08 2 130 –0.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.
Table 12.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bit/s) φ (MHz) Maximum Bit Rate (bit/s) n N n N 4 125000 0 0 9.8304 307200 0 0 4.9152 153600 0 0 10 312500 0 0 5 6 156250 0 0 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 Table 12.
Table 12.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Operating Frequency φ (MHz) 4 Bit Rate (bit/s) n 8 N n 10 N n N 110 — — 250 2 249 3 124 — — 500 2 124 2 249 — — 1k 1 249 2 124 — — 2.5k 1 99 1 199 1 249 5k 0 199 1 99 1 124 10k 0 99 0 199 0 249 25k 0 39 0 79 0 99 50k 0 19 0 39 0 49 100k 0 9 0 19 0 24 250k 0 3 0 7 0 9 500k 0 1* 0 3 0 4 1M 0 0 0 1 0 0* 2.5M 5M [Legend] Blank: Cannot be set.
12.3.10 Serial Pin Select Register (SPSR) SPSR selects the serial I/O pins. SPSR should be set before initialization. Do not set during communication. Bit Bit Name Initial Value R/W Description 7 SPS1 0 R/W Serial Port Select Selects the serial I/O pins. 0: P86/SCK1, P85/RxD1, P84/TxD1 1: P52/ExSCK1, P51/ExRxD1, P50/ExTxD1 6 to 0 — All 0 R/W Reserved The initial value should not be changed. Note: The program development tool (emulator) does not support SPSR. 12.
12.4.1 Data Transfer Format Table 12.8 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, refer to section 12.5, Multiprocessor Communication Function. Table 12.
12.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Since receive data is latched internally at the rising edge of the 8th pulse of the basic clock, data is latched at the middle of each bit, as shown in figure 12.3.
12.4.3 Clock Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin.
12.4.4 SCI Initialization (Asynchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as shown in figure 12.5. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
12.4.5 Data Transmission (Asynchronous Mode) Figure 12.6 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
[1] Initialization [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
12.4.6 Serial Data Reception (Asynchronous Mode) Figure 12.8 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, receives receive data in RSR, and checks the parity bit and stop bit. 2.
Table 12.9 SSR Status Flags and Receive Data Handling SSR Status Flag RDRF* ORER FER PER Receive Data Receive Error Type 1 0 0 1 1 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error Note: * The RDRF flag retains the state it had before data reception.
[3] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Break? Yes No Framing error processing No Clear RE bit in SCR to 0 PER = 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 12.9 Sample Serial Reception Flowchart (2) Rev. 1.
12.5 Multiprocessor Communication Function Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code.
12.5.1 Multiprocessor Serial Data Transmission Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
12.5.2 Multiprocessor Serial Data Reception Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 12.12 shows an example of SCI operation for multiprocessor format reception.
Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID. If the data is not this station’s ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station’s ID, clear the RDRF flag to 0.
[5] Error processing No ORER = 1 Yes Overrun error processing No FER = 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 12.13 Sample Multiprocessor Serial Reception Flowchart (2) Rev. 1.
12.6 Operation in Clocked Synchronous Mode Figure 12.14 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock.
12.6.2 SCI Initialization (Clocked Synchronous Mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 12.15. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag in SSR is set to 1.
12.6.3 Serial Data Transmission (Clocked Synchronous Mode) Figure 12.16 shows an example of SCI operation for transmission in clocked synchronous mode. In serial transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission.
Initialization [1] Start transmission Read TDRE flag in SSR TDRE = 1 [2] No [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
12.6.4 Serial Data Reception (Clocked Synchronous Mode) Figure 12.18 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2.
[1] Initialization Start reception [2] Read ORER flag in SSR Yes ORER = 1 No No No [3] Error processing [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1.
Initialization [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations.
12.7 Interrupt Sources Table 12.10 shows the interrupt sources in serial communication interface. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated.
12.8 12.8.1 Usage Notes Module Stop Mode Setting SCI operation can be disabled or enabled using the module stop control register. The initial setting is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For details, refer to section 20, Power-Down Modes. 12.8.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly.
12.8.6 SCI Operations during Mode Transitions Transmission: Before making a transition to module stop, software standby, or sub-sleep mode, stop all transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins during each mode depend on the port settings, and the pins output a high-level signal after mode cancellation. If a transition is made during data transmission, the data being transmitted will be undefined.
Transmission No All data transmitted? [1] [1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting TE to 1, reading SSR, writing to TDR, and clearing TDRE to 0 after mode cancellation. Yes Read TEND flag in SSR No TEND = 1 [2] Also clear TIE and TEIE to 0 when they are 1. Yes TE = 0 [3] Module stop, watch, sub-active, and sub-sleep modes are included. [2] [3] Make transition to software standby mode etc. Cancel software standby mode etc.
Transmission start Transmission end Transition to Software standby software standby mode cancelled mode TE bit SCK output pin TxD output pin Port input/output Port input/output Marking output Last TxD bit retained SCI TxD output Port Port input/output Port High output* SCI TxD output Note: * Initialized in software standby mode Figure 12.
12.8.7 Switching from SCK Pins to Port Pins When SCK pins are switched to port pins after transmission has completed, pins are enabled for port output after outputting a low pulse of half a cycle as shown in figure 12.25. Low pulse of half a cycle SCK/Port 4. Low pulse output 1. Transmission end Data Bit 6 Bit 7 2. TE = 0 TE 3. C/A = 0 C/A CKE1 CKE0 Figure 12.
Section 13 I2C Bus Interface (IIC) This LSI has a two-channel I2C bus interface. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. 13.
• Selectable input/output pins* Pins, PG4/ExSDAA, PG5/ExSCLA, PG6/ExSDAB, and PG7/ExSCLB, are selectable for the I2C bus input/output pin in each channel. Note: * The program development tool (emulator) does not support this function. Figure 13.1 shows a block diagram of the I2C bus interface. Figure 13.2 shows an example of I/O pin connections to external circuits.
VCC VDD VCC SCL SCL SDA SDA SCL in SDA out (Master) This LSI SCL in SCL in SCL out SCL out SDA in SDA in SDA out SDA out (Slave 1) SCL SDA SDA in SCL SDA SCL out (Slave 2) Figure 13.2 I2C Bus Interface Connections (Example: This LSI as Master) Rev. 1.
13.2 Input/Output Pins Table 13.1 summarizes the input/output pins used by the I2C bus interface. The serial clock I/O pin for each channel can be selected from the three pins*. The serial data I/O pin for each channel can be selected form the three pins*. Do not set multiple pins as the serial clock I/O pin or serial data I/O pin for a single channel. Note: * The program development tool (emulator) does not support this function. Table 13.
13.3 Register Descriptions The I2C bus interface has the following registers. Registers ICDR and SARX and registers ICMR and SAR are allocated to the same addresses. Accessible registers differ depending on the ICE bit in ICCR. When the ICE bit is cleared to 0, SAR and SARX can be accessed, and when the ICE bit is set to 1, ICMR and ICDR can be accessed. For details on the serial timer control register, see section 3.2.3, Serial Timer Control Register (STCR).
13.3.1 I2C Bus Data Register (ICDR) ICDR is an 8-bit readable/writable register that is used as a transmit data register when transmitting and a receive data register when receiving. ICDR is internally divided into a shift register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). Data transfers among these three registers are performed automatically in accordance with changes in the bus state, and they affect the status of internal flags such as ICDRE and ICDRF.
13.3.2 Slave Address Register (SAR) SAR sets the slave address and selects the communication format. If the LSI is in slave mode with the I2C bus format selected, when the FS bit is set to 0 and the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SAR can be accessed only when the ICE bit in ICCR is cleared to 0.
13.3.3 Second Slave Address Register (SARX) SARX sets the second slave address and selects the communication format. If the LSI is in slave mode with the I2C bus format selected, when the FSX bit is set to 0 and the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device specified by the master device. SARX can be accessed only when the ICE bit in ICCR is cleared to 0.
Table 13.
13.3.4 I2C Bus Mode Register (ICMR) ICMR sets the communication format and transfer rate. It can only be accessed when the ICE bit in ICCR is set to 1. Bit Bit Name Initial Value R/W Description 7 MLS 0 R/W MSB-First/LSB-First Select 0: MSB-first 1: LSB-first 2 Set this bit to 0 when the I C bus format is used. 6 WAIT 0 R/W Wait Insertion Bit 2 This bit is valid only in master mode with the I C bus format. 0: Data and the acknowledge bit are transferred consecutively with no wait inserted.
Bit Bit Name Initial Value R/W Description 2 BC2 0 R/W Bit Counter 2 to 0 1 BC1 0 R/W 0 BC0 0 R/W These bits specify the number of bits to be transferred next. Bit BC2 to BC0 settings should be made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than 000, the setting should be made while the SCL line is low. The bit counter is initialized to 000 when a start condition is detected. The value returns to 000 at the end of a data transfer.
Table 13.3 I2C Transfer Rate STCR ICMR Bits 5 and 6 Bit 5 Bit 4 Bit 3 IICX CKS2 CKS1 CKS0 Clock φ = 5 MHz φ = 8 MHz φ = 10 MHz 0 0 0 0 φ/28 179 kHz 286 kHz 357 kHz 0 0 0 1 φ/40 125 kHz 200 kHz 250 kHz 0 0 1 0 φ/48 104 kHz 167 kHz 208 kHz 0 0 1 1 φ/64 78.1 kHz 125 kHz 156 kHz 0 1 0 0 φ/80 62.5 kHz 100 kHz 125 kHz 0 1 0 1 φ/100 50.0 kHz 80.0 kHz 100 kHz 0 1 1 0 φ/112 44.6 kHz 71.4 kHz 89.3 kHz 0 1 1 1 φ/128 39.1 kHz 62.5 kHz 78.
13.3.5 I2C Bus Control Register (ICCR) ICCR controls the I2C bus interface and performs interrupt flag confirmation. Bit Bit Name Initial Value R/W Description 7 ICE 0 R/W I2C Bus Interface Enable 2 2 0: I C bus interface modules are stopped and I C bus interface module internal state is initialized. SAR and SARX can be accessed. 2 1: I C bus interface modules can perform transfer operation, and the ports function as the SCL and SDA input/output pins. ICMR and ICDR can be accessed.
Bit Bit Name Initial Value R/W Description 5 MST 0 R/W [MST clearing conditions] 4 TRS 0 1. When 0 is written by software 2. When lost in bus contention in I2C bus format master mode [MST setting conditions] 1. When 1 is written by software (for MST clearing condition 1) 2. When 1 is written in MST after reading MST = 0 (for MST clearing condition 2) [TRS clearing conditions] 1. When 0 is written by software (except for TRS setting condition 3) 2.
Bit Initial Bit Name Value R/W Description 2 BBSY 0 R/W* Bus Busy 0 SCP 1 W Start Condition/Stop Condition Prohibit In master mode: • Writing 0 in BBSY and 0 in SCP: A stop condition is issued • Writing 1 in BBSY and 0 in SCP: A start condition and a restart condition are issued In slave mode: • Writing to the BBSY flag is disabled. [BBSY setting condition] When the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued.
Bit Bit Name Initial Value R/W Description 1 IRIC 0 R/(W)* I2C Bus Interface Interrupt Request Flag 2 Indicates that the I C bus interface has issued an interrupt request to the CPU. IRIC is set at different times depending on the FS bit in SAR, the FSX bit in SARX, and the WAIT bit in ICMR. See section 13.4.7, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR.
Bit Bit Name Initial Value R/W Description 1 IRIC 0 R/(W)* Clocked synchronous serial format mode: • At the end of data transfer (rise of the 8th transmit/receive) • When a start condition is detected When the ICDRE or ICDRF flag is set to 1 in any operating mode: • When a start condition is detected in transmit mode (when a start condition is detected in transmit mode and the ICDRE flag is set to 1) • When data is transferred among ICDR and buffer (when data is transferred from ICDRT to ICD
Table 13.
Table 13.
Table 13.
13.3.6 I2C Bus Status Register (ICSR) ICSR consists of status flags. Also see tables 13.4 and 13.5. Bit Bit Name Initial Value R/W Description 7 ESTP 0 R/(W)* Error Stop Condition Detection Flag This bit is valid in I2C bus format slave mode. [Setting condition] When a stop condition is detected during frame transfer.
Bit Bit Name Initial Value R/W 4 AASX 0 R/(W)* Description Second Slave Address Recognition Flag In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in SARX.
Bit Bit Name Initial Value R/W Description 2 AAS 0 R/(W)* Slave Address Recognition Flag In I2C bus format slave receive mode, this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the general call address (H'00) is detected.
Bit Initial Bit Name Value R/W Description 0 ACKB R/W Acknowledge Bit 0 Stores acknowledge data.
13.3.7 DDC Switch Register (DDCSWR) DDCSWR controls IIC internal latch clearance. Bit Bit Name Initial Value R/W Description 7 to 5 — All 0 R/W Reserved The initial value should not be changed. 4 — 0 R Reserved 3 CLR3 1 W* IIC Clear 3 to 0 2 CLR2 1 W* 1 CLR1 1 W* Controls initialization of the internal state of IIC_0 and IIC_1.
13.3.8 I2C Bus Extended Control Register (ICXR) ICXR enables or disables the I2C bus interface interrupt generation and continuous receive operation, and indicates the status of receive/transmit operations. Bit Bit Name Initial Value R/W Description 7 STOPIM 0 R/W Stop Condition Interrupt Source Mask Enables or disables the interrupt generation when the stop condition is detected in slave mode.
Bit Bit Name Initial Value R/W Description 5 ICDRF 0 R Receive Data Read Request Flag Indicates the ICDR (ICDRR) status in receive mode. 0: Indicates that the data has been already read from ICDR (ICDRR) or ICDR is initialized. 1: Indicates that data has been received successfully and transferred from ICDRS to ICDRR, and the data is ready to be read out. [Setting conditions] • When data is received successfully and transferred from ICDRS to ICDRR.
Bit Initial Bit Name Value R/W 4 ICDRE R 0 Description Transmit Data Write Request Flag Indicates the ICDR (ICDRT) status in transmit mode. 0: Indicates that the data has been already written to ICDR (ICDRT) or ICDR is initialized. 1: Indicates that data has been transferred from ICDRT to ICDRS and is being transmitted, or the start condition has been detected or transmission has been complete, thus allowing the next data to be written to.
Bit Bit Name Initial Value R/W Description 3 ALIE 0 R/W Arbitration Lost Interrupt Enable Enables or disables IRIC flag setting and interrupt generation when arbitration is lost. 0: Disables interrupt request when arbitration is lost. 1: Enables interrupt request when arbitration is lost. 2 ALSL 0 R/W Arbitration Lost Condition Select Selects the condition under which arbitration is lost.
13.3.9 Port G Control Register (PGCTL) PGCTL selects the input/output pin for IIC.
13.4 Operation The I2C bus interface has an I2C bus format and a serial format. 13.4.1 I2C Bus Data Format The I2C bus format is an addressing format with an acknowledge bit. This is shown in figure 13.3. The first frame following a start condition always consists of 9 bits. The serial format is a non-addressing format with no acknowledge bit. This is shown in figure 13.4. Figure 13.5 shows the I2C bus timing. The symbols used in figures 13.3 to 13.5 are explained in table 13.6.
SDA SCL S 1 to 7 8 9 SLA R/W A 1 to 7 DATA 8 9 A 1 to 7 DATA 8 9 A/A P Figure 13.5 I2C Bus Timing Table 13.6 I2C Bus Data Format Symbols Legend S Start condition. The master device drives SDA from high to low while SCL is high. SLA Slave address. The master device selects the slave device. R/W Indicates the direction of data transfer: from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0 A Acknowledge.
13.4.2 Initialization Initialize the IIC by the procedure shown in figure 13.6 before starting transmission/reception of data.
Start Initialize IIC [1] Initialization Read BBSY flag in ICCR [2] Test the status of the SCL and SDA lines. No BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCR [3] Select master transmit mode. Set BBSY =1 and SCP = 0 in ICCR [4] Start condition issuance Read IRIC flag in ICCR [5] Wait for a start condition generation No IRIC = 1? Yes Write transmit data in ICDR [6] Set transmit data for the first byte (slave address + R/W). (After writing to ICDR, clear IRIC flag continuously.
The transmission procedure and operations by which data is sequentially transmitted in synchronization with ICDR (ICDRT) write operations, are described below. 1. 2. 3. 4. Initialize the IIC as described in section 13.4.2, Initialization. Read the BBSY flag in ICCR to confirm that the bus is free. Set bits MST and TRS to 1 in ICCR to select master transmit mode. Write 1 to BBSY and 0 to SCP in ICCR. This changes SDA from high to low when SCL is high, and generates the start condition. 5.
12. Clear the IRIC flag to 0. Write 0 to ACKE in ICCR, to clear received ACKB contents to 0. Write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition.
Start condition issuance SCL (master output) 8 9 SDA Bit 0 (master output) Data 1 SDA (slave output) [7] 1 2 3 4 Bit 7 Bit 6 Bit 5 Bit 4 5 6 7 8 Bit 3 Bit 2 Bit 1 Bit 0 9 [10] Data 2 A A ICDRE IRIC IRTR ICDR User processing Data 1 [9] ICDR write Data 2 [9] IRIC clear [11] ACKB read [12] IRIC clear [12] Set BBSY = 1and SCP = 0 (Stop condition issuance) Figure 13.9 Example of Stop Condition Issuance Operation Timing in Master Transmit Mode (MLS = WAIT = 0) Rev. 1.
13.4.4 Master Receive Operation In I2C bus format master receive mode, the master device outputs the receive clock, receives data, and returns an acknowledge signal. The slave device transmits data. The master device transmits data containing the slave address and R/W (1: read) in the first frame following the start condition issuance in master transmit mode, selects the slave device, and then switches the mode for receive operation. Receive Operation Using the HNDS Function (HNDS = 1): Figure 13.
The reception procedure and operations using the HNDS function, by which the data reception process is provided in 1-byte units with SCL fixed low at each data reception, are described below. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode. Clear the ACKB bit in ICSR to 0 (acknowledge data setting). Set the HNDS bit in ICXR to 1. Clear the IRIC flag to 0 to determine the end of reception. Go to step [6] to halt reception operation if the first frame is the last receive data.
Master receive mode Master transmit mode SCL is fixed low until ICDR is read SCL is fixed low until ICDR is read SCL (master output) 9 1 2 3 4 5 6 7 8 SDA (slave output) A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 2 Bit 7 Bit 6 9 [3] Data 1 SDA (master output) Data 2 A IRIC IRTR ICDRF ICDRR Data 1 Undefined value User processing [1] TRS=0 clear [5] ICDR read (Data 1) [4] IRIC clear [2] IRIC read (Dummy read) [1] IRIC clear Figure 13.
Receive Operation Using the Wait Function: Figures 13.13 and 13.14 show the sample flowcharts for the operations in master receive mode (WAIT = 1). Master receive mode Set TRS = 0 in ICCR [1] Select receive mode. Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC flag in ICCR Set WAIT = 1 in ICMR [2] Start receiving. The first read is a dummy read.
Slave receive mode Set TRS = 0 in ICCR Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR [1] Select receive mode. Clear IRIC flag in ICCR Set WAIT = 0 in ICMR Read ICDR [2] Start receiving. The first read is a dummy read. Read IRIC flag in ICCR No IRIC = 1? [3] Wait for a receive wait (Set IRIC at the fall of the 8th clock) Yes Set ACKB = 1 in ICSR Set TRS = 1 in ICCR [7] Set acknowledge data for the last reception. [9] Set TRS for stop condition issuance Clear IRIC flag in ICCR [11] Clear IRIC flag.
The reception procedure and operations using the wait function (WAIT bit), by which data is sequentially received in synchronization with ICDR (ICDRR) read operations, are described below. The following describes the multiple-byte reception procedure. In single-byte reception, some steps of the following procedure are omitted. At this time, follow the procedure shown in figure 13.14. 1. Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode.
12. The IRIC flag is set to 1 in either of the following cases. At the fall of the 8th receive clock pulse for one frame SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag is cleared. At the rise of the 9th receive clock pulse for one frame The IRTR and ICDRF flags are set to 1, indicating that one frame of data has been received. The master device outputs the receive clock continuously to receive the next data. 13. Read the IRTR flag in ICSR.
[8] Wait for one clock pulse Stop condition generation SCL (master output) 8 9 SDA Bit 0 (slave output) Data 2 [3] SDA (master output) 9 1 2 3 4 5 6 7 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Data 3 [3] [12] [12] A A IRIC IRTR [4] IRTR=0 ICDR Data 1 User processing [13] IRTR=1 [13] IRTR=0 [4] IRTR=1 Data 2 [6] IRIC clear [11] IRIC clear [10] ICDR read (Data 2) [9] Set TRS=1 [7] Set ACKB=1 Data 3 [15] WAIT cleared to 0, IRIC clear [14] IRIC clear [17] Stop cond
Slave receive mode [1] Initialization. Select slave receive mode. Initialize IIC Set MST = 0 and TRS = 0 in ICCR Set ACKB = 0 in ICSR and HNDS = 1 in ICXR Read IRIC flag in ICCR ICDRF = 1? No [2] Read the receive data remaining unread.
The reception procedure and operations using the HNDS bit function, by which data reception process is provided in 1-byte unit with SCL being fixed low at every data reception, are described below. 1. Initialize the IIC as described in section 13.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS bit to 1 and the ACKB bit to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0.
Start condition generation SCL (Pin waveform) SCL (master output) SCL (slave output) SDA (master output) SDA (slave output) [7] SCL is fixed low until ICDR is read 1 2 3 4 5 6 7 8 9 1 2 1 2 3 4 5 6 7 8 9 1 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Slave address Bit 0 Bit 7 R/W Bit 6 Data 1 [6] A Interrupt request occurrence IRIC ICDRF Address+R/W ICDRS ICDRR Address+R/W Undefined value User processing [2] ICDR read [8] IRIC clear [10] ICDR read (dummy read)
Continuous Receive Operation: Figure 13.20 shows the sample flowchart for the operations in slave receive mode (HNDS = 0). Slave receive mode Set MST = 0 and TRS = 0 in ICCR [1] Select slave receive mode. Set ACKB = 0 in ICSR Set HNDS = 0 in ICXR Clear IRIC in ICCR ICDRF = 1? No [2] Read the receive data remaining unread.
The reception procedure and operations in slave receive are described below. 1. Initialize the IIC as described in section 13.4.2, Initialization. Clear the MST and TRS bits to 0 to set slave receive mode, and set the HNDS and ACKB bits to 0. Clear the IRIC flag in ICCR to 0 to see the end of reception. 2. Confirm that the ICDRF flag is 0. If the ICDRF flag is set to 1, read the ICDR and then clear the IRIC flag to 0. 3.
Start condition issuance SCL (master output) 1 2 3 4 Bit 7 Bit 6 Bit 5 SDA (master output) 5 6 Bit 4 Bit 3 7 8 9 1 3 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 Slave address 2 [6] R/W SDA (slave output) Data 1 A IRIC ICDRF ICDRS Address+R/W Data 1 [7] ICDRR Address+R/W User processing [8] IRIC clear [10] ICDR read Figure 13.
13.4.6 Slave Transmit Operation If the slave address matches to the address in the first frame (address reception frame) following the start condition detection when the 8th bit data (R/W) is 1 (read), the TRS bit in ICCR is automatically set to 1 and the mode changes to slave transmit mode. Figure 13.23 shows the sample flowchart for the operations in slave transmit mode.
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs the receive clock and returns an acknowledge signal. The transmission procedure and operations in slave transmit mode are described below. 1. Initialize slave receive mode and wait for slave address reception. 2. When the slave address matches in the first frame following detection of the start condition, the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal.
10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to 0.
13.4.7 IRIC Setting Timing and SCL Control The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is automatically held low after one frame has been transferred in synchronization with the internal clock. Figures 13.25 to 13.27 show the IRIC set timing and SCL control.
When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted) SCL SDA 8 9 1 2 3 8 A 1 2 3 IRIC User processing Clear IRIC Clear IRIC (a) Data transfer ends with ICDRE=0 at transmission, or ICDRF=0 at reception. SCL SDA 8 9 1 8 A 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) (b) Data transfer ends with ICDRE=1 at transmission, or ICDRF=1 at reception. Figure 13.26 IRIC Setting Timing and SCL Control (2) Rev. 1.
When FS = 1 and FSX = 1 (clocked synchronous serial format) SCL SDA 7 8 7 8 1 1 2 2 3 4 4 3 IRIC User processing Clear IRIC (a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception. SCL SDA 7 8 1 7 8 1 IRIC User processing Clear IRIC Write to ICDR (transmit) or read from ICDR (receive) Clear IRIC (b) Data transfer ends with ICDRE =1 at transmission, or ICDRF = 1 at reception. Figure 13.27 IRIC Setting Timing and SCL Control (3) Rev. 1.
13.4.8 Noise Canceller The logic levels at the SCL and SDA pins are routed through noise cancellers before being latched internally. Figure 13.28 shows a block diagram of the noise canceller. The noise canceller consists of two cascaded latches and a match detector. The SCL (or SDA) pin input signal is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
13.4.9 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication. Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in DDCSWR or clearing ICE bit. For details on the setting of bits CLR3 to CLR0, see section 13.3.7, DDC Switch Register (DDCSWR).
The value of the BBSY bit cannot be modified directly by this module clear function, but since the stop condition pin waveform is generated according to the state and release timing of the SCL and SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and flags may also have an effect. To prevent problems caused by these factors, the following procedure should be used when initializing the IIC state. 1.
13.6 Usage Notes 1. In master mode, if an instruction to generate a start condition is issued and then an instruction to generate a stop condition is issued before the start condition is output to the I2C bus, neither condition will be output correctly. To output the start condition followed by the stop condition, after issuing the instruction that generates the start condition, read DR in each I2C bus output pin, and check that SCL and SDA are both low.
5. The I2C bus interface specification for the SCL rise time tsr is 1000 ns or less (300 ns for highspeed mode). In master mode, the I2C bus interface monitors the SCL line and synchronizes one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds the time determined by the input clock of the I2C bus interface, the high period of SCL is extended. The SCL rise time is determined by the pull-up resistance and load capacitance of the SCL line.
Table 13.10 I2C Bus Timing (with Maximum Influence of tSr/tSf) Time Indication (at Maximum Transfer Rate) [ns] Item tcyc Indication tSCLHO 0.5 tSCLO (–tSr) tSCLLO tBUFO 0.5 tSCLO (–tSf) 0.5 tSCLO –1 tcyc (–tSr) I2C Bus tSr/tSf SpecifiInfluence cation (Max.) (Min.
7. Notes on ICDR read at end of master reception To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is high, and generates the stop condition. After this, receive data can be read by means of an ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR (ICDRR), and so it will not be possible to read the second byte of data.
8. Notes on start condition issuance for retransmission Figure 13.30 shows the timing of start condition issuance for retransmission, and the timing for subsequently writing data to ICDR, together with the corresponding flowchart. Write the transmit data to ICDR after the start condition for retransmission is issued and then the start condition is actually generated.
9. Note on when I2C bus interface stop condition instruction is issued In cases where the rise time of the 9th clock of SCL exceeds the stipulated value because of a large bus load capacity or where a slave device in which a wait can be inserted by driving the SCL pin low is used, the stop condition instruction should be issued after reading SCL after the rise of the 9th clock pulse and determining that it is low.
10. Note on IRIC flag clear when the wait function is used If the rise time of SCL exceeds the stipulated value or a slave device in which a wait can be inserted by driving the SCL pin low is used when the wait function is used in I2C bust interface master mode, the IRIC flag should be cleared after determining that the SCL is low, as described below.
11. Note on ICDR read and ICCR access in slave transmit mode In I2C bus interface slave transmit mode, do not read ICDR or do not read/write from/to ICCR during the time shaded in figure 13.33. However, such read and write operations cause no problem in interrupt handling processing that is generated in synchronization with the rising edge of the 9th clock pulse because the shaded time has passed before making the transition to interrupt handling.
12. Note on TRS bit setting in slave mode In I2C bus interface slave mode, if the TRS bit value in ICCR is set after detecting the rising edge of the 9th clock pulse or the stop condition before detecting the next rising edge on the SCL pin (the time indicated as (a) in figure 13.34), the bit value becomes valid immediately when it is set. However, if the TRS bit is set during the other time (the time indicated as (b) in figure 13.
13. Note on ICDR read in transmit mode and ICDR write in receive mode If ICDR is read in transmit mode (TRS = 1) or ICDR is written to in receive mode (TRS = 0), the SCL pin may not be held low in some cases after transmit/receive operation has been completed, thus inconveniently allowing clock pulses to be output on the SCL bus line before ICDR is accessed correctly. To access ICDR correctly, read ICDR after setting receive mode or write to ICDR after setting transmit mode. 14.
• Arbitration is lost • The AL flag in ICSR is set to 1 I2C bus interface (Master transmit mode) S SLA R/W A DATA1 Transmit data match Transmit timing match Other device (Master transmit mode) S SLA R/W A Transmit data does not match A DATA2 DATA3 A Data contention I2C bus interface (Slave receive mode) S SLA R/W A • Receive address is ignored SLA R/W A DATA4 A • Automatically transferred to slave receive mode • Receive data is recognized as an address • When the receive data m
Rev. 1.
Section 14 Keyboard Buffer Controller This LSI has three on-chip keyboard buffer controller channels. The keyboard buffer controller is provided with functions conforming to the PS/2 interface specifications. Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line (KCLK), providing economical use of connectors, board surface area, etc. Figure 14.1 shows a block diagram of the keyboard buffer controller. 14.
Figure 14.2 shows how the keyboard buffer controller is connected. Vcc Vcc System side Keyboard side KCLK in KCLK in Clock KCLK out KCLK out KD in KD in Data KD out KD out Keyboard buffer controller (This LSI) I/F Figure 14.2 Keyboard Buffer Controller Connection 14.2 Input/Output Pins Table 14.1 lists the input/output pins used by the keyboard buffer controller. Table 14.
14.3 Register Descriptions The keyboard buffer controller has the following registers for each channel. • Keyboard control register H (KBCRH) • Keyboard control register L (KBCRL) • Keyboard data buffer register (KBBR) 14.3.1 Keyboard Control Register H (KBCRH) KBCRH indicates the operating status of the keyboard buffer controller. Bit Bit Name Initial Value R/W Description 7 KBIOE 0 R/W Keyboard In/Out Enable Selects whether or not the keyboard buffer controller is used.
Bit Bit Name Initial Value R/W Description 3 KBIE 0 R/W Keyboard Interrupt Enable Enables or disables interrupts from the keyboard buffer controller to the CPU. 0: Interrupt requests are disabled 1: Interrupt requests are enabled 2 KBF 0 R/(W)* Keyboard Buffer Register Full Indicates that data reception has been completed and the received data is in KBBR.
14.3.2 Keyboard Control Register L (KBCRL) KBCRL enables the receive counter count and controls the keyboard buffer controller pin output. Bit Initial Bit Name Value R/W Description 7 KBE 0 R/W 6 KCLKO 1 R/W 5 KDO 1 R/W 4 — 1 — Keyboard Enable Enables or disables loading of receive data into KBBR. 0: Loading of receive data into KBBR is disabled 1: Loading of receive data into KBBR is enabled Keyboard Clock Out Controls KBC clock I/O pin output.
14.3.3 Keyboard Data Buffer Register (KBBR) KBBR stores receive data. Its value is valid only when KBF = 1. Bit Initial Bit Name Value R/W Description 7 KB7 0 R Keyboard Data 7 to 0 6 KB6 0 R 8-bit read only data. 5 KB5 0 R 4 KB4 0 R 3 KB3 0 R Initialized to H'00 by a reset, in standby mode, watch mode, subactive mode, subsleep mode, and module stop mode, and when KBIOE is cleared to 0. 2 KB2 0 R 1 KB1 0 R 0 KB0 0 R Rev. 1.
14.4 Operation 14.4.1 Receive Operation In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and inputs on this LSI chip (system) side. KD receives a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A sample receive processing flowchart is shown in figure 14.3, and the receive timing in figure 14.4. Start [1] Set the KBIOE bit to 1 in KBCRL.
Flag cleared Receive processing/ error handling KCLK (pin state) 1 KD (pin state) Start bit 2 9 3 0 1 7 10 11 Parity bit Stop bit KCLK (input) KCLK (output) Automatic I/O inhibit KB7 to KB0 Previous data KB0 KB1 Receive data PER KBS KBF [1] [2] [3] [4] [5] [6] Figure 14.4 Receive Timing 14.4.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side.
Start Set KBIOE bit [1] [1] Set the KBE bit to 1 in KBCRH. Read KBCRH [2] [2] Read KBCRH, and if the KCLKI and KDI bits are both 1, write 0 in the KCLKO bit (set I/O inhibit). KCLKI and KDI bits both 1? No [3] Write 0 in the KBE bit (prohibit KBBR receive operation). Yes Set I/O inhibit (KCLKO = 0) KBE = 0 (KBBR reception prohibited) KDO remains at 1 [3] [6] Read KBCRH, and when KCLKI = 0, set the transmit data in the KDO bit (LSBfirst). Next, set the parity bit and stop bit in the KDO bit.
1 Read KBCRH No KCLKI = 0? 2 Yes [7] No KDI = 0? Keyboard side in data transmission state. Execute receive abort processing. * Yes [8] Read KBCRH Error handling No KCLK = 1? Yes Transmit end state (KCLK = high, KD = high) To receive operation or transmit operation Note: * To switch to reception after transmission, set KBE to 1 (KBBR receive enable) while KCLKI is low. Figure 14.
14.4.3 Receive Abort This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard side) in the event of a protocol error, etc. In this case, the system holds the clock low. During reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is an abort request from the system, and data transmission from the keyboard is aborted.
Processing 1 [1] On the system side, drive the KCLK pin low, setting the I/O inhibit state. [1] Receive operation ends normally Receive data processing Clear KBF flag (KCLK = High) Transmit enabled state. If there is transmit data, the data is transmitted. Figure 14.7 Sample Receive Abort Processing Flowchart (2) Keyboard side monitors clock during receive operation (transmit operation as seen from keyboard), and aborts receive operation during this period.
14.4.4 KCLKI and KDI Read Timing Figure 14.9 shows the KCLKI and KDI read timing. T1 T2 φ* Internal read signal KCLK, KD (pin state) KCLKI, KDI (register) Internal data bus (read data) Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 14.9 KCLKI and KDI Read Timing 14.4.5 KCLKO and KDO Write Timing Figure 14.10 shows the KLCKO and KDO write timing and the KCLK and KD pin states.
14.4.6 KBF Setting Timing and KCLK Control Figure 14.11 shows the KBF setting timing and the KCLK pin states. φ* KCLK (pin) 11th fall Internal KCLK Falling edge signal RXCR3 to RXCR0 B'1010 B'0000 KBF KCLK (output) Note: * Automatic I/O inhibit The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 14.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing Rev. 1.
14.4.7 Receive Timing Figure 14.12 shows the receive timing. φ* KCLK (pin) KD (pin) Internal KCLK (KCLKI) Falling edge signal RXCR3 to RXCR0 N N+1 N+2 Internal KD (KDI) KBBR7 to KBBR0 Note: * The φ clock shown here is scaled by 1/N in medium-speed mode when the operating mode is active mode. Figure 14.12 Receive Counter and KBBR Data Load Timing Rev. 1.
14.4.8 KCLK Fall Interrupt Operation In this device, clearing the KBFSEL bit to 0 in KBCRH enables the KBF bit in KBCRL to be used as a flag for the interrupt generated by the fall of KCLK input. Figure 14.13 shows the setting method and an example of operation.
14.5 Usage Notes 14.5.1 KBIOE Setting and KCLK Falling Edge Detection When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1. Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit operates and the KCLK falling edge is detected. If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 14.14 shows the timing of KBIOE setting and KCLK falling edge detection.
14.5.2 Module Stop Mode Setting Keyboard buffer controller operation can be enabled or disabled using the module stop control register. The initial setting is for keyboard buffer controller operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 20, Power-Down Modes. Rev. 1.
Section 15 Host Interface (LPC) This LSI has an on-chip LPC interface. The LPC performs serial transfer of cycle type, address, and data, synchronized with the 33 MHz PCI clock. It uses four signal lines for address/data, and one for host interrupt requests. This LPC module supports only I/O read cycle and I/O write cycle transfers. It is also provided with power-down functions that can control the PCI clock and shut down the host interface. 15.
Figure 15.1 shows a block diagram of the LPC.
15.2 Input/Output Pins Table 15.1 lists the input and output pins of the LPC module. Table 15.
15.3 Register Descriptions The LPC has the following registers.
15.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1) HICR0 and HICR1 contain control bits that enable or disable host interface functions, control bits that determine pin output and the internal state of the host interface, and status flags that monitor the internal state of the host interface.
Bit Bit Name R/W Initial Value Slave Host Description 4 FGA20E 0 R/W — Fast A20 Gate Function Enable Enables or disables the fast A20 gate function. When the fast A20 gate is disabled, the normal A20 gate can be implemented by firmware operation of the P81 output. When the fast A20 gate function is enabled, the DDR bit for P81 must not be set to 1.
Bit Bit Name R/W Initial Value Slave Host Description 2 PMEE 0 R/W — 1 LSMIE 0 R/W — 0 LSCIE 0 R/W — PME output Enable Controls PME output in combination with the PMEB bit in HICR1. PME pin output is open-drain, and an external pull-up resistor is needed to pull the output up to VCC When the PME output function is used, the DDR bit for P80 must not be set to 1.
• HICR1 Bit Bit Name R/W Initial Value Slave Host Description 7 LPCBSY 0 R/W — LPC Busy Indicates that the host interface is processing a transfer cycle.
Bit Bit Name R/W Initial Value Slave Host Description 5 IRQBSY 0 R — SERIRQ Busy Indicates that the host interface's SERIRQ signal is engaged in transfer processing.
Bit Bit Name R/W Initial Value Slave Host Description 3 SDWNB 0 R/W — LPC Software Shutdown Bit Controls host interface shutdown. For details of the LPC shutdown function, and the scope of initialization by an LPC reset and an LPC shutdown, see section 15.4.4, Host Interface Shutdown Function (LPCPD).
15.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3) Bits 6 to 0 in HICR2 control interrupts from the host interface (LPC) module to the slave processor (this LSI). Bit 7 in HICR2 and HICR3 monitor host interface pin states. The pin states can be monitored regardless of the host interface operating state or the operating state of the functions that use pin multiplexing.
Bit 3 Bit Name IBFIE3 R/W Initial Value Slave Host 0 R/W — 2 IBFIE2 0 R/W — 1 IBFIE1 0 R/W — 0 ERRIE 0 R/W — Note: * Description IDR3 and TWR Receive Completion Interrupt Enable Enables or disables IBFI3 interrupt to the slave processor (this LSI).
15.3.3 LPC Channel 3 Address Register (LADR3) LADR3 comprises two 8-bit readable/writable registers that perform LPC channel-3 host address setting and control the operation of the bidirectional data registers. The contents of the address field in LADR3 must not be changed while channel 3 is operating (while LPC3E is set to 1).
Table 15.
15.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3) The ODR registers are 8-bit readable/writable registers for the slave processor (this LSI), and 8-bit read-only registers for the host processor. The registers selected from the host according to the I/O address are shown in the following table. For information on ODR3 selection, see section 15.3.3, LPC Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register is transferred to the host.
I/O Address Bits 15 to 4 Bit 3 Bit 2 Bit 1 Bit 0 Transfer Cycle Host Register Selection 0000 0000 0110 0 1 0 0 I/O read STR1 read 0000 0000 0110 0 1 1 0 I/O read STR2 read • STR1 Bit Bit Name R/W Initial Value Slave Host Description 7 6 5 4 3 DBU17 DBU16 DBU15 DBU14 C/D1 0 0 0 0 0 R/W R/W R/W R/W R R R R R R Defined by User The user can use these bits as necessary.
• STR2 R/W Bit Bit Name Initial Value Slave Host Description 7 DBU27 0 R/W R Defined by User 6 DBU26 0 R/W R The user can use these bits as necessary. 5 DBU25 0 R/W R 4 DBU24 0 R/W R 3 C/D2 0 R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command.
• STR3 (TWRE = 1 or SELSTR3 = 0) Bit Bit Name R/W Initial Value Slave Host Description 7 IBF3B 0 R 6 OBF3B 0 R/(W)* R 5 MWMF 0 R 4 SWMF 0 R/(W)* R Rev. 1.00, 05/04, page 384 of 544 R R Bidirectional Data Register Input Buffer Full Set to 1 when the host processor writes to TWR15. This is an internal interrupt source to the slave processor (this LSI). IBF3B is cleared to 0 when the slave processor reads TWR15.
Bit Bit Name R/W Initial Value Slave Host Description 3 C/D3 0 R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command. 0: Contents of data register (IDR) are data 1: Contents of data register (IDR) are a command 2 DBU32 0 R/W R Defined by User The user can use this bit as necessary. 1 IBF3A 0 R R Input Buffer Full Set to 1 when the host processor writes to IDR.
• STR3 (TWRE = 0 and SELSTR3 = 1) Bit R/W Initial Bit Name Value Slave Host Description 7 DBU37 0 R/W R Defined by User 6 DBU36 0 R/W R The user can use these bits as necessary. 5 DBU35 0 R/W R 4 DBU34 0 R/W R 3 C/D3 0 R R Command/Data When the host processor writes to an IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data or a command.
15.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1) The SIRQCR registers contain status bits that indicate the SERIRQ operating mode and bits that specify SERIRQ interrupt sources. • SIRQCR0 Bit R/W Initial Bit Name Value Slave Host Description 7 Q/C Quiet/Continuous Mode Flag 0 R — Indicates the mode specified by the host at the end of an SERIRQ transfer cycle (stop frame).
Bit Bit Name R/W Initial Value Slave Host Description 4 SMIE3B 0 R/W — Host SMI Interrupt Enable 3B Enables or disables a host SMI interrupt request when OBF3B is set by a TWR15 write.
R/W Bit Bit Name Initial Value Slave Hos t Description 2 SMIE2 0 — R/W Host SMI Interrupt Enable 2 Enables or disables a host SMI interrupt request when OBF2 is set by an ODR2 write.
Bit Bit Name R/W Initial Value Slave Host 0 IRQ1E1 0 R/W — Description Host IRQ1 Interrupt Enable 1 Enables or disables a host IRQ1 interrupt request when OBF1 is set by an ODR1 write.
Bit R/W Initial Bit Name Value Slave Host Description 6 IRQ10E3 0 Host IRQ10 Interrupt Enable 3 R/W — Enables or disables a host IRQ10 interrupt request when OBF3A is set by an ODR3 write.
Bit Bit Name R/W Initial Value Slave Host 4 IRQ6E3 0 R/W — Description Host IRQ6 Interrupt Enable 3 Enables or disables a host IRQ6 interrupt request when OBF3A is set by an ODR3 write.
Bit Bit Name R/W Initial Value Slave Host Description 2 IRQ10E2 0 R/W — Host IRQ10 Interrupt Enable 2 Enables or disables a host IRQ10 interrupt request when OBF2 is set by an ODR2 write.
Bit Bit Name R/W Initial Value Slave Host Description 0 IRQ6E2 0 R/W — Host IRQ6 Interrupt Enable 2 Enables or disables a host IRQ6 interrupt request when OBF2 is set by an ODR2 write.
15.3.9 Host Interface Select Register (HISEL) HISEL selects the function of bits 7 to 4 in STR3 and specifies the output of the host interrupt request signal of each frame. R/W Bit Bit Name Initial Value Slave Host Description 7 SELSTR3 0 W STR3 Register Function Select 3 Selects the function of bits 7 to 4 in STR3 in combination with the TWRE bit in LADR3L. See description on STR3 in section 15.3.7, Status Registers 1 to 3 (STR1 to STR3), for details.
15.4 Operation 15.4.1 Host Interface Activation The host interface is activated by setting one of bits LPC3E to LPC1E in HICR0 to 1 in singlechip mode. When the host interface is activated, the related I/O ports (ports 37 to 30, ports 83 and 82) function as dedicated host interface input/output pins. In addition, setting the FGA20E, PMEE, LSMIE, and LSCIE bits to 1 adds the related I/O ports (ports 81 and 80, ports B0 and B1) to the host interface's input/output pins.
15.4.2 LPC I/O Cycles There are ten kinds of LPC transfer cycle: memory read, memory write, I/O read, I/O write, DMA read, DMA write, bus master memory read, bus master memory write, bus master I/O read, and bus master I/O write. Of these, the chip's LPC supports only I/O read and I/O write cycles. An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state.
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 15.2 and 15.3. LCLK LFRAME Start LAD3–LAD0 ADDR TAR Sync Data TAR 4 2 1 2 2 Start Cycle type, direction, and size Number of clocks 1 1 1 Figure 15.2 Typical LFRAME Timing LCLK LFRAME LAD3–LAD0 Start ADDR Cycle type, direction, and size TAR Sync Slave must stop driving Master will drive high Too many Syncs cause timeout Figure 15.3 Abort Mechanism 15.4.
Regular A20 Gate Operation: Output of the A20 gate signal can be controlled by an H'D1 command followed by data. When the slave processor (this LSI) receives data, it normally uses an interrupt routine activated by the IBF1 interrupt to read IDR1. At this time, firmware copies bit 1 of data following an H'D1 command and outputs it at the gate A20 pin. Fast A20 Gate Operation: The internal state of GA20 output is initialized to 1 when FGA20E = 0.
Table 15.
15.4.4 Host Interface Shutdown Function (LPCPD) The host interface can be placed in the shutdown state according to the state of the LPCPD pin. There are two kinds of host interface shutdown state: LPC hardware shutdown and LPC software shutdown. The LPC hardware shutdown state is controlled by the LPCPD pin, while the software shutdown state is controlled by the SDWNB bit.
Table 15.5 shows the scope of the host interface pin shutdown. Table 15.
The scope of the initialization in each mode is shown in table 15.6. Table 15.
Figure 15.5 shows the timing of the LPCPD and LRESET signals. LCLK LPCPD LAD3–LAD0 LFRAME At least 30 µs At least 100 µs At least 60 µs LRESET Figure 15.5 Power-Down State Termination Timing Rev. 1.
15.4.5 Host Interface Serialized Interrupt Operation (SERIRQ) A host interrupt request can be issued from the host interface by means of the SERIRQ pin. In a host interrupt request via the SERIRQ pin, LCLK cycles are counted from the start frame of the serialized interrupt transfer cycle generated by the host or a peripheral function, and a request signal is generated by the frame corresponding to that interrupt. The timing is shown in figure 15.6.
Serial Interrupt Transfer Cycle Frame Count Contents Drive Source Number of States 0 Start Slave Host 6 1 IRQ0 Slave 3 2 IRQ1 Slave 3 Drive possible in LPC channel 1 3 SMI Slave 3 Drive possible in LPC channels 2 and 3 4 IRQ3 Slave 3 5 IRQ4 Slave 3 6 IRQ5 Slave 3 7 IRQ6 Slave 3 8 IRQ7 Slave 3 9 IRQ8 Slave 3 10 IRQ9 Slave 3 Drive possible in LPC channels 2 and 3 11 IRQ10 Slave 3 Drive possible in LPC channels 2 and 3 12 IRQ11 Slave 3 Drive possible
15.4.6 Host Interface Clock Start Request (CLKRUN) A request to restart the clock (LCLK) can be sent to the host processor by means of the CLKRUN pin. With LPC data transfer and SERIRQ in continuous mode, a clock restart is never requested since the transfer cycles are initiated by the host. With SERIRQ in quiet mode, when a host interrupt request is generated the CLKRUN signal is driven and a clock (LCLK) restart request is sent to the host. The timing for this operation is shown in figure 15.7.
15.5 Interrupt Sources 15.5.1 IBFI1, IBFI2, IBFI3, and ERRI The host interface has four interrupt requests for the slave processor (this LSI): IBF1, IBF2, IBF3, and ERRI. IBFI1, IBFI2, and IBFI3 are IDR receive complete interrupts for IDR1, IDR2, and IDR3 and TWR, respectively. The ERRI interrupt indicates the occurrence of a special state such as an LPC reset, LPC shutdown, or transfer cycle abort. An interrupt request is enabled by setting the corresponding enable bit. Table 15.
Table 15.8 summarizes the methods of setting and clearing these bits, and figure 15.8 shows the processing flowchart. Table 15.
Slave CPU Master CPU ODR1 write Write 1 to IRQ1E1 SERIRQ IRQ1 output Interrupt initiation SERIRQ IRQ1 source clearance ODR1 read OBF1 = 0? No Yes No All bytes transferred? Hardware operation Yes Software operation Figure 15.8 HIRQ Flowchart (Example of Channel 1) Rev. 1.
15.6 Usage Notes 15.6.1 Module Stop Mode Setting LPC operation can be enabled or disabled using the module stop control register. The initial setting is for LPC operation to be halted. Register access is enabled by canceling module stop mode. For details, refer to section 20, Power-Down Modes. 15.6.
Table 15.
Section 16 A/D Converter This LSI includes a successive-approximation-type 10-bit A/D converter that allows up to six analog input channels to be selected. A/D conversion for digital input is effective as a comparator in multiple input testing. 16.1 Features • 10-bit resolution • Ιnput channels: six analog input channels • Analog conversion voltage range can be specified using the reference power supply voltage pin (AVref) as an analog reference voltage. • Conversion time: 13.
A block diagram of the A/D converter is shown in figure 16.1.
16.2 Input/Output Pins Table 16.1 summarizes the pins used by the A/D converter. The 6 analog input pins are divided into two groups consisting of four channels and two channels. Analog input pins 0 to 3 (AN0 to AN3) comprising group 0 and analog input pins 4 and 5 (AN4 and AN5) comprising group 1. The AVcc and AVss pins are the power supply pins for the analog block in the A/D converter. Table 16.
16.3 Register Descriptions The A/D converter has the following registers. • • • • • • A/D data register A (ADDRA) A/D data register B (ADDRB) A/D data register C (ADDRC) A/D data register D (ADDRD) A/D control/status register (ADCSR) A/D control register (ADCR) 16.3.1 A/D Data Registers A to D (ADDRA to ADDRD) There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
16.3.2 A/D Control/Status Register (ADCSR) ADCSR controls A/D conversion operations. Bit Bit Name Initial Value R/W Description 7 ADF 0 R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion.
Bit Initial Bit Name Value R/W Description 2 CH2 0 R/W Channel Select 2 to 0 1 CH1 0 R/W 0 CH0 0 R/W Select analog input channels. The input channel setting must be made when conversion is halted (ADST = 0). Note: 16.3.
16.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. The ADST bit can be set at the same time as the operating mode or analog input channel is changed. 16.4.
Figure 16.2 shows the operation timing. 1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4.
16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 16.3 shows the A/D conversion timing. Table 16.3 indicates the A/D conversion time. As indicated in figure 16.3, the A/D conversion time (tCONV) includes tD and the input sampling time (tSPL).
Table 16.3 A/D Conversion Time (Single Mode) CKS = 0 CKS = 1 Item Symbol Min. Typ. Max. Min. Typ. Max. A/D conversion start delay time tD 10 — 17 6 — 9 Input sampling time tSPL — 63 — — 31 — A/D conversion time tCONV 259 — 266 131 — 134 Note: 16.4.4 * Values in the table indicate the number of states. External Trigger Input Timing A/D conversion can be externally triggered.
16.5 Interrupt Sources The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 enables ADI interrupt requests while the ADF bit in ADCSR is set to 1 after A/D conversion is completed. 16.6 A/D Conversion Accuracy Definitions This LSI's A/D conversion accuracy definitions are given below.
Digital output Ideal A/D conversion characteristic H'3FF H'3FE H'3FD H'004 H'003 H'002 Quantization error H'001 H'000 1 2 1024 1024 1022 1023 FS 1024 1024 Analog input voltage Figure 16.5 A/D Conversion Accuracy Definitions Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 16.6 A/D Conversion Accuracy Definitions Rev. 1.
16.7 Usage Notes 16.7.1 Permissible Signal Source Impedance This LSI's analog input (3-V version) is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
16.7.3 Setting Range of Analog Power Supply and Other Pins If conditions shown below are not met, the reliability of this LSI may be adversely affected. • Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss ≤ ANn ≤ AVref (n = 0 to 5). • Relation between AVcc, AVss and Vcc, Vss For the relationship between AVcc, AVss and Vcc, Vss, set AVss = Vss. If the A/D converter is not used, the AVcc and AVss pins must on no account be left open.
AVCC AVref *1 2 Rin* *1 100 Ω AN0 to AN5 0.1 µF Notes: AVSS Values are reference values. 1. 10 µF 0.01 µF 2. Rin: Input impedance Figure 16.8 Example of Analog Input Protection Circuit 10 kΩ AN0 to AN5 To A/D converter 20 pF Note: * Values are reference values. Figure 16.9 Equivalent Circuit of Analog Input Pin 16.7.6 Module Stop Mode Setting A/D converter operation can be enabled or disabled using the module stop control register.
Rev. 1.
Section 17 RAM This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR).
Rev. 1.
Section 18 ROM This LSI has an on-chip ROM (flash memory). The features of the flash memory are summarized below. A block diagram of the flash memory is shown in figure 18.1. 18.1 Features • Size Product Classification ROM Capacitance ROM Address H8S/2111B 64 Kbytes H'000000 to H'00FFFF (mode 2) H'0000 to H'DFFF (mode 3) • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erase is performed in single-block units.
• Programmer mode In addition to on-board programming mode, programmer mode is supported to program or erase the flash memory using a PROM programmer. Internal address bus Internal data bus (16 bits) FLMCR1 Module bus FLMCR2 EBR1 Bus interface/controller Operating mode EBR2 Flash memory (64 Kbytes) [Legend] FLMCR1: FLMCR2: EBR1: EBR2: Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 Figure 18.1 Block Diagram of Flash Memory Rev. 1.
18.2 Mode Transitions When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an operating mode as shown in figure 18.2. In user mode, flash memory can be read but not programmed or erased. The boot, user program, and programmer modes are provided as modes to write and erase the flash memory. The differences between boot mode and user program mode are shown in table 18.1. Figure 18.3 shows the boot mode and figure 18.4 shows the user program mode.
1. Initial state The flash memory is erased at shipment. The following describes how to write over an old-version application program or data in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. SCI communication check When boot mode is entered, the boot program in this LSI (originally incorporated in the chip) is started and SCI communication is checked.
1. Initial state (1) The program that will transfer the programming/erase control program from flash memory to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer The transfer program in the flash memory is executed and the programming/erase control program is transferred to RAM.
18.3 Block Configuration Figure 18.5 shows the block configuration of flash memory. The thick lines indicate erasing units, the narrow lines indicate programming units, and the values are addresses. The flash memory is divided into 8 Kbytes (2 blocks), 16 Kbytes (1 block), 28 Kbytes (1 block), and 1 Kbyte (4 blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units starting from an address whose lower bits are H'00 or H'80.
18.4 Input/Output Pins The flash memory is controlled by means of the pins shown in table 18.2. Table 18.2 Pin Configuration Pin Name I/O Function RES Input Reset MD1 Input Sets this LSI's operating mode MD0 Input Sets this LSI's operating mode P92 Input Sets this LSI's operating mode P91 Input Sets this LSI's operating mode P90 Input Sets this LSI's operating mode TxD1 Output Serial transmit data output RxD1 Input Serial receive data input 18.
18.5.1 Flash Memory Control Register 1 (FLMCR1) FLMCR1, used together with FLMCR2, makes the flash memory transit to program mode, program-verify mode, erase mode, or erase-verify mode. For details on register setting, refer to section 18.8, Flash Memory Programming/Erasing.FLMCR1 is initialized to H'80 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode.
18.5.2 Flash Memory Control Register 2 (FLMCR2) FLMCR2 monitors the state of flash memory programming/erasing protection (error protection) and sets up the flash memory to transit to programming/erasing mode. FLMCR2 is initialized to H'00 by a reset or in hardware standby mode. The ESU and PSU bits are cleared to 0 in software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0.
18.5.3 Erase Block Registers 1 and 2 (EBR1, EBR2) EBR1 and EBR2 are used to specify the flash memory erase block. EBR1 and EBR2 are initialized to H'00 by a reset, or in hardware standby mode, software standby mode, sub-active mode, sub-sleep mode, or watch mode, or when the SWE bit in FLMCR1 is cleared to 0. Set only one bit to 1 at a time, otherwise all bits in EBR1 and EBR2 are automatically cleared to 0.
18.6 Operating Modes The flash memory is connected to the CPU via a 16-bit data bus, enabling byte data and word data to be accessed in a single state. Even addresses are connected to the upper 8 bits and odd addresses are connected to the lower 8 bits. Note that word data must start from an even address. In normal mode (mode 3), up to 56 Kbytes of ROM can be used. Table 18.
18.7.1 Boot Mode Table 18.5 shows the boot mode operations between reset end and branching to the programming control program. 1. When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. Prepare a programming control program in accordance with the description in section 18.8, Flash Memory Programming/Erasing. In boot mode, if any data exists in the flash memory (except in the case that all data are 1), all blocks in the flash memory are erased.
7. Boot mode can be cleared by a reset. Cancel the reset*2 after driving the reset pin low, waiting at least 20 states, and then setting the mode pins. Boot mode is also cleared when a WDT overflow occurs. 8. Do not change the mode pin input levels in boot mode. 9. All interrupts are disabled during programming or erasing of the flash memory. Notes: 1. Some parts of this area are reserved only for boot mode and therefore should not be used for any other purpose. 2.
Table 18.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate is Possible Host Bit Rate System Clock Frequency Range of LSI 19200 bps 8 to 10 MHz 9600 bps 4 to 10 MHz 4800 bps 4 to 10 MHz H'FFE080 ID code area*1 H'FFE088 Programming control program area*1 (2040 bytes) H'FFE880 Boot program area*2 (1920 bytes) H'FFEFFF H'FFFF00 Boot program area*2 (128 bytes) H'FFFF7F Notes: 1.
18.7.2 User Program Mode On-board programming/erasing of an individual flash memory block can also be performed in user program mode by branching to a user program/erase control program. The user must set branching conditions and provide on-board means of supplying programming data. The flash memory must contain the user program/erase control program or a program which provides the user program/erase control program from external memory.
18.8 Flash Memory Programming/Erasing A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 and FLMCR2 settings, the flash memory operates in one of the following four modes: program mode, program-verify mode, erase mode, and erase-verify mode. The programming control program in boot mode and the user program/erase control program in user program mode use these operating modes in combination to perform programming/erasing.
Write pulse application subroutine Sub-Routine Write Pulse Start of programming START WDT enable Set SWE bit in FLMCR1 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
18.8.2 Erase/Erase-Verify When erasing flash memory, the erase/erase-verify flowchart shown in figure 18.10 should be followed. 1. Prewriting (setting erase block data to all 0) is not necessary. 2. Erasing is performed in block units. Make only a single-block specification in erase block registers 1 and 2 (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn. 3. The time during which the E bit is set to 1 is the flash memory erase time. 4.
START *1 Set SWE bit in FLMCR1 Wait (x) µs *2 n=1 Set EBR1 and EBR2 *4 Enable WDT Set ESU bit in FLMCR2 Wait (y) µs *2 Start of erasing Set E bit in FLMCR1 *2 Wait (z) ms End of erasing Clear E bit in FLMCR1 *2 Wait (α) µs Clear ESU bit in FLMCR2 Wait (β) µs *2 Disable WDT Set EV bit in FLMCR1 Wait (γ) µs *2 n←n+1 Set block start address as verify address H'FF dummy write to verify address Wait (ε) µs *2 Read verify data *3 Increment address Verify data = all "1"? NG OK NG La
18.9 Program/Erase Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 18.9.1 Hardware Protection Hardware protection is a state in which programming/erasing of flash memory is forcibly disabled or aborted by a reset (including WDT overflow reset), or a transition to hardware standby mode, software standby mode, sub-active mode, sub-sleep mode or watch mode.
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase mode is aborted at the point at which the error occurred. Program mode or erase mode cannot be entered by setting the P or E bit to 1. However, because the PV and EV bit settings are retained, a transition to verify mode can be made. The error protection state can be cancelled by a reset or in hardware standby mode. 18.
18.11 Programmer Mode In programmer mode, the on-chip flash memory can be programmed/erased by a PROM programmer via a socket adapter, just like for a discrete flash memory. Use a PROM programmer that supports the Renesas 64-Kbyte flash memory on-chip MCU device*. Figure 18.11 shows a memory map in programmer mode. Note: Set the programming voltage of the PROM programmer to 3.3V. MCU mode H'000000 Programmer mode H'00000 On-chip ROM area H'00FFFF H'0FFFF Undefined value output H'1FFFF Figure 18.
18.12 Usage Notes The following lists notes on the use of on-board programming modes and programmer mode. 1. Perform programming/erasing with the specified voltage and timing. If a voltage higher than the rated voltage is applied, the product may be fatally damaged. Use a PROM programmer that supports the Renesas 64-Kbyte flash memory on-chip MCU device at 3.3 V. Do not set the programmer to HN28F101 or the programming voltage to 5.0 V. 2.
Rev. 1.
Section 19 Clock Pulse Generator This LSI incorporates a clock pulse generator, which generates the system clock (φ), bus master clock, and internal clock. The clock pulse generator consists of an oscillator, duty correction circuit, clock select circuit, medium-speed clock divider, bus master clock select circuit, subclock input circuit, and waveform forming circuit. Figure 19.1 shows a block diagram of the clock pulse generator.
19.1 Oscillator Clock pulses can be supplied either by connecting a crystal resonator, or by providing external clock input. 19.1.1 Connecting Crystal Resonator Figure 19.2 shows a typical method of connecting a crystal resonator. An appropriate damping resistance Rd, given in table 19.1, should be used. An AT-cut parallel-resonance crystal resonator should be used. Figure 19.3 shows the equivalent circuit of a crystal resonator. A resonator having the characteristics given in table 19.2 should be used.
19.1.2 External Clock Input Method Figure 19.4 shows a typical method of connecting an external clock signal. To leave the XTAL pin open, incidental capacitance should be 10 pF or less. To input an inverted clock to the XTAL pin, the external clock should be set to high in standby mode, subactive mode, subsleep mode, and watch mode. External clock input conditions are shown in table 19.3. The frequency of the external clock should be the same as that of the system clock (φ).
Table 19.3 External Clock Input Conditions VCC =3.0 to 3.6 V Item Symbol Min Max Unit Test Conditions External clock input pulse width low level tEXL 40 — ns Figure 19.5 External clock input pulse width high level tEXH 40 — ns External clock rising time tEXr — 10 ns External clock falling time tEXf — 10 ns 0.4 0.6 tcyc φ ≥ 5 MHz 80 — ns φ < 5 MHz 0.4 0.
VCC STBY 3.0 V VIH EXTAL φ (Internal and external) RES tDEXT* Note: * The external clock output stabilization delay time (tDEXT) includes a RES pulse width (tRESW). Figure 19.6 Timing of External Clock Output Stabilization Delay Time 19.2 Duty Correction Circuit The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects the duty of a clock that is output from the oscillator, and generates the system clock (φ). 19.
19.5 Subclock Input Circuit The subclock input circuit controls subclock input from the EXCL pin. To use the subclock, a 32.768-kHz external clock should be input from the EXCL pin. At this time, the P96DDR bit in P9DDR should be cleared to 0, and the EXCLE bit in LPWRCR should be set to 1. Subclock input conditions are shown in table 19.5. When the subclock is not used, subclock input should not be enabled. Table 19.5 Subclock Input Conditions Vcc = 3.0 to 3.
19.7 Clock Select Circuit The clock select circuit selects the system clock that is used in this LSI. A clock generated by an oscillator to which the EXTAL and XTAL pins are input is selected as a system clock when returning from high-speed mode, medium-speed mode, sleep mode, reset state, or standby mode. A subclock input from the EXCL pin is selected as a system clock in subactive mode, subsleep mode, or watch mode.
Rev. 1.
Section 20 Power-Down Modes For operating modes after the reset state is cancelled, this LSI has not only the normal program execution state but also seven power-down modes in which power consumption is significantly reduced. In addition, there is also module stop mode in which reduced power consumption can be achieved by individually stopping on-chip peripheral modules. • Medium-speed mode System clock frequency for the CPU operation can be selected as φ/2, φ/4, φ/8, φ/16, or φ/32.
20.1.1 Standby Control Register (SBYCR) SBYCR controls power-down modes. Bit Bit Name Initial Value R/W Description 7 SSBY 0 R/W 6 5 4 STS2 STS1 STS0 0 0 0 R/W R/W R/W 3 0 R Software Standby Specifies the operating mode to be entered after executing the SLEEP instruction.
Table 20.1 Operating Frequency and Wait Time STS2 STS1 STS0 Wait Time 10 MHz 8 MHz 6 MHz 4 MHz Unit 0 0 0 8192 states 0.8 1.0 1.3 20. ms 0 0 1 16384 states 1.6 2.0 2.7 4.1 0 1 0 32768 states 3.3 4.1 5.5 8.2 0 1 1 65536 states 6.6 8.2 10.9 16.4 1 0 0 131072 states 13.1 16.4 21.8 32.8 1 0 1 262144 states 26.2 32.8 43.6 65.6 1 1 0 Reserved 1 1 1 Reserved Shaded cells indicate the recommended specification. 20.1.
Bit Bit Name Initial Value R/W Description 6 LSON 0 R/W Low-Speed On Flag Specifies the operating mode to be entered after executing the SLEEP instruction. This bit also controls whether to shift to high-speed mode or subactive mode when watch mode is cancelled.
20.1.3 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL) MSTPCRH and MSTPCRL specify on-chip peripheral modules to shift to module stop mode in module units. Each module can enter module stop mode by setting the corresponding bit to 1.
20.2 Mode Transitions and LSI States Figure 20.1 shows the enabled mode transition diagram. The mode transition from program execution state to program halt state is performed by the SLEEP instruction. The mode transition from program halt state to program execution state is performed by an interrupt. The STBY input causes a mode transition from any state to hardware standby mode. The RES input causes a mode transition from a state other than hardware standby mode to the reset state. Table 20.
Table 20.
20.3 Medium-Speed Mode The CPU makes a transition to medium-speed mode as soon as the current bus cycle ends according to the setting of the SCK2 to SCK0 bits in SBYCR. In medium-speed mode, the CPU operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32). On-chip peripheral modules other than the bus masters always operate on the system clock (φ). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock.
20.4 Sleep Mode The CPU makes a transition to sleep mode if the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and the LSON bit in LPWRCR is cleared to 0. In sleep mode, CPU operation stops but the peripheral modules do not stop. The contents of the CPU's internal registers are retained. Sleep mode is exited by any interrupt, the RES pin, or the STBY pin. When an interrupt occurs, sleep mode is exited and interrupt exception handling starts.
When the RES pin is driven low, system clock oscillation is started. At the same time as system clock oscillation starts, the system clock is supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high after clock oscillation stabilizes, the CPU begins reset exception handling. When the STBY pin is driven low, software standby mode is cancelled and a transition is made to hardware standby mode. Figure 20.
20.6 Hardware Standby Mode The CPU makes a transition to hardware standby mode from any mode when the STBY pin is driven low. In hardware standby mode, all functions enter the reset state. As long as the prescribed voltage is supplied, on-chip RAM data is retained. The I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low.
20.7 Watch Mode The CPU makes a transition to watch mode when the SLEEP instruction is executed in high-speed mode or subactive mode with the SSBY bit in SBYCR set to 1, the DTON bit in LPWRCR cleared to 0, and the PSS bit in TCSR (WDT_1) set to 1. In watch mode, the CPU is stopped and peripheral modules other than WDT_1 are also stopped.
20.8 Subsleep Mode The CPU makes a transition to subsleep mode when the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR cleared to 0, the LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. In subsleep mode, the CPU is stopped. Peripheral modules other than TMR_0, TMR_1, WDT_0, and WDT_1 are also stopped.
20.9 Subactive Mode The CPU makes a transition to subactive mode when the SLEEP instruction is executed in highspeed mode with the SSBY bit in SBYCR set to 1, the DTON bit and LSON bit in LPWRCR set to 1, and the PSS bit in TCSR (WDT_1) set to 1. When an interrupt occurs in watch mode, and if the LSON bit in LPWRCR is 1, a direct transition is made to subactive mode. Similarly, if an interrupt occurs in subsleep mode, a transition is made to subactive mode.
20.10 Module Stop Mode Module stop mode can be individually set for each on-chip peripheral module. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. In turn, when the corresponding MSTP bit is cleared to 0, module stop mode is cancelled and the module operation resumes at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and PWM are retained.
20.12 Usage Notes 20.12.1 I/O Port Status The status of the I/O ports is retained in software standby mode. Therefore, when a high level is output, the current consumption is not reduced by the amount of current to support the high level output. 20.12.2 Current Consumption when Waiting for Oscillation Stabilization The current consumption increases during oscillation stabilization. Rev. 1.
Section 21 List of Registers The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. 1. • • • • 2. • • • • 3. • • 4. • • Register Addresses (address order) Registers are listed from the lower allocation addresses. The MSB-side address is indicated for 16-bit addresses. Registers are classified by functional modules. The access size is indicated.
21.1 Register Addresses (Address Order) The data bus width indicates the numbers of bits by which the register is accessed. The number of access states indicates the number of states based on the specified reference clock.
Number of Access States Register Name Abbreviation Number of Bits Address Module Data Bus Width Bidirectional data register 1 TWR1 8 H'FE21 LPC 8 3 Bidirectional data register 2 TWR2 8 H'FE22 LPC 8 3 Bidirectional data register 3 TWR3 8 H'FE23 LPC 8 3 Bidirectional data register 4 TWR4 8 H'FE24 LPC 8 3 Bidirectional data register 5 TWR5 8 H'FE25 LPC 8 3 Bidirectional data register 6 TWR6 8 H'FE26 LPC 8 3 Bidirectional data register 7 TWR7 8 H'FE27 LPC 8
Number of Access States Number of Bits Address Module Data Bus Width Wakeup event interrupt mask register WUEMRB B 8 H'FE44 INT 8 3 Port G output data register PGODR 8 H'FE46 PORT 8 3 Port G input data register PGPIN 8 H'FE47 (read) PORT 8 3 Port G data direction register PGDDR 8 H'FE47 (write) PORT 8 3 Port E output data register PEODR 8 H'FE48 PORT 8 3 Port F output data register PFODR 8 H'FE49 PORT 8 3 Port E input data register PEPIN 8 H'FE4A (read) PORT
Data Bus Width Number of Access States Register Name Abbreviation Number of Bits Address Module Keyboard control register H_1 KBCRH_1 8 H'FEDC 8 Keyboard buffer controller_1 2 Keyboard control register L_1 KBCRL_1 8 H'FEDD 8 Keyboard buffer controller_1 2 Keyboard data buffer register_1 KBBR_1 8 H'FEDE 8 Keyboard buffer controller_1 2 Keyboard control register H_2 KBCRH_2 8 H'FEE0 8 Keyboard buffer controller_2 2 Keyboard control register L_2 KBCRL_2 8 H'FEE1 8 Keyboard bu
Register Name Abbreviation Number of Bits Address Module Data Bus Width Low power control register LPWRCR 8 H'FF85 SYSTEM 8 Number of Access States 2 Module stop control register H MSTPCRH 8 H'FF86 SYSTEM 8 2 Module stop control register L MSTPCRL 8 H'FF87 SYSTEM 8 2 Serial mode register_1 SMR_1 8 H'FF88 SCI_1 8 2 I C bus control register_1 ICCR_1 8 H'FF88 IIC_1 8 2 Bit rate register_1 BRR_1 8 H'FF89 SCI_1 8 2 2 2 I C bus status register_1 ICSR_1 8 H'FF89
Register Name Abbreviation Number of Bits Address Module Data Bus Width Output control register AFL OCRAFL 8 H'FF9B FRT 8 Number of Access States 2 Input capture register CH ICRCH 8 H'FF9C FRT 8 2 Output compare register DMH OCRDMH 8 H'FF9C FRT 8 2 Input capture register CL ICRCL 8 H'FF9D FRT 8 2 Output compare register DML OCRDML 8 H'FF9D FRT 8 2 Input capture register DH ICRDH 8 H'FF9E FRT 8 2 Input capture register DL ICRDL 8 H'FF9F FRT 8 2 Timer con
Number of Access States Address Module Data Bus Width 8 H'FFBD (write) PORT 8 2 P7PIN 8 H'FFBE (read) PORT 8 2 Port B data direction register PBDDR 8 H'FFBE (write) PORT 8 2 Port 8 data register P8DR 8 H'FFBF PORT 8 2 Port 9 data direction register P9DDR 8 H'FFC0 PORT 8 2 Register Name Abbreviation Number of Bits Port 8 data direction register P8DDR Port 7 input data register Port 9 data register P9DR 8 H'FFC1 PORT 8 2 Interrupt enable register IER 8 H'FFC
Number of Access States 2 Abbreviation Number of Bits Address Module Data Bus Width ICMR_0 8 H'FFDF IIC_0 8 Slave address register_0 SAR_0 8 H'FFDF IIC_0 8 2 A/D data register AH ADDRAH 8 H'FFE0 A/D converter 8 2 A/D data register AL ADDRAL 8 H'FFE1 A/D converter 8 2 A/D data register BH ADDRBH 8 H'FFE2 A/D converter 8 2 A/D data register BL ADDRBL 8 H'FFE3 A/D converter 8 2 A/D data register CH ADDRCH 8 H'FFE4 A/D converter 8 2 A/D data register CL ADDR
Number of Access States 2 Register Name Abbreviation Number of Bits Address Module Data Bus Width Input capture register F TICRF 8 H'FFF3 TMR_X 16 Time constant register B_Y TCORB_Y 8 H'FFF3 TMR_Y 16 2 Timer counter_X TCNT_X 8 H'FFF4 TMR_X 16 2 Timer counter_Y TCNT_Y 8 H'FFF4 TMR_Y 16 2 Timer constant register C TCORC 8 H'FFF5 TMR_X 16 2 Timer input select register TISR 8 H'FFF5 TMR_Y 16 2 Timer constant register A_X TCORA_X 8 H'FFF6 TMR_X 16 2 Timer co
21.2 Register Bits Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers 8 bits, and 16-bit registers are shown as 2 lines.
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TWR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LPC TWR2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TWR3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TWR4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TWR5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TWR6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TWR7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module WUEMRB WUEMR7 WUEMR6 WUEMR5 WUEMR4 WUEMR3 WUEMR2 WUEMR1 WUEMR0 INT PGODR PG7ODR PG6ODR PG5ODR PG4ODR PG3ODR PG2ODR PG1ODR PG0ODR PORT PGPIN PG7PIN PG6PIN PG5PIN PG4PIN PG3PIN PG2PIN PG1PIN PG0PIN PGDDR PG7DDR PG6DDR PG5DDR PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR PEODR PE7ODR PE6ODR PE5ODR PE4ODR PE3ODR PE2ODR PE1ODR PE0ODR PFODR PF7ODR PF6ODR PF5ODR PF4ODR PF3ODR PF2ODR PF1
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module ICRA ICRA7 ICRA6 ICRA5 ICRA4 ICRA3 ICRA2 ICRA1 ICRA0 INT ICRB ICRB7 ICRB6 ICRB5 ICRB4 ICRB3 ICRB2 ICRB1 ICRB0 ICRC ICRC7 ICRC6 ICRC5 ICRC4 ICRC3 ICRC2 ICRC1 ICRC0 ISR IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F ISCRH IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA ABRKCR CMF —
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — FRT TCSR ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA FRCH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 FRCL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OCRAH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 OCRBH Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 OCRAL Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR PORT PAPIN PA7PIN PA6PIN PA5PIN PA4PIN PA3PIN PA2PIN PA1PIN PA0PIN PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR P1PCR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR P2PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TCR_1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_0, TMR_1 TCSR_0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 TCSR_1 CMFB CMFA OVF — OS3 OS2 OS1 OS0 TCORA_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCORA_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCORB_0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register Abbreviation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TCR_X CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_X TCR_Y CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR_Y KMIMR KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0 INT TCSR_X CMFB CMFA OVF ICF OS3 OS2 OS1 OS0 TMR_X TCSR_Y CMFB CMFA OVF ICIE OS3 OS2 OS1 OS0 TMR_Y KMPCR KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR PORT TICRR Bit 7 Bit 6 Bit
21.
Register High-Speed/ Abbrevia- MediumSpeed SubWatch Active Sub-Sleep Stop Software Hardware Standby Standby Module — — LPC — — Reset TWR6 — — — — — — — TWR7 — — — — — — — TWR8 — — — — — — — — — TWR9 — — — — — — — — — TWR10 — — — — — — — — — TWR11 — — — — — — — — — TWR12 — — — — — — — — — TWR13 — — — — — — — — — TWR14 — — — — — — — — — TWR15 — — — — — — — — — IDR3 — — — — — — — — — ODR3
Register High-Speed/ Abbrevia- Medium- Software Hardware tion Reset Speed Watch Sleep SubActive Sub-Sleep Stop Module Standby Standby Module WUEMRB Initialized — — — — — — — Initialized INT PGODR Initialized — — — — — — — Initialized PORT PGPIN — — — — — — — — — PGDDR Initialized — — — — — — — Initialized PEODR Initialized — — — — — — — Initialized PFODR Initialized — — — — — — — Initialized PEPIN — — — — — — — — — PEDD
Register High-Speed/ Abbrevia- Medium- Software Hardware tion Reset Speed Watch Sleep SubActive Sub-Sleep Stop Standby Standby Module ICRA Initialized — — — — — — — Initialized INT ICRB Initialized — — — — — — — Initialized ICRC Initialized — — — — — — — Initialized ISR Initialized — — — — — — — Initialized ISCRH Initialized — — — — — — — Initialized ISCRL Initialized — — — — — — — Initialized ABRKCR Initialized — — — — — —
Register High-Speed/ Abbrevia- Medium- Software Hardware tion Reset Speed Watch Sleep SubActive Sub-Sleep Stop Module Standby Standby Module TIER Initialized — — — — — — — Initialized FRT TCSR Initialized — — — — — — — Initialized FRCH Initialized — — — — — — — Initialized FRCL Initialized — — — — — — — Initialized OCRAH Initialized — — — — — — — Initialized OCRBH Initialized — — — — — — — Initialized OCRAL Initialized — — —
Register High-Speed/ Abbrevia- Medium- Sub- Module Software Hardware Standby Standby Module — Initialized PORT — — tion Reset Speed Watch Sleep Active Sub-Sleep Stop PAODR Initialized — — — — — — PAPIN — — — — — — — PADDR Initialized — — — — — — — Initialized P1PCR Initialized — — — — — — — Initialized P2PCR Initialized — — — — — — — Initialized P3PCR Initialized — — — — — — — Initialized P1DDR Initialized — — — — — — —
Register High-Speed/ Abbrevia- Medium- Software Hardware tion Reset Speed Watch Sleep SubActive Sub-Sleep Stop Module Standby Standby Module TCR_0 Initialized — — — — — — — Initialized TMR_0, TCR_1 Initialized — — — — — — — Initialized TCSR_0 Initialized — — — — — — — Initialized TCSR_1 Initialized — — — — — — — Initialized TCORA_0 Initialized — — — — — — — Initialized TCORA_1 Initialized — — — — — — — Initialized TCORB_0 Initial
High-Speed/ Register Medium- Software Hardware tion Reset Speed Watch Sleep Active Sub-Sleep Stop Standby Standby Module TCR_X Initialized — — — — — — — Initialized TMR_X TCR_Y Initialized — — — — — — — Initialized TMR_Y KMIMR Initialized — — — — — — — Initialized INT TCSR_X Initialized — — — — — — — Initialized TMR_X TCSR_Y Initialized — — — — — — — Initialized TMR_Y KMPCR Initialized — — — — — — — Initialized PORT TICRR Init
21.
Lower Address H'FE20 Register Name Register Select Condition Module Name TWR0MW MSTP0 = 0 LPC TWR0SW H'FE21 TWR1 H'FE22 TWR2 H'FE23 TWR3 H'FE24 TWR4 H'FE25 TWR5 H'FE26 TWR6 H'FE27 TWR7 H'FE28 TWR8 H'FE29 TWR9 H'FE2A TWR10 H'FE2B TWR11 H'FE2C TWR12 H'FE2D TWR13 H'FE2E TWR14 H'FE2F TWR15 H'FE30 IDR3 H'FE31 ODR3 H'FE32 STR3 H'FE34 LADR3H H'FE35 LADR3L H'FE36 SIRQCR0 H'FE37 SIRQCR1 H'FE38 IDR1 H'FE39 ODR1 H'FE3A STR1 H'FE3C IDR2 H'FE3D ODR2 H'FE3E ST
Lower Address Register Name Register Select Condition Module Name H'FE44 WUEMRB No condition INT H'FE46 PGODR No condition PORT H'FE47 PGPIN (read) No condition IIC_0 PGDDR (write) H'FE48 PEODR H'FE49 PFODR H'FE4A PEPIN (read) PEDDR (write) H'FE4B PFPIN (read) PFDDR (write) H'FE4C PCODR H'FE4D PDODR H'FE4E PCPIN (read) PCDDR (write) H'FE4F PDPIN (read) H'FED4 ICXR_0 H'FED5 ICXR_1 H'FED8 KBCRH_0 H'FED9 KBCRL_0 H'FEDA KBBR_0 H'FEDC KBCRH_1 H'FEDD KBCRL_1 PDDDR (wr
Lower Address Register Name Register Select Condition Module Name No condition INT FLSHE = 1 in STCR FLASH H'FEE8 ICRA H'FEE9 ICRB H'FEEA ICRC H'FEEB ISR H'FEEC ISCRH H'FEED ISCRL H'FEF4 ABRKCR H'FEF5 BARA H'FEF6 BARB H'FEF7 BARC H'FF80 FLMCR1 H'FF81 FLMCR2 H'FF82 PCSR FLSHE = 0 in STCR PWM EBR1 FLSHE = 1 in STCR FLASH H'FF83 SYSCR2 FLSHE = 0 in STCR SYSTEM EBR2 FLSHE = 1 in STCR FLASH H'FF84 SBYCR FLSHE = 0 in STCR SYSTEM H'FF85 LPWRCR H'FF86 MSTPCRH IIC
Lower Address H'FF94 Register Name Register Select Condition OCRAH MSTP13 = 0 OCRBH H'FF95 OCRS = 0 in TOCR OCRAL OCRS = 0 in TOCR OCRBL OCRS = 1 in TOCR TCR H'FF97 TOCR H'FF98 ICRAH ICRS = 0 in TOCR OCRARH ICRS = 1 in TOCR ICRAL ICRS = 0 in TOCR OCRARL ICRS = 1 in TOCR H'FF9A H'FF9B H'FF9C H'FF9D ICRBH ICRS = 0 in TOCR OCRAFH ICRS = 1 in TOCR ICRBL ICRS = 0 in TOCR OCRAFL ICRS = 1 in TOCR ICRCH ICRS = 0 in TOCR OCRDMH ICRS = 1 in TOCR ICRCL ICRS = 0 in TOCR OCRDML ICR
Lower Address Register Name Register Select Condition Module Name No condition PORT H'FFAA PAODR H'FFAB PAPIN (read) H'FFAC P1PCR H'FFAD P2PCR PADDR (write) H'FFAE P3PCR H'FFB0 P1DDR H'FFB1 P2DDR H'FFB2 P1DR H'FFB3 P2DR H'FFB4 P3DDR H'FFB5 P4DDR H'FFB6 P3DR H'FFB7 P4DR H'FFB8 P5DDR H'FFB9 P6DDR H'FFBA P5DR H'FFBB P6DR H'FFBC PBODR H'FFBD P8DDR (write) PBPIN (read) H'FFBE P7PIN (read) PBDDR (write) H'FFBF P8DR H'FFC0 P9DDR H'FFC1 P9DR H'FFC2 IER No condi
Lower Address Register Name Register Select Condition Module Name MSTP12 = 0 TMR_0, TMR_1 No condition PWM H'FFC8 TCR_0 H'FFC9 TCR_1 H'FFCA TCSR_0 H'FFCB TCSR_1 H'FFCC TCORA_0 H'FFCD TCORA_1 H'FFCE TCORB_0 H'FFCF TCORB_1 H'FFD0 TCNT_0 H'FFD1 TCNT_1 H'FFD3 PWOERA H'FFD5 PWDPRA H'FFD6 PWSL H'FFD7 PWDR0 to PWDR7 H'FFD8 ICCR_0 H'FFD9 ICSR_0 H'FFDE ICDR_0 SARX_0 H'FFDF ICMR_0 SAR_0 H'FFE0 ADDRAH H'FFE1 ADDRAL H'FFE2 ADDRBH H'FFE3 ADDRBL H'FFE4 ADDRCH H'FFE5
Lower Address Register Name Register Select Condition Module Name H'FFEA TCSR_1 No condition WDT_1 TCNT_1 (write) H’FFEB TCNT_1 (read) H'FFF0 TCR_X TCR_Y H'FFF1 H'FFF2 H'FFF3 TMR_X TMRX/Y = 1 in TCONRS TMR_Y MSTP2 = 0, HIE = 0 in SYSCR INT TCSR_X TMRX/Y = 0 in TCONRS TMR_X TCSR_Y MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 1 in TCONRS TMR_Y KMPCR MSTP2 = 0, HIE = 1 in SYSCR PORT TICRR TMRX/Y = 0 in TCONRS TMR_X TCORA_Y MSTP8 = 0, HIE = 0 in SYSCR TMRX/Y = 1 in TCONRS TMR_Y KMIM
Section 22 Electrical Characteristics 22.1 Absolute Maximum Ratings Table 22.1 lists the absolute maximum ratings. Table 22.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC, VCL VCCB Vin –0.3 to +4.3 –0.3 to +7.0 –0.3 to VCC +0.3 V V V Vin Vin Vin AVref AVCC VAN Topr Topr –0.3 to VCCB +0.3 –0.3 to +7.0 –0.3 to AVCC + 0.3 –0.3 to AVCC + 0.3 –0.3 to +4.3 –0.3 to AVCC +0.
22.2 DC Characteristics Table 22.2 lists the DC characteristics. Permitted output current values and bus drive characteristics are shown in tables 22.3 and 22.4, respectively. Table 22.2 DC Characteristics (1) Conditions: VCC = 3.0 V to 3.6 V*7, VCCB = 3.0 V to 5.5 V, AVCC*1 = 3.0 V to 3.6 V, AVref*1 = 3.
Symbol Min. Typ. Max. Unit Test Conditions VOL — — 0.4 V IOL = 1.6 mA Ports 1 to 3 — — 1.0 V IOL = 5 mA RESO — — 0.4 V IOL = 1.6 mA Item Output low voltage All output pins 5 (except RESO)* Notes: 1. Do not leave the AVcc, AVref, and AVss pins open even if the A/D converter is not used. Even if the A/D converter is not used, apply a value in the range 2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref ≤ AVCC. 2.
Table 22.2 DC Characteristics (2) Conditions: VCC = 3.0 V to 3.6 V*5, VCCB = 3.0 V to 5.5 V, AVCC*1 = 3.0 V to 3.6 V, AVref*1 = 3.0 V to AVCC, VSS = AVSS*1 = 0 V, Ta = –20 to +75°C Symbol Min. Typ. Max. Test Unit Conditions Iin — — 10.0 µA STBY, NMI, MD1, MD0 — — 1.0 Port 7 — — 1.0 ITSI — — 1.0 µA Vin = 0.5 to VCC – 0.5 V, Vin = 0.5 to VCCB – 0.5 V –IP 5 — 150 µA 30 — 300 30 — 600 Vin = 0 V, VCC = 3.0 V to 3.6 V VCCB = 3.0 V to 5.
Typ. Max. Test Unit Conditions 3.0 — 3.6 V 2.0 — 3.6 2.0 — — Item Symbol Min. Analog power supply voltage*1 AVCC RAM standby voltage VRAM Operating Idle/not used V Notes: 1. Do not leave the AVCC, AVref, and AVSS pins open even if the A/D converter is not used. Even if the A/D converter is not used, apply a value in the range 2.0 V to 3.6 V to AVCC and AVref pins by connection to the power supply (VCC), or some other method. Ensure that AVref ≤ AVCC. 2.
Table 22.3 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Item Permissible output low current (per pin) Symbol Min. Typ. Max.
This LSI 600 Ω Ports 1 to 3 LED Figure 22.2 LED Drive Circuit (Example) Table 22.4 Bus Drive Characteristics Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = –20 to +75°C Applicable Pins: SCL1, SCL0, SDA1, SDA0 ExSDAA, ExSCLA, ExSDAB, ExSCLB (bus drive function selected) Min. Typ. Max. Test Unit Conditions VCC × 0.3 — — V VT+ — — VCC × 0.7 VCC = 3.0 V to 3.6 V VT+ – VT– VCC × 0.05 — — VCC = 3.0 V to 3.6 V Input high voltage VIH VCC × 0.7 — 5.5 Input low voltage VIL –0.
Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, Ta = –20 to +75°C Applicable Pins: PS2AC, PS2AD, PS2BC, PS2BD, PS2CC, PS2CD, PA7 to PA4 (bus drive function selected) Item Symbol Min. Typ. Max. Unit Test Conditions Output low voltage VOL — — 0.8 V — — 0.5 IOL = 8 mA — — 0.4 IOL = 3 mA 22.3 IOL = 16 mA, VCCB = 4.5 V to 5.5 V AC Characteristics Figure 22.3 shows the test conditions for the AC characteristics.
22.3.1 Clock Timing Table 22.5 shows the clock timing. The clock timing specified here covers clock (φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details on external clock input (EXTAL pin and EXCL pin) timing, see section19, Clock Pulse Generator. Table 22.5 Clock Timing Condition: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 4 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Symbol Min.
22.3.2 Control Signal Timing Table 22.6 shows the control signal timing. The only external interrupts that can operate on the subclock (φ = 32.768 kHz) are NMI and IRQ0, 1, 2, 6, and 7. Table 22.6 Control Signal Timing Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.768 kHz, 4 MHz to maximum operating frequency, Ta = –20 to +75°C Condition 10 MHz Item Symbol Min. Max. Unit Test Conditions RES setup time tRESS 300 — ns Figure 22.
22.3.3 Timing of On-Chip Peripheral Modules Tables 22.7 to 22.10 show the on-chip peripheral module timing. The only on-chip peripheral modules that can operate in subclock operation (φ = 32.768 kHz) are the I/O ports, external interrupts (NMI and IRQ0, 1, 2, 6, and 7), the watchdog timer, and the 8-bit timer (channels 0 and 1). Table 22.7 Timing of On-Chip Peripheral Modules (1) Conditions: VCC = 3.0 V to 3.6 V, VCCB = 3.0 V to 5.5 V, VSS = 0 V, φ = 32.
Condition 10 MHz Symbol Min. Max. Test Unit Conditions tTXD — 100 ns Receive data setup time tRXS (synchronous) 100 — ns Receive data hold time (synchronous) 100 — ns A/D Trigger input setup time tTRGS converter 50 — ns Figure 22.19 RESO output delay time tRESD — 200 ns Figure 22.20 RESO output pulse width 132 — tcyc Item SCI Transmit data delay time (synchronous) WDT Note: * tRXH tRESOW Figure 22.
Table 22.9 I2C Bus Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency, Ta = –20 to +75°C Ratings Item Symbol Min. Typ. Max. Unit SCL input cycle time tSCL 12 — — tcyc SCL input high pulse width tSCLH 3 — — tcyc SCL input low pulse width tSCLL 5 — — tcyc SCL, SDA input rise time tSr — — 7.
Table 22.10 LPC Module Timing Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, φ = 4 MHz to maximum operating frequency, Ta = –20 to +75°C Symbol Min. Typ. Max. Test Unit Conditions tLcyc 30 — — ns Input clock pulse width (H) tLCKH 11 — — Input clock pulse width (L) 11 — — Item LPC 22.
22.5 Flash Memory Characteristics Table 22.12 shows the flash memory characteristics. Table 22.12 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, VSS = 0 V, Ta = –20 to +75°C Item Test Condition Symbol Min. Typ. Max.
Item Erase Symbol Min. Typ. Max.
22.6 Usage Note The method of connecting an external capacitor is shown in figure 22.4. Connect the system power supply to the VCL pin together with the VCC pins. Vcc power supply VCL Bypass capacitor 10 µF 0.01 µF VSS < Vcc = 3.0 V to 3.6 V > Connect the Vcc power supply to the chip's VCL pin in the same way as the VCC pins. It is recommended that a bypass capacitor be connected to the power supply pins. (Values are reference values.) Figure 22.4 Connection of VCL Capacitor 22.7 Timing Chart 22.
EXTAL tDEXT tDEXT VCC STBY tOSC1 tOSC1 RES φ Figure 22.6 Oscillation Settling Timing φ NMI IRQi (i = 0, 1, 2, 6, 7) tOSC2 Figure 22.7 Oscillation Setting Timing (Exiting Software Standby Mode) Rev. 1.
22.7.2 Control Signal Timing The control signal timings are shown below. φ tRESS tRESS RES tRESW Figure 22.8 Reset Input Timing φ tNMIH tNMIS NMI tNMIW IRQi (i = 7 to 0) tIRQW tIRQS IRQi Edge input (i = 7 to 0) tIRQH tIRQS IRQi Level input (i = 7 to 0) Figure 22.9 Interrupt Input Timing Rev. 1.
22.7.3 On-Chip Peripheral Module Timing The on-chip peripheral module timings are shown below. T2 T1 φ tPRS Ports 1 to 9, and A to G (read) tPRH tPWD Ports 1 to 6, 8, 9, and A to G (write) Figure 22.10 I/O Port Input/Output Timing φ tFTOD FTOA, FTOB tFTIS FTIA, FTIB, FTIC, FTID Figure 22.11 FRT Input/Output Timing φ tFTCS FTCI tFTCWL tFTCWH Figure 22.12 FRT Clock Input Timing Rev. 1.
φ tTMOD TMO0, TMO1 TMOX, ExTMOX, TMOY, TMOA, TMOB Figure 22.13 8-Bit Timer Output Timing φ tTMCS TMCI0, TMCI1 TMIX, TMIY, ExTMIX, ExTMIY, TMIA, TMIB tTMCWL tTMCS tTMCWH Figure 22.14 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 TMIX, TMIY, ExTMIX, ExTMIY, TMIA, TMIB Figure 22.15 8-Bit Timer Reset Input Timing φ tPWOD PW7 to PW0 Figure 22.16 PWM, PWMX Output Timing Rev. 1.
tSCKW tSCKr tSCKf SCK1, ExSCK1 tScyc Figure 22.17 SCK Clock Input Timing SCK1, ExSCK1 tTXD TxD1, ExTxD1 (transmit data) tRXS tRXH RxD1, ExRxD1 (receive data) Figure 22.18 SCI Input/Output Timing (Synchronous Mode) φ tTRGS ADTRG Figure 22.19 A/D Converter External Trigger Input Timing φ tRESD tRESD RESO tRESOW Figure 22.20 WDT Output Timing (RESO) Rev. 1.
1. Reception φ tKBIS tKBIH KCLK/KD* T1 2. Transmission (a) T2 φ tKBOD KCLK/KD* Transmission (b) KCLK/KD* tKBF Note: φ shown here is the clock scaled by 1/N when the operating mode is active medium-speed mode. * KCLK: PS2AC to PS2CC KD: PS2AD to PS2CD Figure 22.
tLCKH tLcyc LCLK tLCKL LCLK tTXD LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) tRXS tRXH LAD3 to LAD0, SERIRQ, CLKRUN LFRAME (Receive signal) tOFF LAD3 to LAD0, SERIRQ, CLKRUN (Transmit signal) Figure 22.23 Host Interface (LPC) Timing Testing voltage: 0.4Vcc 50pF Figure 22.24 Tester Measurement Condition Rev. 1.
Appendix A. I/O Port States in Each Processing State Table A.
B. Product Codes Product Type H8S/2111B-B H8S/2111B-C Product Code Flash memory version HD64F2111BVB (3 V version) HD64F2111BVC Rev. 1.
C. Package Dimensions For package dimensions, dimensions described in Renesas Semiconductor Packages Data Book have priority. Unit: mm 18.0 ± 0.2 16 108 73 72 0.4 18.0 ± 0.2 109 144 37 1 *0.18 ± 0.05 0.16 ± 0.04 0.08 *Dimension including the plating thickness Base material dimension 0.10 ± 0.05 0.15 ± 0.04 *0.17 ± 0.05 1.0 1.00 0.07 M 1.20 Max 36 1.0 0˚ – 8˚ 0.5 ± 0.1 Package Code JEDEC EIAJ Weight (reference value) TFP-144 — Conforms 0.6 g Figure C.
Rev. 1.
Index 16-bit count mode................................... 210 16-bit free-running timer (FRT) ............. 157 8-bit PWM timer (PWM)........................ 147 8-bit timer (TMR) ................................... 183 A/D converter ......................................... 413 A20 gate.................................................. 398 Absolute address....................................... 41 Additional pulse...................................... 154 Address map ......................................
ICIX........................................................ 215 IICI ......................................................... 337 Immediate ................................................. 42 Increment timing .................................... 170 Input capture input.................................. 172 Input capture operation........................... 212 Instruction set ........................................... 29 Interrupt control modes ............................ 80 Interrupt controller.......
ICXR....................302, 482, 491, 499, 507 IDR ......................380, 481, 490, 498, 506 IER.........................73, 486, 494, 502, 510 ISCR ......................72, 483, 492, 500, 508 ISR.........................73, 483, 492, 500, 508 KBBR ..................354, 482, 491, 499, 507 KBCR ..................351, 482, 491, 499, 507 KMIMR .................73, 487, 496, 504, 512 KMIMRA ..............73, 487, 496, 504, 512 KMPCR ...............113, 487, 496, 504, 512 LADR3 ................
TCONRI ..............203, 488, 496, 504, 512 TCONRS .............203, 488, 496, 504, 512 TCOR ..................191, 486, 495, 503, 511 TCORC................202, 488, 496, 504, 512 TCR ....................166, 192, 484, 486, 493, .............................495, 501, 503, 509, 511 TCRAB............................................... 205 TCRXY .............................................. 204 TCSR ..................163, 196, 224, 484, 485, ............................486, 493, 495, 501, 503, ..............
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2111B Publication Date: Rev.1.00, May 14, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd.. 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str.
H8S/2111B Hardware Manual
