User manual

Rev. 1.00, 05/04, page 378 of 544
R/W
Bit Bit Name
Initial
Value Slave Host Description
3 IBFIE3 0 R/W — IDR3 and TWR Receive Completion Interrupt Enable
Enables or disables IBFI3 interrupt to the slave
processor (this LSI).
0: Input data register IDR3 and TWR receive completed
interrupt requests disabled
1: [When TWRIE = 0 in LADR3]
Input data register (IDR3) receive completed interrupt
requests enabled
[When TWRIE = 1 in LADR3]
Input data register (IDR3) and TWR receive completed
interrupt requests enabled
2 IBFIE2 0 R/W — IDR2 Receive Completion Interrupt Enable
Enables or disables IBFI2 interrupt to the slave
processor (this LSI).
0: Input data register (IDR2) receive completed interrupt
requests disabled
1: Input data register (IDR2) receive completed interrupt
requests enabled
1 IBFIE1 0 R/W — IDR1 Receive Completion Interrupt Enable
Enables or disables IBFI1 interrupt to the slave
processor (this LSI).
0: Input data register (IDR1) receive completed interrupt
requests disabled
1: Input data register (IDR1) receive completed interrupt
requests enabled
0 ERRIE 0 R/W — Error Interrupt Enable
Enables or disables ERRI interrupt to the slave
processor (this LSI).
0: Error interrupt requests disabled
1: Error interrupt requests enabled
Note: * Only 0 can be written to bits 6 to 4, to clear the flag.
• HICR3
R/W
Bit Bit Name Initial Value Slave Host Description
7 LFRAME Undefined R — LFRAME Pin Monitor
6 CLKRUN Undefined R — CLKRUN Pin Monitor
5 SERIRQ Undefined R — SERIRQ Pin Monitor
4 LRESET Undefined R — LRESET Pin Monitor
3 LPCPD Undefined R — LPCPD Pin Monitor
2 PME Undefined R — PME Pin Monitor
1 LSMI Undefined R — LSMI Pin Monitor
0 LSCI Undefined R — LSCI Pin Monitor