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R10DS0151EJ0100 Rev.1.00 Page 1 of 12

2013.6.21

R1LP0108E Series

1Mb Advanced LPSRAM (128k word x 8bit)

Description

The R1LP0108E Series is a family of low voltage 1-Mbit static RAMs organized as 131,072-word by 8-bit, fabricated

by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LP0108E Series has realized higher

density, higher performance and low power consumption. The R1LP0108E Series is suitable for memory applications

where a simple interfacing, battery operating and battery backup are the important design objectives. It has been

packaged in 32-pin SOP,32-pin TSOP and 32-pin sTSOP.

Features

 Single 4.5~5.5V power supply

 Small stand-by current: 0.6µA (5.0V, typical)

 No clocks, No refresh

 All inputs and outputs are TTL compatible.

 Easy memory expansion by CS1# and CS2

 Common Data I/O

 Three-state outputs: OR-tie Capability

 OE# prevents data contention on the I/O bus

R10DS0151EJ0100

Rev.1.00

2013.6.21

Summary of content (14 pages)

PAGE 1
R1LP0108E Series 1Mb Advanced LPSRAM (128k word x 8bit) R10DS0151EJ0100 Rev.1.00 2013.6.21 Description The R1LP0108E Series is a family of low voltage 1-Mbit static RAMs organized as 131,072-word by 8-bit, fabricated by Renesas’s high-performance 0.15um CMOS and TFT technologies. The R1LP0108E Series has realized higher density, higher performance and low power consumption.
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R1LP0108E Series Ordering Information Orderable Part Name R1LP0108ESN-5SR#B* R1LP0108ESN-5SI#B* R1LP0108ESN-7SR#B* R1LP0108ESN-7SI#B* R1LP0108ESN-5SR#S* R1LP0108ESN-5SI#S* R1LP0108ESN-7SR#S* R1LP0108ESN-7SI#S* R1LP0108ESA-5SR#B* R1LP0108ESA-5SI#B* R1LP0108ESA-7SR#B* R1LP0108ESA-7SI#B* R1LP0108ESA-5SR#S* R1LP0108ESA-5SI#S* R1LP0108ESA-7SR#S* R1LP0108ESA-7SI#S* R1LP0108ESF-5SR#B* R1LP0108ESF-5SI#B* R1LP0108ESF-7SR#B* R1LP0108ESF-7SI#B* R1LP0108ESF-5SR#S* R1LP0108ESF-5SI#S* R1LP0108ESF-7SR#S* R1LP0108ESF-7SI#
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R1LP0108E Series Pin Arrangement NC A16 A14 A12 A7 A6 A5 A4 32 Vcc 2 31 A15 3 30 CS2 4 29 WE# 5 28 A13 6 27 A8 7 26 A9 25 A11 9 24 OE# 10 23 A10 11 22 CS1# 12 21 DQ7 13 20 DQ6 14 19 DQ5 15 18 DQ4 16 17 DQ3 8 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND R10DS0151EJ0100 Rev.1.00 2013.6.
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R1LP0108E Series Pin Description Pin name Function Vcc Power supply Vss A0 to A16 DQ0 to DQ7 CS1# CS2 WE# OE# NC Ground Address input Data input/output Chip select 1 Chip select 2 Write enable Output enable Non connection Block Diagram A0 A1 ADDRESS ROW MEMORY ARRAY BUFFER DECODER 128k-word x8-bit A16 DQ0 DQ DQ1 BUFFER SENSE / WRITE AMPLIFIER DQ7 COLUMN DECODER CLOCK GENERATOR WE# Vcc Vss CS1# CS2 OE# R10DS0151EJ0100 Rev.1.00 2013.6.
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R1LP0108E Series Operation Table CS1# CS2 WE# OE# DQ0~7 Operation X L X X High-Z Stand-by H X X X High-Z Stand-by L H L X Din Write L H H L Dout Read L H H H High-Z Output disable Note 1. H: VIH L:VIL X: VIH or VIL Absolute Maximum Parameter Power supply voltage relative to Vss Terminal voltage on any pin relative to Vss Power dissipation Operation temperature Storage temperature range Storage temperature range under bias Note Symbol Vcc VT PT Topr*3 Value -0.
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R1LP0108E Series DC Operating Conditions Parameter Symbol Min. Typ. Max. Unit Vcc 4.5 5.0 5.5 V Supply voltage Note Vss 0 0 0 V Input high voltage VIH 2.2 - Vcc+0.3 V Input low voltage VIL -0.3 - 0.8 V 1 0 - +70 °C 2 -40 - +85 °C 2 Ambient temperature range Note R Ver. Ta I Ver. 1. –3.0V for pulse ≤ 30ns (full width at half maximum) 2. Ambient temperature range depends on R/I-version. Please see table on page 1.
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R1LP0108E Series AC Characteristics Test Conditions (Vcc = 4.5V ~ 5.5V, Ta = 0 ~ +70°C / -40 ~ +85°C*1)     Input pulse levels: VIL = 0.6V, VIH = 2.4V Input rise and fall time: 5ns Input and output timing reference level: 1.5V Output load: See figures (Including scope and jig) 1.5V RL = 500 ohm DQ Note CL = 30 pF ( -5SI, -5SR) CL = 100 pF ( -7SI, -7SR) 1. Ambient temperature range depends on R/I-version. Please see table on page 1. R10DS0151EJ0100 Rev.1.00 2013.6.
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R1LP0108E Series Read Cycle Parameter Read cycle time Address access time Chip select access time Output enable to output valid Output hold from address change Chip select to output in low-Z Output enable to output in low-Z Chip deselect to output in high-Z Output disable to output in high-Z Symbol tRC tAA tACS1 tACS2 tOE tOH tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ R1LP0108E**-5** R1LP0108E**-7** Min. 55 5 5 5 5 0 0 0 Min. 70 10 10 10 5 0 0 0 Max. 55 55 55 30 20 20 20 Max.
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R1LP0108E Series Timing Waveforms Read Cycle tRC A0~16 tOH tAA tACS1 CS1# tCLZ1 CS2 tCHZ1 tACS2 tCLZ2 WE# tCHZ2 VIH WE# = “H” level tOE OE# tOLZ tOHZ High impedance DQ0~7 R10DS0151EJ0100 Rev.1.00 2013.6.
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R1LP0108E Series Write Cycle (1) (WE# CLOCK) tWC A0~16 tCW CS1# tCW CS2 tAW tAS tWP tWR WE# OE# tWHZ tOLZ tOHZ DQ0~7 tOW Valid Data tDW R10DS0151EJ0100 Rev.1.00 2013.6.
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R1LP0108E Series Write Cycle (2) (CS1#, CS2 CLOCK) tWC A0~16 tAW tAS tCW tWR tAS tCW tWR CS1# CS2 tWP WE# OE# VIH OE# = “H” level tDW DQ0~7 R10DS0151EJ0100 Rev.1.00 2013.6.
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R1LP0108E Series Low Vcc Data Retention Characteristics Parameter Symbol VCC for data retention VDR Min. Typ. Max. Test conditions*2 Unit 2.0 - 5.5 V Vin ≥ 0V (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V - 0.6*1 2 A ~+25°C Vcc=3.0V, Vin ≥ 0V Data retention current - - 3 A ~+40°C - - 8 A ~+70°C - - 10 A ~+85°C ICCDR (1) 0V ≤ CS2 ≤ 0.2V or (2) CS1# ≥ Vcc-0.2V, CS2 ≥ Vcc-0.2V Chip deselect time to data retention tCDR 0 ns See retention waveform.
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Revision History R1LP0108E Series Data Sheet Description Rev. Date 1.00 2013.6.21 Page - Summary First Edition issued All trademarks and registered trademarks are the property of their respective owners.
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Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2.