Datasheet

Rev. 2.00 Sep. 28, 2009 Page viii of xl
REJ09B0429-0200
2.7.6 Immediate⎯#xx:8, #xx:16, or #xx:32.................................................................... 47
2.7.7 Program-Counter Relative⎯@(d:8, PC) or @(d:16, PC)....................................... 47
2.7.8 Memory Indirect⎯@@aa:8 ................................................................................... 48
2.7.9 Effective Address Calculation ................................................................................ 49
2.8 Processing States.................................................................................................................. 51
2.9 Usage Note........................................................................................................................... 53
2.9.1 Notes on Using the Bit Operation Instruction......................................................... 53
Section 3 MCU Operating Modes .....................................................................55
3.1 Operating Mode Selection ................................................................................................... 55
3.2 Register Descriptions ...........................................................................................................56
3.2.1 Mode Control Register (MDCR) ............................................................................ 56
3.2.2 System Control Register (SYSCR)......................................................................... 57
3.2.3 Serial Timer Control Register (STCR) ................................................................... 58
3.3 Operating Mode Descriptions.............................................................................................. 60
3.3.1 Mode 2.................................................................................................................... 60
3.4 Address Map........................................................................................................................ 61
Section 4 Exception Handling ...........................................................................63
4.1 Exception Handling Types and Priority............................................................................... 63
4.2 Exception Sources and Exception Vector Table.................................................................. 64
4.3 Reset .................................................................................................................................... 66
4.3.1 Reset Exception Handling ...................................................................................... 66
4.3.2 Interrupts after Reset............................................................................................... 67
4.3.3 On-Chip Peripheral Modules after Reset is Cancelled............................................ 67
4.4 Interrupt Exception Handling............................................................................................... 68
4.5 Trap Instruction Exception Handling................................................................................... 68
4.6 Stack Status after Exception Handling................................................................................. 69
4.7 Usage Note........................................................................................................................... 70
Section 5 Interrupt Controller............................................................................71
5.1 Features................................................................................................................................ 71
5.2 Input/Output Pins................................................................................................................. 72
5.3 Register Descriptions ...........................................................................................................73
5.3.1 Interrupt Control Registers A to D (ICRA to ICRD).............................................. 73
5.3.2 Address Break Control Register (ABRKCR) ......................................................... 74
5.3.3 Break Address Registers A to C (BARA to BARC)............................................... 75
5.3.4 IRQ Sense Control Registers (ISCR16H, ISCR16L, ISCRH, ISCRL)................... 76
5.3.5 IRQ Enable Registers (IER16, IER) ....................................................................... 78
5.3.6 IRQ Status Registers (ISR16, ISR)......................................................................... 79