Datasheet

Section 3 MCU Operating Modes
Rev. 2.00 Sep. 28, 2009 Page 58 of 870
REJ09B0429-0200
Bit Bit Name
Initial
Value
R/W Description
3 XRST 1 R External Reset
This bit indicates the reset source. A reset is caused by an
external reset input, or when the watchdog timer
overflows.
0: A reset is caused when the watchdog timer
overflows.
1: A reset is caused by an external reset.
2 NMIEG 0 R/W NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
1 — 0 R/W Reserved
The initial value should not be changed.
0 RAME 1 R/W RAM Enable
Enables or disables on-chip RAM. The RAME bit is
initialized when the reset state is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
3.2.3 Serial Timer Control Register (STCR)
STCR enables or disables register access, IIC operating mode, and on-chip flash memory, and
selects the input clock of the timer counter.
Bit Bit Name
Initial
Value
R/W Description
7
6
5
IICX2
IICX1
IICX0
0
0
0
R/W
R/W
R/W
IIC Transfer Rate Select 2, 1, and 0
These bits control the IIC operation. These bits select a
transfer rate in master mode together with bits CKS2 to
CKS0 in the I
2
C bus mode register (ICMR). For details on
the transfer rate, see table 17.3. The IICXn bit controls
IIC_n. (n = 0 to 2)