Datasheet

Rev. 2.00 Sep. 28, 2009 Page ix of xl
REJ09B0429-0200
5.4 Interrupt Sources.................................................................................................................. 80
5.4.1 External Interrupts .................................................................................................. 80
5.4.2 Internal Interrupts ................................................................................................... 81
5.5 Interrupt Exception Handling Vector Table......................................................................... 82
5.6 Interrupt Control Modes and Interrupt Operation ................................................................ 84
5.6.1 Interrupt Control Mode 0........................................................................................ 86
5.6.2 Interrupt Control Mode 1........................................................................................ 88
5.6.3 Interrupt Exception Handling Sequence ................................................................. 91
5.6.4 Interrupt Response Times ....................................................................................... 93
5.6.5 DTC Activation by Interrupt................................................................................... 94
5.7 Usage Notes ......................................................................................................................... 96
5.7.1 Conflict between Interrupt Generation and Disabling ............................................ 96
5.7.2 Instructions that Disable Interrupts......................................................................... 97
5.7.3 Interrupts during Execution of EEPMOV Instruction............................................. 97
5.7.4 IRQ Status Registers (ISR16, ISR) ......................................................................... 97
Section 6 Bus Controller (BSC).........................................................................99
6.1 Features................................................................................................................................ 99
6.2 Input/Output Pins............................................................................................................... 102
6.3 Register Descriptions ......................................................................................................... 103
6.3.1 Bus Control Register (BCR) ................................................................................. 103
6.3.2 Bus Control Register 2 (BCR2) ............................................................................ 105
6.3.3 Wait State Control Register (WSCR) ................................................................... 106
6.3.4 Wait State Control Register 2 (WSCR2) .............................................................. 108
6.3.5 System Control Register 2 (SYSCR2) .................................................................. 109
6.4 Bus Control........................................................................................................................ 110
6.4.1 Bus Specifications................................................................................................. 110
6.4.2 Advanced Mode.................................................................................................... 117
6.4.3 I/O Select Signals.................................................................................................. 118
6.5 Bus Interface ...................................................................................................................... 119
6.5.1 Data Size and Data Alignment.............................................................................. 119
6.5.2 Valid Strobes......................................................................................................... 121
6.5.3 Valid Strobes (in Glueless Extension) .................................................................. 122
6.5.4 Basic Operation Timing in Normal Extended Mode ............................................ 123
6.5.5 Basic Operation Timing in Address-Data Multiplex Extended Mode .................. 134
6.5.6 Wait Control ......................................................................................................... 142
6.6 Burst ROM Interface.......................................................................................................... 146
6.6.1 Basic Operation Timing........................................................................................ 146
6.6.2 Wait Control ......................................................................................................... 147
6.7 Idle Cycle........................................................................................................................... 148