Datasheet

Section 5 Interrupt Controller

Rev. 2.00 Sep. 28, 2009 Page 81 of 870

REJ09B0429-0200

IRQn interrupt

request

IRQnE

IRQnF

Clear signal

Edge/level

detection circuit

IRQnSCA, IRQnSCB

IRQn input or

ExIRQn* input

n = 15 to 0

Figure 5.2 Block Diagram of Interrupts IRQ15 to IRQ0

5.4.2 Internal Interrupts

Internal interrupts issued from the on-chip peripheral modules have the following features:

• For each on-chip peripheral module there are flags that indicate the interrupt request status,

and enable bits that individually select enabling or disabling of these interrupts. When the

enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt

controller.

• The control level for each interrupt can be set by ICR.

• The DTC can be activated by an interrupt request from an on-chip peripheral module.

• An interrupt request that activates the DTC is not affected by the interrupt control mode or the

status of the CPU interrupt mask bits.