Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 99 of 870
REJ09B0429-0200
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of
access states of the external address space. The BSC also has a bus arbitration function, and
controls the operation of the internal bus masters – CPU and data transfer controller (DTC).
6.1 Features
• Extended modes
Two modes for external extension
Normal extended mode: Normal extension
(when ADMXE = 0 in SYSCR2 and OBE = 0 in PTCNT0)
Glueless extension
(when ADMXE = 0 in SYSCR2 and OBE = 1 in PTCNT0)
Address-data multiplex extended mode: Multiplex extension (when ADMXE = 1 in SYSCR2)
• Extended area division
Possible in normal extended mode
The external address space can be accessed as basic extended areas.
A 256-Kbyte extended area can be set and controlled independently of basic extended areas.
• Address pin reduction
In normal extended mode:
A 256-Kbyte extended area from H'F80000 to H'FBFFFF can be selected using 18 address
pins and the CS256 signal.
A 2-Kbyte area from H'FFF000 to H'FFF7FF can be selected using six to eleven address pins
and the IOS signal.
In address-data multiplex extended mode:
The external address space can be accessed as the following two extended areas.
H'F80000 to H'F8FFFF 64 Kbytes 256-Kbyte extended area
H'FFF000 to H'FFF7FF 2 Kbytes IOS extended area
These areas can be selected using 8 pins or 16 pins, which is a total of address pins and data
input/output pins.
• Control address hold signal and area select signal polarity
The output polarity of IOS, CS256, and AH can be inverted by the PNCCS and PNCAH bits in
LPWRCR