Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 103 of 870
REJ09B0429-0200
6.3 Register Descriptions
The following registers are provided for the bus controller. For the system control register
(SYSCR), see section 3.2.2, System Control Register (SYSCR). For port control register 0
(PTCNT0), see section 8.16.2, Port Control Register 0 (PTCNT0).
• Bus control register (BCR)
• Bus control register 2 (BCR2)
• Wait state control register (WSCR)
• Wait state control register 2 (WSCR2)
• System control register 2 (SYSCR2)
6.3.1 Bus Control Register (BCR)
BCR is used to specify the access mode for the external address space and the I/O area range when
the AS/IOS pin is specified as an I/O strobe pin.
Bit Bit Name
Initial
Value
R/W Description
7 ⎯ 1 R/W Reserved
The initial value should not be changed.
6 ICIS 1 R/W Idle Cycle Insertion
Selects whether or not to insert 1-state of the idle cycle
between successive external read and external write
cycles.
0: Idle cycle not inserted
1: 1-state idle cycle inserted
5 BRSTRM 0 R/W Valid only in the normal extended mode.
Burst ROM Enable
Selects the bus interface for the external address space.
0: Basic bus interface
1: Burst ROM interface
When the CS256E bit in SYSCR is set to 1, burst ROM
interface cannot be selected for the 256-Kbyte extended
area.