Datasheet

Rev. 2.00 Sep. 28, 2009 Page xiii of xl
REJ09B0429-0200
8.15.1 Port F Data Direction Register (PFDDR) ............................................................. 249
8.15.2 Port F Output Data Register (PFODR) ................................................................. 249
8.15.3 Port F Input Data Register (PFPIN)...................................................................... 250
8.15.4 Pin Functions ........................................................................................................ 250
8.16 Change of Peripheral Function Pins................................................................................... 251
8.16.1 IRQ Sense Port Select Register 16 (ISSR16),
IRQ Sense Port Select Register (ISSR)................................................................. 251
8.16.2 Port Control Register 0 (PTCNT0) ....................................................................... 253
Section 9 14-Bit PWM Timer (PWMX)..........................................................255
9.1 Features.............................................................................................................................. 255
9.2 Input/Output Pins............................................................................................................... 256
9.3 Register Descriptions ......................................................................................................... 256
9.3.1 PWMX (D/A) Counter (DACNT) ........................................................................ 257
9.3.2 PWMX (D/A) Data Registers A and B (DADRA and DADRB).......................... 258
9.3.3 PWMX (D/A) Control Register (DACR) ............................................................. 260
9.3.4 Peripheral Clock Select Register (PCSR) ............................................................. 261
9.4 Bus Master Interface.......................................................................................................... 262
9.5 Operation ........................................................................................................................... 263
Section 10 16-Bit Free-Running Timer (FRT) ..................................................271
10.1 Features.............................................................................................................................. 271
10.2 Register Descriptions ......................................................................................................... 273
10.2.1 Free-Running Counter (FRC) ............................................................................... 273
10.2.2 Output Compare Registers A and B (OCRA and OCRB) .................................... 273
10.2.3 Output Compare Registers AR and AF (OCRAR and OCRAF) .......................... 274
10.2.4 Timer Interrupt Enable Register (TIER)............................................................... 275
10.2.5 Timer Control/Status Register (TCSR)................................................................. 276
10.2.6 Timer Control Register (TCR).............................................................................. 277
10.2.7 Timer Output Compare Control Register (TOCR) ............................................... 278
10.3 Operation Timing............................................................................................................... 279
10.3.1 FRC Increment Timing ......................................................................................... 279
10.3.2 Output Compare Output Timing........................................................................... 279
10.3.3 FRC Clear Timing ................................................................................................ 280
10.3.4 Timing of Output Compare Flag (OCF) Setting................................................... 280
10.3.5 Timing of FRC Overflow Flag (OVF) Setting...................................................... 281
10.3.6 Automatic Addition Timing.................................................................................. 282
10.4 Interrupt Sources................................................................................................................ 282
10.5 Usage Notes ....................................................................................................................... 283
10.5.1 Conflict between FRC Write and Clear ................................................................ 283