Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 112 of 870
REJ09B0429-0200
Table 6.3 Bit Settings and Bus Specifications of Basic Bus Interface
Areas
BRSTRM CS256E Basic Extended Area 256-Kbyte Extended Area
0 Used as basic extended area 0
1
Basic extended area
ABW, AST,
WMS1, WMS0,
WC1, WC0
ABW256, AST256, WMS10,
WC11, WC10
0 Used as burst ROM interface 1
1
Burst ROM interface*
ABW, AST, WMS0, WC1, WC0,
BRSTS1, BRSTS0
ABW256, AST256, WMS10,
WC11, WC10
Note: * In the burst ROM interface, the bus width is specified by the ABW bit in WSCR, the
number of full access states (wait can be inserted) is specified by the AST bit in WSCR,
and the number of access cycles in burst access is specified regardless of the AST bit
setting.
Table 6.4 Bus Specifications for Basic Extended Area/Basic Bus Interface
Bus Specifications
ABW AST WMS1 WMS0 WC1 WC0 Bus Width
Number of
Access
States
Number of
Program
Wait
States
0 X X X X 16 2 0
0 1 X X 3 0
0 0 0
1 1
0 2
0
1
Other than
WMS1 = 0 and
WMS0 = 1
1
1
16
3
3
0 X X X X 8 2 0
0 1 X X 3 0
0 0 0
1 1
0 2
1
1
Other than
WMS1 = 0 and
WMS0 = 1
1
1
8
3
3
[Legend]
X: Don't care