Datasheet

Rev. 2.00 Sep. 28, 2009 Page xiv of xl
REJ09B0429-0200
10.5.2 Conflict between FRC Write and Increment......................................................... 284
10.5.3 Conflict between OCR Write and Compare-Match .............................................. 285
10.5.4 Switching of Internal Clock and FRC Operation.................................................. 286
Section 11 8-Bit Timer (TMR).......................................................................... 289
11.1 Features.............................................................................................................................. 289
11.2 Register Descriptions......................................................................................................... 292
11.2.1 Timer Counter (TCNT)......................................................................................... 292
11.2.2 Time Constant Register A (TCORA).................................................................... 293
11.2.3 Time Constant Register B (TCORB) .................................................................... 293
11.2.4 Timer Control Register (TCR).............................................................................. 294
11.2.5 Timer Control/Status Register (TCSR)................................................................. 297
11.2.6 Timer Connection Register S (TCONRS) ............................................................ 301
11.3 Operation Timing............................................................................................................... 302
11.3.1 TCNT Count Timing ............................................................................................ 302
11.3.2 Timing of CMFA and CMFB Setting at Compare-Match .................................... 302
11.3.3 Timing of Counter Clear at Compare-Match........................................................ 303
11.3.4 Timing of Overflow Flag (OVF) Setting .............................................................. 303
11.4 TMR_0 and TMR_1 Cascaded Connection....................................................................... 304
11.4.1 16-Bit Count Mode............................................................................................... 304
11.4.2 Compare-Match Count Mode ............................................................................... 304
11.5 Interrupt Sources................................................................................................................ 305
11.6 Usage Notes ....................................................................................................................... 306
11.6.1 Conflict between TCNT Write and Counter Clear ............................................... 306
11.6.2 Conflict between TCNT Write and Increment...................................................... 307
11.6.3 Conflict between TCOR Write and Compare-Match............................................ 308
11.6.4 Switching of Internal Clocks and TCNT Operation ............................................. 309
11.6.5 Mode Setting with Cascaded Connection ............................................................. 310
Section 12 Watchdog Timer (WDT) .................................................................311
12.1 Features.............................................................................................................................. 311
12.2 Input/Output Pins............................................................................................................... 313
12.3 Register Descriptions......................................................................................................... 313
12.3.1 Timer Counter (TCNT)......................................................................................... 313
12.3.2 Timer Control/Status Register (TCSR)................................................................. 314
12.4 Operation ........................................................................................................................... 318
12.4.1 Watchdog Timer Mode......................................................................................... 318
12.4.2 Interval Timer Mode............................................................................................. 320
12.4.3 RESO Signal Output Timing ................................................................................ 321
12.5 Interrupt Sources................................................................................................................ 322