Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 123 of 870
REJ09B0429-0200
6.5.4 Basic Operation Timing in Normal Extended Mode
(1) 8-Bit, 2-State Access Space
Figure 6.5 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is
accessed, the upper half (D15 to D8) of the data bus is used. Wait states cannot be inserted.
Bus cycle
T
1
T
2
Address bus
φ
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS (IOSE = 0)
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
*
HWR
D15 to D8
Valid
Write
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.5 Bus Timing for 8-Bit, 2-State Access Space