Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 127 of 870
REJ09B0429-0200
Bus cycle
T
1
T
2
Address bus
φ
AS (IOSE = 0)
RD
D15 to D8
Valid
D7 to D0
Valid
Read
*
HWR
LWR
D15 to D8
Valid
D7 to D0
Valid
Write
IOS (IOSE = 1)
CS256 (CS256E = 1)
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.9 Bus Timing for 16-Bit, 2-State Access Space (Word Access)