Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 134 of 870
REJ09B0429-0200
6.5.5 Basic Operation Timing in Address-Data Multiplex Extended Mode
(1) 8-Bit, 2-State Data Access Space
Figures 6.16 and 6.17 show the bus timing for an 8-bit, 2-state access space. When an 8-bit access
space is accessed, the upper half (AD15 to AD8) of the data bus is used. Wait states cannot be
inserted.
Read Cycle
Address Data
Data
Address Data
Write Cycle
T
1
T
2
T
3
T
AW
T
4
T
1
T
2
T
3
T
AW
T
4
φ
CS256
IOS
AH
RD
HWR
AD15 to AD8
Address Address
Data
Figure 6.16 Bus Timing for 8-Bit, 2-State Access Space