Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 135 of 870
REJ09B0429-0200
Read Cycle
Address Data Address Data
Write Cycle
T
1
T
2
T
3
T
4
T
1
T
2
T
3
T
4
CS256
IOS
AH
RD
HWR
AD15 to AD8
φ
Address Address
Data
Data
Figure 6.17 Bus Timing for 8-Bit, 2-State Access Space
(2) 8-Bit, 3-State Data Access Space
Figure 6.18 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is
accessed, the upper half (AD15 to AD8) of the data bus is used. Wait states can be inserted.
Read Cycle
Address Data Data
Data
Write Cycle
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
Address
CS256
IOS
AH
RD
HWR
AD15 to AD8
φ
Address Address
Data
Figure 6.18 Bus Timing for 8-Bit, 3-State Access Space