Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 136 of 870
REJ09B0429-0200
(3) 16-Bit, 2-State Data Access Space
Figures 6.19 to 6.24 show bus timings for a 16-bit, 2-state access space. When a 16-bit access
space is accessed, the upper half (AD15 to AD8) of the data bus is used for even addresses, and
the lower half (AD7 to AD0) for odd addresses. Wait states cannot be inserted.
Read Cycle
Address Data Data
Write Cycle
T
1
T
2
T
3
T
AW
T
4
Address
T
1
T
2
T
3
T
AW
T
4
CS256
IOS
AH
RD
HWR
LWR
AD15 to AD8
AD7 to AD0
φ
Address Address
Data Data
Address Address
Figure 6.19 Bus Timing for 16-Bit, 2-State Access Space (1) (Even Byte Access)