Datasheet

Rev. 2.00 Sep. 28, 2009 Page xvi of xl
REJ09B0429-0200
13.7.1 Sample Connection ............................................................................................... 374
13.7.2 Data Format (Except in Block Transfer Mode) .................................................... 374
13.7.3 Block Transfer Mode............................................................................................ 376
13.7.4 Receive Data Sampling Timing and Reception Margin ....................................... 377
13.7.5 Initialization.......................................................................................................... 378
13.7.6 Serial Data Transmission (Except in Block Transfer Mode) ................................ 379
13.7.7 Serial Data Reception (Except in Block Transfer Mode) ..................................... 382
13.7.8 Clock Output Control............................................................................................ 384
13.8 Interrupt Sources................................................................................................................ 386
13.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 386
13.8.2 Interrupts in Smart Card Interface Mode .............................................................. 387
13.9 Usage Notes ....................................................................................................................... 388
13.9.1 Module Stop Mode Setting ................................................................................... 388
13.9.2 Break Detection and Processing ........................................................................... 388
13.9.3 Mark State and Break Sending ............................................................................. 388
13.9.4 Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ......................................................................... 388
13.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 388
13.9.6 Restrictions on Using DTC................................................................................... 389
13.9.7 SCI Operations during Mode Transitions ............................................................. 390
13.9.8 Notes on Switching from SCK Pins to Port Pins .................................................. 394
Section 14 CRC Operation Circuit (CRC) ........................................................ 397
14.1 Features.............................................................................................................................. 397
14.2 Register Descriptions......................................................................................................... 398
14.2.1 CRC Control Register (CRCCR) .......................................................................... 398
14.2.2 CRC Data Input Register (CRCDIR).................................................................... 399
14.2.3 CRC Data Output Register (CRCDOR)................................................................ 399
14.3 CRC Operation Circuit Operation...................................................................................... 399
14.4 Note on CRC Operation Circuit......................................................................................... 403
Section 15 Serial Communication Interface with FIFO (SCIF)........................405
15.1 Features.............................................................................................................................. 405
15.2 Input/Output Pins............................................................................................................... 407
15.3 Register Descriptions......................................................................................................... 408
15.3.1 Receive Shift Register (FRSR) ............................................................................. 409
15.3.2 Receive Buffer Register (FRBR) .......................................................................... 409
15.3.3 Transmitter Shift Register (FTSR)........................................................................ 409
15.3.4 Transmitter Holding Register (FTHR).................................................................. 410
15.3.5 Divisor Latch H, L (FDLH, FDLL) ...................................................................... 410