Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 140 of 870
REJ09B0429-0200
(4) 16-Bit, 3-State Data Access Space
Figures 6.25 to 6.27 show bus timings for a 16-bit, 3-state access space. When a 16-bit access
space is accessed, the upper half (AD15 to AD8) of the data bus is used for even addresses, and
the lower half (AD7 to AD0) for odd addresses. Wait states can be inserted.
Read Cycle
Address Data Data
Write Cycle
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
T
1
T
2
T
3
T
AW
T
5
T
DSW
T
4
Address
CS256
IOS
AH
RD
HWR
LWR
AD7 to AD0
AD15 to AD8
φ
Address Address
Address Address
Data Data
Figure 6.25 Bus Timing for 16-Bit, 3-State Access Space (1) (Even Byte Access)