Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 145 of 870
REJ09B0429-0200
Read Cycle
Data Data
Write Cycle
T
5
T
DSW
T
DOW
T
DOW
T
3
T
4
T
5
T
DSW
T
DOW
T
DOW
T
3
T
4
CS256
IOS
WAIT
AH
RD
HWR
LWR
AD7 to AD0
Data
Data
AD15 to AD8
φ
Data
Data
Figure 6.29 Example of Wait State Insertion Timing
