Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 149 of 870
REJ09B0429-0200
Table 6.15 shows the pin states in an idle cycle.
Table 6.15 Pin States in Idle Cycle
Pins Pin State
A23 to A0 Contents of immediately following bus cycle
D15 to D0 High impedance
AS, IOS, CS256 High
RD High
HWR, LWR High
6.8 Bus Arbitration
6.8.1 Overview
The BSC has a bus arbiter that arbitrates bus master operations. There are two bus masters – the
CPU and DTC – that perform read/write operations while they have bus mastership.
6.8.2 Operation
Each bus master requests the bus mastership by means of a bus mastership request signal. The bus
arbiter detects the bus mastership request signal from the bus masters, and if a bus request occurs,
it sends a bus mastership request acknowledge signal to the bus master that made the request at the
designated timing. If there are bus requests from more than one bus master, the bus mastership
request acknowledge signal is sent to the one with the highest priority. When a bus master receives
the bus mastership request acknowledge signal, it takes the bus mastership until that signal is
canceled. The order of bus master priority is as follows:
(High) DTC > CPU (Low)