Datasheet

Section 6 Bus Controller (BSC)
Rev. 2.00 Sep. 28, 2009 Page 150 of 870
REJ09B0429-0200
6.8.3 Bus Mastership Transfer Timing
When a bus request is received from a bus master with a higher priority than that of the bus master
that has acquired the bus mastership and is currently operating, the bus mastership is not
necessarily transferred immediately. Each bus master can relinquish the bus mastership at the
timings given below.
(1) CPU
The CPU is the lowest-priority bus master, and if a bus mastership request is received from the
DTC, the bus arbiter transfers the bus mastership to the DTC. The timing for transferring the bus
mastership is as follows:
• Bus mastership is transferred at a break between bus cycles. However, if bus cycle is executed
in discrete operations, as in the case of a long-word size access, the bus is not transferred at a
break between the operations. For details see section 2.7, Bus States During Instruction
Execution in the H8S/2600 Series, H8S/2000 Series Software Manual.
• If the CPU is in sleep mode, it transfers the bus mastership immediately.
(2) DTC
The DTC sends the bus arbiter a request for the bus mastership when a request for DTC activation
occurs. The DTC releases the bus mastership after a series of processes has completed.