Datasheet

Rev. 2.00 Sep. 28, 2009 Page xviii of xl
REJ09B0429-0200
17.2 Input/Output Pins............................................................................................................... 452
17.3 Register Descriptions......................................................................................................... 453
17.3.1 I
2
C Bus Data Register (ICDR) .............................................................................. 453
17.3.2 Slave Address Register (SAR).............................................................................. 454
17.3.3 Second Slave Address Register (SARX) .............................................................. 455
17.3.4 I
2
C Bus Mode Register (ICMR)............................................................................ 457
17.3.5 I
2
C Bus Transfer Rate Select Register (IICX3)..................................................... 459
17.3.6 I
2
C Bus Control Register (ICCR).......................................................................... 462
17.3.7 I
2
C Bus Status Register (ICSR)............................................................................. 471
17.3.8 I
2
C Bus Extended Control Register (ICXR).......................................................... 475
17.3.9 I
2
C SMBus Control Register (ICSMBCR)............................................................ 479
17.4 Operation ........................................................................................................................... 481
17.4.1 I
2
C Bus Data Format ............................................................................................. 481
17.4.2 Initialization.......................................................................................................... 483
17.4.3 Master Transmit Operation................................................................................... 483
17.4.4 Master Receive Operation .................................................................................... 487
17.4.5 Slave Receive Operation....................................................................................... 496
17.4.6 Slave Transmit Operation ..................................................................................... 504
17.4.7 IRIC Setting Timing and SCL Control ................................................................. 507
17.4.8 Operation Using the DTC ..................................................................................... 510
17.4.9 Noise Canceler...................................................................................................... 512
17.4.10 Initialization of Internal State ............................................................................... 512
17.5 Interrupt Source ................................................................................................................. 514
17.6 Usage Notes ....................................................................................................................... 515
Section 18 LPC Interface (LPC)........................................................................ 529
18.1 Features.............................................................................................................................. 529
18.2 Input/Output Pins............................................................................................................... 532
18.3 Register Descriptions......................................................................................................... 533
18.3.1 Host Interface Control Registers 0 and 1 (HICR0 and HICR1)............................ 535
18.3.2 Host Interface Control Registers 2 and 3 (HICR2 and HICR3)............................ 543
18.3.3 Host Interface Control Register 4 (HICR4) .......................................................... 546
18.3.4 Host Interface Control Register 5 (HICR5) .......................................................... 548
18.3.5 Pin Function Control Register (PINFNCR) .......................................................... 548
18.3.6 LPC Channel 1, 2 Address Register H, L (LADR12H, LADR12L)..................... 549
18.3.7 LPC Channel 3 Address Register H, L (LADR3H, LADR3L)............................. 551
18.3.8 Input Data Registers 1 to 3 (IDR1 to IDR3) ......................................................... 554
18.3.9 Output Data Registers 0 to 3 (ODR1 to ODR3) ................................................... 554
18.3.10 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15)..................................... 555
18.3.11 Status Registers 1 to 3 (STR1 to STR3) ............................................................... 556