Datasheet

Section 7 Data Transfer Controller (DTC)
Rev. 2.00 Sep. 28, 2009 Page 160 of 870
REJ09B0429-0200
Bit Bit Name
Initial
Value
R/W Description
3 to 0 ECSB3 to
ECSB0
All 0 R/W Event Counter Channel Select 3 to 0
These bits select pins for event counter input. A series
of pins are selected starting from EVENT0. When
PAnDDR is set to 1, inputting events to EVENT0 to
EVENT7 is ignored.
0000: EVENT0 is used
0001: EVENT0 to EVENT1 are used
0010: EVENT0 to EVENT2 are used
0011: EVENT0 to EVENT3 are used
0100: EVENT0 to EVENT4 are used
0101: EVENT0 to EVENT5 are used
0110: EVENT0 to EVENT6 are used
0111: EVENT0 to EVENT7 are used
1000: EVENT0 to EVENT8 are used
1001: EVENT0 to EVENT9 are used
1010: EVENT0 to EVENT10 are used
1011: EVENT0 to EVENT11 are used
1100: EVENT0 to EVENT12 are used
1101: EVENT0 to EVENT13 are used
1110: EVENT0 to EVENT14 are used
1111: EVENT0 to EVENT15 are used
7.2.11 Event Counter Status Register (ECS)
ECS is a 16-bit register that holds events temporarily. The DTC decides the counter to be
incremented according to the state of this register. Reading this register allows the monitoring of
events that are not yet counted by the event counter. Access in 8-bit unit is not allowed.
Bit Bit Name
Initial
Value
R/W Description
15 to 0 E15 to E0 All 0 R Event Monitor 15 to 0
These bits indicate processed/unprocessed states of the
events that are input to EVENT15 to EVENT0.
0: The corresponding event is already processed
1: The corresponding event is not yet processed